Talos™ II Linux sources for OpenBMC https://git.raptorcs.com/git/talos-obmc-linux/atom?h=dev-4.13 2017-08-21T07:37:33+00:00 2017-08-21T07:37:33+00:00 Dave Airlie airlied@redhat.com 2017-08-21T07:37:33+00:00 urn:sha1:3aadb888b1b62ba04798414cae431d3c3bd5f452 drm/tegra: Changes for v4.14-rc1 This contains a couple of fixes and improvements for host1x, with some preparatory work for Tegra186 support. The remainder is cleanup and minor bugfixes for Tegra DRM along with enhancements to debuggability. There have also been some enhancements to the kernel interfaces for host1x job submissions and support for mmap'ing PRIME buffers directly, all of which get the interfaces very close to ready for serious work. * tag 'drm/tegra/for-4.14-rc1' of git://anongit.freedesktop.org/tegra/linux: (21 commits) drm/tegra: Prevent BOs from being freed during job submission drm/tegra: gem: Implement mmap() for PRIME buffers drm/tegra: Support render node drm/tegra: sor: Trace register accesses drm/tegra: dpaux: Trace register accesses drm/tegra: dsi: Trace register accesses drm/tegra: hdmi: Trace register accesses drm/tegra: dc: Trace register accesses drm/tegra: sor: Use unsigned int for register offsets drm/tegra: hdmi: Use unsigned int for register offsets drm/tegra: dsi: Use unsigned int for register offsets drm/tegra: dpaux: Use unsigned int for register offsets drm/tegra: dc: Use unsigned int for register offsets drm/tegra: Fix NULL deref in debugfs/iova drm/tegra: switch to drm_*_get(), drm_*_put() helpers drm/tegra: Set MODULE_FIRMWARE for the VIC drm/tegra: Add CONFIG_OF dependency gpu: host1x: Support sub-devices recursively gpu: host1x: fix error return code in host1x_probe() gpu: host1x: Fix bitshift/mask multipliers ... 2017-08-17T15:57:18+00:00 Dmitry Osipenko digetx@gmail.com 2017-08-11T17:54:56+00:00 urn:sha1:ec73c4cfe7de6229e49989f7d7754a7039cd5c28 Since DRM IOCTL's are lockless, there is a chance that BOs could be released while a job submission is in progress. To avoid that, keep the GEM reference until the job has been pinned, part of which will be to take another reference. v2: remove redundant check and avoid memory leak Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2017-08-17T15:57:18+00:00 Thierry Reding treding@nvidia.com 2017-08-15T13:42:40+00:00 urn:sha1:a8bc8c6510d64b759644647a03f8aec55056bded The mapping of PRIME buffers can reuse much of the GEM mapping code, so extract the common bits into a new tegra_gem_mmap() helper. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Thierry Reding <treding@nvidia.com> 2017-08-17T15:57:17+00:00 Thierry Reding treding@nvidia.com 2017-08-15T13:42:39+00:00 urn:sha1:6c68b71776e760c67f10fbdbe56908793a7b1763 None of the driver-specific IOCTLs are privileged, so mark them as such and advertise that the driver supports render nodes. Signed-off-by: Thierry Reding <treding@nvidia.com> 2017-08-17T15:57:17+00:00 Thierry Reding treding@nvidia.com 2017-08-15T13:41:14+00:00 urn:sha1:932f6529139ee7279e4c241eea46402ac7275936 Add tracepoint events for SOR controller register accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> 2017-08-17T15:57:16+00:00 Thierry Reding treding@nvidia.com 2017-08-15T13:41:13+00:00 urn:sha1:eba7c4551a9b07bf68126e4f22fec4b66475f529 Add tracepoint events for DPAUX controller register accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> 2017-08-17T15:57:16+00:00 Thierry Reding treding@nvidia.com 2017-08-15T13:41:12+00:00 urn:sha1:75af8fa7fd47e8f76198e13052b42e66d9e1f233 Add tracepoint events for DSI controller register accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> 2017-08-17T15:57:15+00:00 Thierry Reding treding@nvidia.com 2017-08-15T13:41:11+00:00 urn:sha1:07a8aab89927ee58100b9a0d121dafacbcc3a5dd Add tracepoint events for HDMI controller register accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> 2017-08-17T15:57:14+00:00 Thierry Reding treding@nvidia.com 2017-08-15T13:41:10+00:00 urn:sha1:67e04d1ab19b0cc6d87ca7c44b058edf678bc3a3 Add tracepoint events for display controller register accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> 2017-08-17T15:57:14+00:00 Thierry Reding treding@nvidia.com 2017-08-15T13:41:09+00:00 urn:sha1:5c5f13016d2f4d5144418bec57a75490c5f9fc96 Register offsets are usually fairly small numbers, so an unsigned int is more than enough to represent them. Signed-off-by: Thierry Reding <treding@nvidia.com>