<feed xmlns='http://www.w3.org/2005/Atom'>
<title>talos-obmc-linux/drivers/gpu/drm/amd/amdgpu/si_ih.c, branch dev-4.13</title>
<subtitle>Talos™ II Linux sources for OpenBMC</subtitle>
<id>https://git.raptorcs.com/git/talos-obmc-linux/atom?h=dev-4.13</id>
<link rel='self' href='https://git.raptorcs.com/git/talos-obmc-linux/atom?h=dev-4.13'/>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-obmc-linux/'/>
<updated>2017-05-16T15:17:41+00:00</updated>
<entry>
<title>drm/amd: fix include notation and remove -Iinclude/drm flag</title>
<updated>2017-05-16T15:17:41+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2017-04-24T04:50:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-obmc-linux/commit/?id=248a1d6f1ac410d3ed3907c1be2502e286f59bb8'/>
<id>urn:sha1:248a1d6f1ac410d3ed3907c1be2502e286f59bb8</id>
<content type='text'>
Include &lt;drm/*.h&gt; instead of relative path from include/drm, then
remove the -Iinclude/drm compiler flag.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reviewed-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/1493009447-31524-4-git-send-email-yamada.masahiro@socionext.com
</content>
</entry>
<entry>
<title>drm/amdgpu/ih: store the full context id</title>
<updated>2017-03-30T03:53:37+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-11-29T23:02:12+00:00</published>
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<id>urn:sha1:7ccf5aa8ba8241cba0f6a894ec1e68a2794cef6f</id>
<content type='text'>
The contextID field (formerly known as src_data) of the IH
vector stores client specific information about an interrupt.
It was expanded from 32 bits to 128 on newer asics.  Expand the
src_id field to handle this.

Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: switch ih handling to two levels (v3)</title>
<updated>2017-03-30T03:53:37+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-03-29T22:28:50+00:00</published>
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<id>urn:sha1:d766e6a393383c60a55bdcc72586f21a1ff12509</id>
<content type='text'>
Newer asics have a two levels of irq ids now:
client id - the IP
src id - the interrupt src within the IP

v2: integrated Christian's comments.
v3: fix rebase fail in SI and CIK

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Reviewed-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move misc si headers into amdgpu</title>
<updated>2017-01-27T17:20:41+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-01-24T23:00:57+00:00</published>
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<id>urn:sha1:689957b12b6315c63bd8cce879e2b259a8a4b666</id>
<content type='text'>
Move these to the amdgpu directory to match what we
do for other asics.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rework IP block registration (v2)</title>
<updated>2016-10-25T18:38:45+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-10-13T21:41:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-obmc-linux/commit/?id=a12551072126758ecb0743147054f22bf233bb7d'/>
<id>urn:sha1:a12551072126758ecb0743147054f22bf233bb7d</id>
<content type='text'>
This makes it easier to replace specific IP blocks on
asics for handling virtual_dce, DAL, etc. and for building
IP lists for hw or tables.  This also stored the status
information in the same structure.

v2: split out spelling fix into a separate patch
    add a function to add IPs to the list

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Tidy up SI IH code</title>
<updated>2016-09-12T22:12:22+00:00</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2016-09-06T15:36:42+00:00</published>
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<id>urn:sha1:6e9057a8f90f3a9d662d8c0a347850e1fa331a30</id>
<content type='text'>
Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Edward O'Callaghan &lt;funfunctor@folklore1984.net&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add interupt handler implementation for si v3</title>
<updated>2016-08-31T16:10:19+00:00</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-01-19T06:02:14+00:00</published>
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<id>urn:sha1:27ae10641e9c99f32db004cc54cb0639cd58d6d1</id>
<content type='text'>
v3: rebase fixups

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
