talos-obmc-linux/drivers/crypto/Makefile, branch dev-4.13

crypto: cavium - Add support for CNN55XX adapters.

2017-06-10T04:04:33+00:00

Add Physical Function driver support for CNN55XX crypto adapters. CNN55XX adapters belongs to Cavium NITROX family series, which accelerate both Symmetric and Asymmetric crypto workloads. These adapters have crypto engines that need firmware to become operational. Signed-off-by: Srikanth Jampala Signed-off-by: Herbert Xu

crypto: inside-secure - add SafeXcel EIP197 crypto engine driver

2017-06-10T04:04:21+00:00

Add support for Inside Secure SafeXcel EIP197 cryptographic engine, which can be found on Marvell Armada 7k and 8k boards. This driver currently implements: ecb(aes), cbc(aes), sha1, sha224, sha256 and hmac(sah1) algorithms. Two firmwares are needed for this engine to work. Their are mostly used for more advanced operations than the ones supported (as of now), but we still need them to pass the data to the internal cryptographic engine. Signed-off-by: Antoine Tenart Signed-off-by: Herbert Xu

crypto: omap-aes - Add support for GCM mode

2017-06-10T04:04:19+00:00

OMAP AES hw supports AES-GCM mode. This patch adds support for GCM and RFC4106 GCM mode in omap-aes driver. The GCM implementation is mostly written into its own source file, which gets built into the same driver binary as the existing AES support. Signed-off-by: Lokesh Vutla [t-kristo@ti.com: forward port to latest upstream kernel, conversion to use omap-crypto lib and some additional fixes] Signed-off-by: Tero Kristo Signed-off-by: Herbert Xu

crypto: omap - add base support library for common routines

2017-06-10T04:04:15+00:00

This contains the generic APIs for aligning SG buffers. Signed-off-by: Tero Kristo Signed-off-by: Herbert Xu

crypto: exynos - Add new Exynos RNG driver

2017-04-21T12:30:46+00:00

Replace existing hw_ranndom/exynos-rng driver with a new, reworked one. This is a driver for pseudo random number generator block which on Exynos4 chipsets must be seeded with some value. On newer Exynos5420 chipsets it might seed itself from true random number generator block but this is not implemented yet. New driver is a complete rework to use the crypto ALGAPI instead of hw_random API. Rationale for the change: 1. hw_random interface is for true RNG devices. 2. The old driver was seeding itself with jiffies which is not a reliable source for randomness. 3. Device generates five random 32-bit numbers in each pass but old driver was returning only one 32-bit number thus its performance was reduced. Compatibility with DeviceTree bindings is preserved. New driver does not use runtime power management but manually enables and disables the clock when needed. This is preferred approach because using runtime PM just to toggle clock is huge overhead. Another difference is reseeding itself with generated random data periodically and during resuming from system suspend (previously driver was re-seeding itself again with jiffies). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Stephan Müller Reviewed-by: PrasannaKumar Muralidharan Reviewed-by: Bartlomiej Zolnierkiewicz Signed-off-by: Herbert Xu

crypto: stm32 - Support for STM32 CRC32 crypto module

2017-04-05T13:58:33+00:00

This module registers a CRC32 ("Ethernet") and a CRC32C (Castagnoli) algorithm that make use of the STMicroelectronics STM32 crypto hardware. Theses algorithms are compatible with the little-endian generic ones. Both algorithms use ~0 as default seed (key). With CRC32C the output is xored with ~0. Using TCRYPT CRC32C speed test, this shows up to 900% speedup compared to the crc32c-generic algorithm. Signed-off-by: Fabien Dessenne Signed-off-by: Herbert Xu

crypto: zip - Add ThunderX ZIP driver core

2017-03-09T10:34:25+00:00

Add a driver for the ZIP engine found on Cavium ThunderX SOCs. The ZIP engine supports hardware accelerated compression and decompression. It includes 2 independent ZIP cores and supports: - DEFLATE compression and decompression (RFC 1951) - LZS compression and decompression (RFC 2395 and ANSI X3.241-1994) - ADLER32 and CRC32 checksums for ZLIB (RFC 1950) and GZIP (RFC 1952) The ZIP engine is presented as a PCI device. It supports DMA and scatter-gather. Signed-off-by: Mahipal Challa Signed-off-by: Jan Glauber Signed-off-by: Herbert Xu

crypto: brcm - Add Broadcom SPU driver

2017-02-11T09:55:20+00:00

Add Broadcom Secure Processing Unit (SPU) crypto driver for SPU hardware crypto offload. The driver supports ablkcipher, ahash, and aead symmetric crypto operations. Signed-off-by: Steve Lin Signed-off-by: Rob Rice Signed-off-by: Herbert Xu

crypto: cavium - Enable CPT options crypto for build

2017-02-11T09:55:17+00:00

Add the CPT options in crypto Kconfig and update the crypto Makefile Update the MAINTAINERS file too. Signed-off-by: George Cherian Reviewed-by: David Daney Signed-off-by: Herbert Xu

crypto: mediatek - Add crypto driver support for some MediaTek chips

2016-12-27T09:51:30+00:00

This adds support for the MediaTek hardware accelerator on mt7623/mt2701/mt8521p SoC. This driver currently implement: - SHA1 and SHA2 family(HMAC) hash algorithms. - AES block cipher in CBC/ECB mode with 128/196/256 bits keys. Signed-off-by: Ryder Lee Signed-off-by: Herbert Xu