talos-obmc-linux/drivers/clk, branch dev-4.10

Merge tag 'v4.10.17' into dev-4.10

2017-06-05T02:24:15+00:00

This is the 4.10.17 stable release

clk/aspeed: Fix g4 clkin rate calculation

2017-05-24T05:55:51+00:00

Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Joel Stanley

clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036

2017-05-14T12:08:26+00:00

commit 9b1b23f03abdd25ffde8bbfe5824b89bc0448c28 upstream. The mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a "," between the 3rd and 4th parent names, making them fall together and thus lookups fail. Fix that. Fixes: 5190c08b2989 ("clk: rockchip: add clock controller for rk3036") Signed-off-by: Heiko Stuebner Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: Make x86/ conditional on CONFIG_COMMON_CLK

2017-05-14T12:08:24+00:00

commit f35b6542c3ac3f28056d298348a81f7d56d3a041 upstream. Fix Makefile for x86 support, dependency on CONFIG_COMMON_CLK was not explicit Fixes: 701190fd7419 ('clk: x86: add support for Lynxpoint LPSS clocks') Signed-off-by: Pierre-Louis Bossart Acked-by: Andy Shevchenko Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: mp: Adjust parent rate for pre-dividers

2017-03-30T07:44:07+00:00

commit ac8616e4c81dded650dfade49a7da283565d37ce upstream. The MP style clocks support an mux with pre-dividers. While the driver correctly accounted for them in the .determine_rate callback, it did not in the .recalc_rate and .set_rate callbacks. This means when calculating the factors in the .set_rate callback, they would be off by a factor of the active pre-divider. Same goes for reading back the clock rate after it is set. Fixes: 2ab836db5097 ("clk: sunxi-ng: Add M-P factor clock support") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock

2017-03-30T07:44:07+00:00

commit 9ad0bb39fce319d7b92c17d306ed0a9f70a02e7d upstream. The enable bit offset for the hdmi-ddc module clock is wrong. It is pointing to the main hdmi module clock enable bit. Reported-by: Bob Ham Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Signed-off-by: Greg Kroah-Hartman

clk: aspeed: fix APB and AHB clock rates

2017-03-28T09:26:06+00:00

The masking is one bit too generous which generates really low clock rates. OpenBMC-Staging-Count: 1 Signed-off-by: Cédric Le Goater Signed-off-by: Joel Stanley

clk: aspeed: Add driver for uart clock

2017-03-22T14:04:18+00:00

OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley

clk: aspeed: Add clock driver for g5 clocks

2017-03-22T14:04:17+00:00

These are the base clocks required for booting the system. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley

clk: aspeed: Add clock driver for g4 clocks

2017-03-22T14:04:17+00:00

These are the base clocks required for booting the system. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley