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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable/proc_cen_ref_clk_enable_errors.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- COPYRIGHT International Business Machines Corp. 2013,2014 -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- $Id: proc_cen_ref_clk_enable_errors.xml,v 1.2 2014/02/28 17:53:41 jmcgill Exp $ -->
<!-- Error definitions for proc_cen_ref_clk_enable -->
<hwpErrors>
<!-- *********************************************************************** -->
<hwpError>
<rc>RC_PROC_CEN_REF_CLK_ENABLE_SWIZZLE_ERR</rc>
<description>Translated Centaur refclock enable bit position is out of range.</description>
<ffdc>PROC_TARGET</ffdc>
<ffdc>CENTAUR_POSITION</ffdc>
<ffdc>REFCLOCK_BIT</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
<hwpError>
<rc>RC_PROC_CEN_REF_CLK_ENABLE_CONFIG_ERR</rc>
<description>Not all Centaurs marked as attached were configured.</description>
<ffdc>PROC_TARGET</ffdc>
<ffdc>CONFIGURED_CENTAUR_POSITIONS</ffdc>
<ffdc>ATTACHED_CENTAUR_POSITIONS</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>
</hwpErrors>
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