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<!-- IBM_PROLOG_BEGIN_TAG
This is an automatically generated prolog.
$Source: src/usr/hwpf/hwp/common_attributes.xml $
IBM CONFIDENTIAL
COPYRIGHT International Business Machines Corp. 2012
p1
Object Code Only (OCO) source materials
Licensed Internal Code Source Materials
IBM HostBoot Licensed Internal Code
The source code for this program is not published or other-
wise divested of its trade secrets, irrespective of what has
been deposited with the U.S. Copyright Office.
Origin: 30
IBM_PROLOG_END_TAG -->
<!--
XML file specifying HWPF attributes.
These are platInit attributes associated with multiple target types
Each execution platform must initialize.
-->
<attributes>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_FUNCTIONAL</id>
<targetType>
TARGET_TYPE_DIMM, TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP,
TARGET_TYPE_EX_CHIPLET, TARGET_TYPE_MBA_CHIPLET,
TARGET_TYPE_MCS_CHIPLET, TARGET_TYPE_XBUS_ENDPOINT,
TARGET_TYPE_ABUS_ENDPOINT
</targetType>
<description>
1 if the target is functional, else 0
Set by the platform.
</description>
<valueType>uint8</valueType>
<enum>NON_FUNCTIONAL = 0, FUNCTIONAL = 1</enum>
<platInit/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_POS</id>
<targetType>
TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP, TARGET_TYPE_DIMM
</targetType>
<description>
Position of chip/dimm within drawer
This data is from the MRW
TARGET_TYPE_PROC_CHIP:
0, 1, 2, 3...
TARGET_TYPE_MEMBUF_CHIP:
(attached PROC_CHIP->ATTR_POS * 8) +
(attached MCS_CHIPLET->ATTR_CHIP_UNIT_POS)
TARGET_TYPE_DIMM:
(attached PROC_CHIP->ATTR_POS * 64) +
(attached MCS_CHIPLET->ATTR_CHIP_UNIT_POS * 8) +
DIMM-NUMBER
where DIMM-NUMBER:
0: MBA0, port0, dimm0
1: MBA0, port0, dimm1
2: MBA0, port1, dimm0
3: MBA0, port1, dimm1
4: MBA1, port0, dimm0
5: MBA1, port0, dimm1
6: MBA1, port1, dimm0
7: MBA1, port1, dimm1
</description>
<valueType>uint32</valueType>
<platInit/>
</attribute>
<attribute>
<id>ATTR_EI_BUS_TX_LANE_INVERT</id>
<targetType>
TARGET_TYPE_MCS_CHIPLET,TARGET_TYPE_MEMBUF_CHIP,TARGET_TYPE_ABUS_ENDPOINT
</targetType>
<description>
Source: MRW: Downstream N/P Lane Swap Mask and Upstream N/P Lane Swap Mask
Usage: TX_LANE_INVERT initfile setting for DMI and A buses
This attribute represents the polarity of a differential wire pair
on the DMI and A buses. Normally differential pair wires are connected
between the two positive phases of the pair and the two negative phases
between two chips. In the DMI and Abus designs it's allowable for the
board designer to wire the positive phase of a lane from one chip to
the negative phase of the other chip on that same lane and vice versa
in order to simplify wiring on the board and reduce the number of
board layers. This attribute is set up as a 32 bit uint value
interpreted as a 32 bit binary vector where the left-most bit position
(msb/bit0) corresponds to the polarity of lane 0 and the right-most bit
position (lsb/bit31) corresponds to lane 31. A binary 1 in any
position in the attribute means that the board designer has done a
polarity swap within the differential pair and the initfile must set
the tx_lane_invert bit in the driving chip for that wire pair (called a lane).
The Downstream N/P Lane Swap Mask from the MRW represents the polarity
of the bus wiring as it goes from the master chip to the slave chip
(master chip is defined as the chip with a lower value of
(node*100 + chip position) and Upstream N/P Lane Swap Mask represents
the polarity of the bus wiring as it goes from the slave chip back to
the master chip.
Examples:
- Port A2 on Chip Target n0p0 connects to Port A2 on chip target
n0p2. This connection has a Downstream N/P Lane Swap Mask and
an Upstream N/P Lane Swap Mask. Setting the Downstream N/P
Lane Swap Mask to a value of 0x80000000 means lane 0 is polarity
swapped and the initfile should set lane 0's tx_lane_invert bit
on the n0p0 targeted chip (the so-called master chip).
If the Upstream N/P Lane Swap Mask is 0x20000000 this means lane
2 is polarity swapped and the initfile should set lane 2's
tx_lane_invert bit on the n0p2 targeted chip (the so-called slave chip).
It is up to the platform code to set up each ATTR_EI_BUS_TX_LANE_INVERT
value for the correct target endpoints, ie. 0x80000000 for n0p0 and
0x20000000 for n0p2.
</description>
<valueType>uint32</valueType>
<platInit/>
</attribute>
</attributes>
|
