1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
|
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/usr/diag/prdf/plat/mem/prdfMemDsd.H $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
/** @file prdfMemDsd.H */
#ifndef __prdfMemDsd_H
#define __prdfMemDsd_H
// Platform includes
#include <prdfMemEccAnalysis.H>
#include <prdfMemMark.H>
#include <prdfMemScrubUtils.H>
#include <prdfMemTdQueue.H>
#include <prdfP9McaExtraSig.H>
#include <prdfPlatServices.H>
namespace PRDF
{
/** @brief DRAM Spare Deploy procedure. */
template<TARGETING::TYPE T>
class DsdEvent : public TdEntry
{
public: // functions
/**
* @brief Constructor
* @param i_chip MCA or MBA.
* @param i_rank Rank reporting chip mark.
*/
DsdEvent<T>( ExtensibleChip * i_chip, const MemRank & i_rank,
const MemMark & i_mark, bool i_eccSpare = false ) :
TdEntry(DSD_EVENT, i_chip, i_rank), iv_mark(i_mark),
iv_eccSpare(i_eccSpare)
{
PRDF_ASSERT( nullptr != i_chip );
PRDF_ASSERT( T == i_chip->getType() );
PRDF_ASSERT( i_mark.isValid() );
}
public: // overloaded functions from parent class
uint32_t nextStep( STEP_CODE_DATA_STRUCT & io_sc, bool & o_done )
{
#define PRDF_FUNC "[DsdEvent::nextStep] "
// TODO: RTC 189221 should assert if DRAM Sparing is NOT supported.
uint32_t o_rc = SUCCESS;
o_done = false;
do
{
// First, do analysis.
o_rc = analyzePhase( io_sc, o_done );
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "analyzePhase() failed on 0x%08x,0x%2x",
iv_chip->getHuid(), getKey() );
break;
}
if ( o_done ) break; // Nothing more to do.
// Then, start the next phase of the procedure.
o_rc = startNextPhase( io_sc );
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "startNextPhase() failed on 0x%08x,0x%2x",
iv_chip->getHuid(), getKey() );
break;
}
} while (0);
// Add the chip mark to the callout list if no callouts in the list.
if ( 0 == io_sc.service_data->getMruListSize() )
{
MemoryMru mm { iv_chip->getTrgt(), iv_rank, iv_mark.getSymbol() };
io_sc.service_data->SetCallout( mm );
}
return o_rc;
#undef PRDF_FUNC
}
uint32_t getKey() const
{ return MemRank(iv_rank.getMaster()).getKey(); } // Master rank only
private: // functions
/**
* @brief Does isolation for ECC attentions during each phase.
* @param i_eccAttns Mask of all currently active maintenance attentions.
* See enum MaintEccAttns for values.
* @param io_sc The step code data struct.
* @param o_done True if the procedure is complete or has aborted.
* @return Non-SUCCESS if an internal function fails, SUCCESS otherwise.
*/
uint32_t checkEcc( const uint32_t & i_eccAttns,
STEP_CODE_DATA_STRUCT & io_sc, bool & o_done );
/**
* @brief Called in the last phase of the procedure to determine if the
* spare was successfully applied.
* @param i_eccAttns Mask of all currently active maintenance attentions.
* See enum MaintEccAttns for values.
* @param io_sc The step code data struct.
* @param o_done True if the procedure is complete or has aborted.
* @return Non-SUCCESS if an internal function fails, SUCCESS otherwise.
*/
uint32_t verifySpare( const uint32_t & i_eccAttns,
STEP_CODE_DATA_STRUCT & io_sc, bool & o_done );
/**
* @brief Do analysis based on the current phase.
* @param io_sc The step code data struct.
* @param o_done True if the procedure is complete or has aborted.
* @return Non-SUCCESS if an internal function fails, SUCCESS otherwise.
*/
uint32_t analyzePhase( STEP_CODE_DATA_STRUCT & io_sc, bool & o_done )
{
#define PRDF_FUNC "[DsdEvent::analyzePhase] "
uint32_t o_rc = SUCCESS;
do
{
if ( TD_PHASE_0 == iv_phase )
{
// Before starting the first command, set iv_mark in the
// hardware steer mux.
/* TODO: RTC 189221
o_rc = mssSetSteerMux<T>( iv_chip, iv_rank, iv_mark,
iv_eccSpare );
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "mssSetSteerMux(0x%08x,0x%2x) failed",
iv_chip->getHuid(), getKey() );
break;
}
*/
break; // Nothing to analyze yet.
}
// Look for any ECC errors that occurred during the command.
uint32_t eccAttns;
o_rc = checkEccFirs<T>( iv_chip, eccAttns );
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "checkEccFirs(0x%08x) failed",
iv_chip->getHuid() );
break;
}
// Analyze the ECC errors, if needed.
o_rc = checkEcc( eccAttns, io_sc, o_done );
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "checkEcc() failed on 0x%08x",
iv_chip->getHuid() );
break;
}
if ( o_done ) break; // abort the procedure.
// Determine if the spare was applied successfully.
o_rc = verifySpare( eccAttns, io_sc, o_done );
if ( SUCCESS != o_rc )
{
PRDF_ERR( PRDF_FUNC "verifySpare() failed on 0x%08x",
iv_chip->getHuid() );
break;
}
} while (0);
#ifdef __HOSTBOOT_RUNTIME
if ( (SUCCESS == o_rc) && o_done )
{
// Clear the ECC FFDC for this master rank.
MemDbUtils::resetEccFfdc<T>( iv_chip, iv_rank, MASTER_RANK );
}
#endif
return o_rc;
#undef PRDF_FUNC
}
/**
* @brief Starts the appropriate maintenance command for each phase of the
* procedure.
* @pre iv_phase must be set appropriately before calling this function.
* @return Non-SUCCESS if an internal function fails, SUCCESS otherwise.
*/
uint32_t startCmd();
/**
* @brief Starts the next phase of the procedure.
* @param io_sc The step code data struct.
* @post iv_phase will be updated appropriately per design.
* @return Non-SUCCESS if an internal function fails, SUCCESS otherwise.
*/
uint32_t startNextPhase( STEP_CODE_DATA_STRUCT & io_sc );
private: // instance variables
const MemMark iv_mark; ///< The chip mark from hardware.
const bool iv_eccSpare; ///< True if the spare should be applied to the x4
///< DRAM ECC spare.
};
} // end namespace PRDF
#endif // __prdfMemDsd_H
|
