path: root/src/usr/diag/prdf/common/plat/nimbus/nimbus_mca.rule

# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/nimbus/nimbus_mca.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2016,2018
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

chip nimbus_mca
{
    name        "NIMBUS MCA target";
    targettype  TYPE_MCA;
    sigoff      0x9000;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

# Import signatures
.include "prdfMemExtraSig.H";
.include "prdfP9McaExtraSig.H";

 #############################################################################
 #                                                                           #
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 #  #     #  #       #    #     #    #          #    #       #    #  #       #
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 #  #     #  ######   ####     ###    ####      #    ######  #    #   ####   #
 #                                                                           #
 #############################################################################

    ############################################################################
    # P9 MCA target MCACALFIR
    ############################################################################

    register MCACALFIR
    {
        name        "P9 MCA target MCACALFIR";
        scomaddr    0x07010900;
        reset       (&, 0x07010901);
        mask        (|, 0x07010905);
        capture     group default;
        capture     group McbistCapture;
    };

    register MCACALFIR_MASK
    {
        name        "P9 MCA target MCACALFIR MASK";
        scomaddr    0x07010903;
        capture     group default;
        capture     group McbistCapture;
    };

    register MCACALFIR_ACT0
    {
        name        "P9 MCA target MCACALFIR ACT0";
        scomaddr    0x07010906;
        capture     group default;
        capture     group McbistCapture;
        capture     req nonzero("MCACALFIR");
    };

    register MCACALFIR_ACT1
    {
        name        "P9 MCA target MCACALFIR ACT1";
        scomaddr    0x07010907;
        capture     group default;
        capture     group McbistCapture;
        capture     req nonzero("MCACALFIR");
    };

    ############################################################################
    # P9 MCA target MCAECCFIR
    ############################################################################

    register MCAECCFIR
    {
        name        "P9 MCA target MCAECCFIR";
        scomaddr    0x07010a00;
        reset       (&, 0x07010a01);
        mask        (|, 0x07010a05);
        capture     group default;
        capture     group McbistCapture;
        capture     group MaintCmdRegs_mca;
    };

    register MCAECCFIR_MASK
    {
        name        "P9 MCA target MCAECCFIR MASK";
        scomaddr    0x07010a03;
        capture     group default;
        capture     group McbistCapture;
    };

    register MCAECCFIR_ACT0
    {
        name        "P9 MCA target MCAECCFIR ACT0";
        scomaddr    0x07010a06;
        capture     group default;
        capture     group McbistCapture;
        capture     req nonzero("MCAECCFIR");
    };

    register MCAECCFIR_ACT1
    {
        name        "P9 MCA target MCAECCFIR ACT1";
        scomaddr    0x07010a07;
        capture     group default;
        capture     group McbistCapture;
        capture     req nonzero("MCAECCFIR");
    };

    ############################################################################
    # P9 MCA target DDRPHYFIR
    ############################################################################

    register DDRPHYFIR
    {
        name        "P9 MCA target DDRPHYFIR";
        scomaddr    0x07011000;
        reset       (&, 0x07011001);
        mask        (|, 0x07011005);
        capture     group default;
        capture     group McbistCapture;
    };

    register DDRPHYFIR_MASK
    {
        name        "P9 MCA target DDRPHYFIR MASK";
        scomaddr    0x07011003;
        capture     group default;
        capture     group McbistCapture;
    };

    register DDRPHYFIR_ACT0
    {
        name        "P9 MCA target DDRPHYFIR ACT0";
        scomaddr    0x07011006;
        capture     group default;
        capture     group McbistCapture;
        capture     req nonzero("DDRPHYFIR");
    };

    register DDRPHYFIR_ACT1
    {
        name        "P9 MCA target DDRPHYFIR ACT1";
        scomaddr    0x07011007;
        capture     group default;
        capture     group McbistCapture;
        capture     req nonzero("DDRPHYFIR");
    };

# Include registers not defined by the xml
.include "nimbus_mca_regs.rule";

};

 ##############################################################################
 #                                                                            #
 # ####                                 #                                     #
 # #   # #   # #    #####  ###      #  # #    ##  ##### ###  ###  #   #  ###  #
 # #   # #   # #    #     #        #  #   #  #  #   #    #  #   # ##  # #     #
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 # #   #  ###  #### #####  ###  #    #     #  ##    #   ###  ###  #   #  ###  #
 #                                                                            #
 ##############################################################################

################################################################################
# Summary for MCA
################################################################################

rule rMCA
{
  CHECK_STOP:
    summary( 0, rMCACALFIR ) |
    summary( 1, rMCAECCFIR ) |
    summary( 2, rDDRPHYFIR );

  RECOVERABLE:
    summary( 0, rMCACALFIR ) |
    summary( 1, rMCAECCFIR ) |
    summary( 2, rDDRPHYFIR );

  UNIT_CS:
    summary( 0, rMCACALFIR ) |
    summary( 1, rMCAECCFIR );

  HOST_ATTN:
    summary( 0, rMCACALFIR ) |
    summary( 1, rMCAECCFIR );

};

group gMCA attntype CHECK_STOP, RECOVERABLE, UNIT_CS, HOST_ATTN
    filter singlebit
{
    (rMCA, bit(0)) ? analyze(gMCACALFIR);
    (rMCA, bit(1)) ? analyze(gMCAECCFIR);
    (rMCA, bit(2)) ? analyze(gDDRPHYFIR);
};

################################################################################
# P9 MCA target MCACALFIR
################################################################################

rule rMCACALFIR
{
  CHECK_STOP:
    MCACALFIR & ~MCACALFIR_MASK & ~MCACALFIR_ACT0 & ~MCACALFIR_ACT1;
  RECOVERABLE:
    MCACALFIR & ~MCACALFIR_MASK & ~MCACALFIR_ACT0 &  MCACALFIR_ACT1;
  HOST_ATTN:
    MCACALFIR & ~MCACALFIR_MASK &  MCACALFIR_ACT0 & ~MCACALFIR_ACT1;
  UNIT_CS:
    MCACALFIR & ~MCACALFIR_MASK &  MCACALFIR_ACT0 &  MCACALFIR_ACT1;
};

group gMCACALFIR
    filter priority(13),
           cs_root_cause(4,13,14)
{
    /** MCACALFIR[0]
     *  A MBA recoverable error has occurred.
     */
    (rMCACALFIR, bit(0)) ? self_th_1;

    /** MCACALFIR[1]
     *  MBA Nonrecoverable Error
     */
    (rMCACALFIR, bit(1)) ? self_th_1;

    /** MCACALFIR[2]
     *  Excessive refreshes to a single rank.
     */
    (rMCACALFIR, bit(2)) ? self_th_32perDay;

    /** MCACALFIR[3]
     *  Err detected in the MBA debug WAT logic
     */
    (rMCACALFIR, bit(3)) ? defaultMaskedError;

    /** MCACALFIR[4]
     *  A RCD parity error has been detected
     */
    (rMCACALFIR, bit(4)) ? rcd_parity_error;

    /** MCACALFIR[5]
     *  Calibration complete indication xout
     */
    (rMCACALFIR, bit(5)) ? self_th_32perDay;

    /** MCACALFIR[6]
     *  Emergency Throttle
     */
    (rMCACALFIR, bit(6)) ? defaultMaskedError;

    /** MCACALFIR[7]
     *  DDR cal reset timeout
     */
    (rMCACALFIR, bit(7)) ? self_th_1;

    /** MCACALFIR[8]
     *  event_n active on DDR interface
     */
    (rMCACALFIR, bit(8)) ? defaultMaskedError;

    /** MCACALFIR[9]
     *  WRQ or RRQ is in a hung state.
     */
    (rMCACALFIR, bit(9)) ? self_th_1;

    /** MCACALFIR[10]
     *  State machine one hot error.
     */
    (rMCACALFIR, bit(10)) ? self_th_1;

    /** MCACALFIR[11]
     *  Sequencer error crossing async interface
     */
    (rMCACALFIR, bit(11)) ? self_th_1;

    /** MCACALFIR[12]
     *  Address PE  internal to seq.
     */
    (rMCACALFIR, bit(12)) ? self_th_1;

    /** MCACALFIR[13]
     *  Persistent RCD error, port failed
     */
    (rMCACALFIR, bit(13)) ? mem_port_failure_UERE;

    /** MCACALFIR[14]
     *  RCD during periodic cal
     */
    (rMCACALFIR, bit(14)) ? rcd_parity_error;

    /** MCACALFIR[15]
     *  Parity error on debug bus SCOM registers
     */
    (rMCACALFIR, bit(15)) ? defaultMaskedError;

    /** MCACALFIR[16]
     *  scom error
     */
    (rMCACALFIR, bit(16)) ? defaultMaskedError;

    /** MCACALFIR[17]
     *  scom error copy
     */
    (rMCACALFIR, bit(17)) ? defaultMaskedError;

};

################################################################################
# P9 MCA target MCAECCFIR
################################################################################

rule rMCAECCFIR
{
  CHECK_STOP:
    MCAECCFIR & ~MCAECCFIR_MASK & ~MCAECCFIR_ACT0 & ~MCAECCFIR_ACT1;
  RECOVERABLE:
    MCAECCFIR & ~MCAECCFIR_MASK & ~MCAECCFIR_ACT0 &  MCAECCFIR_ACT1;
  HOST_ATTN:
    MCAECCFIR & ~MCAECCFIR_MASK &  MCAECCFIR_ACT0 & ~MCAECCFIR_ACT1;
  UNIT_CS:
    MCAECCFIR & ~MCAECCFIR_MASK &  MCAECCFIR_ACT0 &  MCAECCFIR_ACT1;
};

group gMCAECCFIR
    filter priority(14,17,37),
           cs_root_cause(14,17,37)
{
    /** MCAECCFIR[0]
     *  Mainline read MPE on rank 0
     */
    (rMCAECCFIR, bit(0)) ? verify_chip_mark_0;

    /** MCAECCFIR[1]
     *  Mainline read MPE on rank 1
     */
    (rMCAECCFIR, bit(1)) ? verify_chip_mark_1;

    /** MCAECCFIR[2]
     *  Mainline read MPE on rank 2
     */
    (rMCAECCFIR, bit(2)) ? verify_chip_mark_2;

    /** MCAECCFIR[3]
     *  Mainline read MPE on rank 3
     */
    (rMCAECCFIR, bit(3)) ? verify_chip_mark_3;

    /** MCAECCFIR[4]
     *  Mainline read MPE on rank 4
     */
    (rMCAECCFIR, bit(4)) ? verify_chip_mark_4;

    /** MCAECCFIR[5]
     *  Mainline read MPE on rank 5
     */
    (rMCAECCFIR, bit(5)) ? verify_chip_mark_5;

    /** MCAECCFIR[6]
     *  Mainline read MPE on rank 6
     */
    (rMCAECCFIR, bit(6)) ? verify_chip_mark_6;

    /** MCAECCFIR[7]
     *  Mainline read MPE on rank 7
     */
    (rMCAECCFIR, bit(7)) ? verify_chip_mark_7;

    /** MCAECCFIR[8]
     *  Mainline read NCE
     */
    (rMCAECCFIR, bit(8)) ? mainline_nce_tce_handling;

    /** MCAECCFIR[9]
     *  Mainline read TCE
     */
    (rMCAECCFIR, bit(9)) ? mainline_nce_tce_handling;

    /** MCAECCFIR[8:9]
     *  Mainline read NCE and TCE
     */
    (rMCAECCFIR, bit(8,9)) ? mainline_nce_tce_handling;

    /** MCAECCFIR[10]
     *  Mainline read SCE
     */
    (rMCAECCFIR, bit(10)) ? defaultMaskedError;

    /** MCAECCFIR[11]
     *  Mainline read MCE
     */
    (rMCAECCFIR, bit(11)) ? defaultMaskedError;

    /** MCAECCFIR[12]
     *  Mainline read SUE
     */
    (rMCAECCFIR, bit(12)) ? defaultMaskedError;

    /** MCAECCFIR[13]
     *  Mainline read AUE
     */
    (rMCAECCFIR, bit(13)) ? mainline_aue_iaue_handling;

    /** MCAECCFIR[14]
     *  Mainline read UE
     */
    (rMCAECCFIR, bit(14)) ? mainline_ue_handling_UERE;

    /** MCAECCFIR[15]
     *  Mainline read RCD
     */
    (rMCAECCFIR, bit(15)) ? self_th_1; # NIMBUS_20

    /** MCAECCFIR[16]
     *  Mainline read IAUE
     */
    (rMCAECCFIR, bit(16)) ? mainline_aue_iaue_handling;

    /** MCAECCFIR[17]
     *  Mainline read IUE
     */
    (rMCAECCFIR, bit(17)) ? mainline_iue_handling;

    /** MCAECCFIR[18]
     *  Mainline read IRCD
     */
    (rMCAECCFIR, bit(18)) ? defaultMaskedError;

    /** MCAECCFIR[19]
     *  Mainline read IMPE
     */
    (rMCAECCFIR, bit(19)) ? memory_impe_handling;

    /** MCAECCFIR[20:27]
     *  Maintenance MPE
     */
    (rMCAECCFIR, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError;

    /** MCAECCFIR[28]
     *  Maintenance NCE
     */
    (rMCAECCFIR, bit(28)) ? defaultMaskedError;

    /** MCAECCFIR[29]
     *  Maintenance TCE
     */
    (rMCAECCFIR, bit(29)) ? defaultMaskedError;

    /** MCAECCFIR[30]
     *  Maintenance SCE
     */
    (rMCAECCFIR, bit(30)) ? defaultMaskedError;

    /** MCAECCFIR[31]
     *  Maintenance MCE
     */
    (rMCAECCFIR, bit(31)) ? defaultMaskedError;

    /** MCAECCFIR[32]
     *  Maintenance SUE
     */
    (rMCAECCFIR, bit(32)) ? defaultMaskedError;

    /** MCAECCFIR[33]
     *  Maintenance AUE
     */
    (rMCAECCFIR, bit(33)) ? maintenance_aue_handling;

    /** MCAECCFIR[34]
     *  Maintenance UE
     */
    (rMCAECCFIR, bit(34)) ? defaultMaskedError;

    /** MCAECCFIR[35]
     *  Maintenance RCD
     */
    (rMCAECCFIR, bit(35)) ? defaultMaskedError;

    /** MCAECCFIR[36]
     *  Maintenance IAUE
     */
    (rMCAECCFIR, bit(36)) ? maintenance_iaue_handling;

    /** MCAECCFIR[37]
     *  Maintenance IUE
     */
    (rMCAECCFIR, bit(37)) ? maintenance_iue_handling;

    /** MCAECCFIR[38]
     *  Maintenance IRCD
     */
    (rMCAECCFIR, bit(38)) ? defaultMaskedError;

    /** MCAECCFIR[39]
     *  Maintenance IMPE
     */
    (rMCAECCFIR, bit(39)) ? memory_impe_handling;

    /** MCAECCFIR[40]
     *  spare
     */
    (rMCAECCFIR, bit(40)) ? defaultMaskedError;

    /** MCAECCFIR[41]
     *  SCOM_PARITY_CLASS_STATUS
     */
    (rMCAECCFIR, bit(41)) ? threshold_and_mask_self;

    /** MCAECCFIR[42]
     *  SCOM_PARITY_CLASS_RECOVERABLE
     */
    (rMCAECCFIR, bit(42)) ? self_th_1;

    /** MCAECCFIR[43]
     *  SCOM_PARITY_CLASS_UNRECOVERABLE
     */
    (rMCAECCFIR, bit(43)) ? self_th_1;

    /** MCAECCFIR[44]
     *  ECC_CORRECTOR_INTERNAL_PARITY_ERROR
     */
    (rMCAECCFIR, bit(44)) ? self_th_1;

    /** MCAECCFIR[45]
     *  WRITE_RMW_CE
     */
    (rMCAECCFIR, bit(45)) ? self_th_32perDay;

    /** MCAECCFIR[46]
     *  WRITE_RMW_UE
     */
    (rMCAECCFIR, bit(46)) ? self_th_1;

    /** MCAECCFIR[47]
     *  WRITE_RMW_SUE
     */
    (rMCAECCFIR, bit(47)) ? defaultMaskedError;

    /** MCAECCFIR[48]
     *  WDF_OVERRUN_ERROR_0
     */
    (rMCAECCFIR, bit(48)) ? self_th_1;

    /** MCAECCFIR[49]
     *  WDF_OVERRUN_ERROR_1
     */
    (rMCAECCFIR, bit(49)) ? self_th_1;

    /** MCAECCFIR[50]
     *  WDF_SCOM_SEQUENCE_ERROR
     */
    (rMCAECCFIR, bit(50)) ? self_th_1;

    /** MCAECCFIR[51]
     *  WDF_STATE_MACHINE_ERROR
     */
    (rMCAECCFIR, bit(51)) ? self_th_1;

    /** MCAECCFIR[52]
     *  WDF_MISC_REGISTER_PARITY_ERROR
     */
    (rMCAECCFIR, bit(52)) ? self_th_1;

    /** MCAECCFIR[53]
     *  WRT_SCOM_SEQUENCE_ERROR
     */
    (rMCAECCFIR, bit(53)) ? self_th_1;

    /** MCAECCFIR[54]
     *  WRT_MISC_REGISTER_PARITY_ERROR
     */
    (rMCAECCFIR, bit(54)) ? self_th_1;

    /** MCAECCFIR[55]
     *  ECC_GENERATOR_INTERNAL_PARITY_ERROR
     */
    (rMCAECCFIR, bit(55)) ? self_th_1;

    /** MCAECCFIR[56]
     *  READ_BUFFER_OVERFLOW_ERROR
     */
    (rMCAECCFIR, bit(56)) ? self_th_1;

    /** MCAECCFIR[57]
     *  WDF_ASYNC_INTERFACE_ERROR
     */
    (rMCAECCFIR, bit(57)) ? self_th_1;

    /** MCAECCFIR[58]
     *  READ_ASYNC_INTERFACE_PARITY_ERROR
     */
    (rMCAECCFIR, bit(58)) ? self_th_1;

    /** MCAECCFIR[59]
     *  READ_ASYNC_INTERFACE_SEQUENCE_ERROR
     */
    (rMCAECCFIR, bit(59)) ? self_th_1;

    /** MCAECCFIR[60:61]
     *  spare
     */
    (rMCAECCFIR, bit(60|61)) ? defaultMaskedError;

    /** MCAECCFIR[62]
     *  INTERNAL_SCOM_ERROR
     */
    (rMCAECCFIR, bit(62)) ? defaultMaskedError;

    /** MCAECCFIR[63]
     *  INTERNAL_SCOM_ERROR_COPY
     */
    (rMCAECCFIR, bit(63)) ? defaultMaskedError;

};

################################################################################
# P9 MCA target DDRPHYFIR
################################################################################

rule rDDRPHYFIR
{
  CHECK_STOP:
    DDRPHYFIR & ~DDRPHYFIR_MASK & ~DDRPHYFIR_ACT0 & ~DDRPHYFIR_ACT1;
  RECOVERABLE:
    DDRPHYFIR & ~DDRPHYFIR_MASK & ~DDRPHYFIR_ACT0 &  DDRPHYFIR_ACT1;
};

group gDDRPHYFIR
    filter singlebit,
           cs_root_cause
{
    /** DDRPHYFIR[54]
     *  Non-recoverable FSM error
     */
    (rDDRPHYFIR, bit(54)) ? mca_ue_algorithm_th_5perDay;

    /** DDRPHYFIR[55]
     *  Full bus impact Register Parity Error
     */
    (rDDRPHYFIR, bit(55)) ? mca_ue_algorithm_th_1;

    /** DDRPHYFIR[56]
     *  DDRPHY Parity errors
     */
    (rDDRPHYFIR, bit(56)) ? defaultMaskedError;

    /** DDRPHYFIR[57]
     *  FSM errors
     */
    (rDDRPHYFIR, bit(57)) ? mca_ue_algorithm_th_5perDay;

    /** DDRPHYFIR[58]
     *  Register parity error impacting 16 bits
     */
    (rDDRPHYFIR, bit(58)) ? mca_ue_algorithm_th_1;

    /** DDRPHYFIR[59]
     *  Register parity error impacting 8 bits
     */
    (rDDRPHYFIR, bit(59)) ? mca_ue_algorithm_th_1;

    /** DDRPHYFIR[60]
     *  Register PE 4 bit impact
     */
    (rDDRPHYFIR, bit(60)) ? self_th_1;

    /** DDRPHYFIR[61]
     *  Register PE 1 bit impact
     */
    (rDDRPHYFIR, bit(61)) ? self_th_1;

};

 ##############################################################################
 #                                                                            #
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 ##############################################################################

# Include the actions defined for this target
.include "p9_common_actions.rule";
.include "nimbus_mca_actions.rule";