path: root/src/usr/diag/prdf/common/plat/cen/cen_mba.rule

# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/cen/cen_mba.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2012,2018
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

chip cen_mba
{
    name        "Centaur MBA chiplet";
    targettype  TYPE_MBA;
    sigoff      0x9000;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

.include "prdfMemExtraSig.H";
.include "prdfCenMbaExtraSig.H";

 #############################################################################
 #                                                                           #
 #  ######                                                                   #
 #  #     #  ######   ####     ###    ####    #####  ######  #####    ####   #
 #  #     #  #       #    #     #    #          #    #       #    #  #       #
 #  ######   #####   #          #     ####      #    #####   #    #   ####   #
 #  #   #    #       #  ###     #         #     #    #       #####        #  #
 #  #    #   #       #    #     #    #    #     #    #       #   #   #    #  #
 #  #     #  ######   ####     ###    ####      #    ######  #    #   ####   #
 #                                                                           #
 #############################################################################

    ############################################################################
    # Centaur chip MBA target MBACALFIR
    ############################################################################

    register MBACALFIR
    {
        name        "Centaur chip MBA target MBACALFIR";
        scomaddr    0x03010400;
        reset       (&, 0x03010401);
        mask        (|, 0x03010405);
        capture     group default;
    };

    register MBACALFIR_MASK
    {
        name        "Centaur chip MBA target MBACALFIR MASK";
        scomaddr    0x03010403;
        capture     group default;
    };

    register MBACALFIR_ACT0
    {
        name        "Centaur chip MBA target MBACALFIR ACT0";
        scomaddr    0x03010406;
        capture     group default;
        capture     req nonzero("MBACALFIR");
    };

    register MBACALFIR_ACT1
    {
        name        "Centaur chip MBA target MBACALFIR ACT1";
        scomaddr    0x03010407;
        capture     group default;
        capture     req nonzero("MBACALFIR");
    };

    ############################################################################
    # Centaur chip MBA target MBASECUREFIR
    ############################################################################

    # This register is hardwired to channel failure (checkstop) and we cannot
    # mask or change the state of the action registers.
    register MBASECUREFIR
    {
        name        "Centaur chip MBA target MBASECUREFIR";
        scomaddr    0x0301041b;
        reset       (&, 0x0301041c);
        capture     group default;
    };

    ############################################################################
    # Centaur chip MBA target MBAFIR
    ############################################################################

    register MBAFIR
    {
        name        "Centaur chip MBA target MBAFIR";
        scomaddr    0x03010600;
        reset       (&, 0x03010601);
        mask        (|, 0x03010605);
        capture     group default;
    };

    register MBAFIR_MASK
    {
        name        "Centaur chip MBA target MBAFIR MASK";
        scomaddr    0x03010603;
        capture     group default;
    };

    register MBAFIR_ACT0
    {
        name        "Centaur chip MBA target MBAFIR ACT0";
        scomaddr    0x03010606;
        capture     group default;
        capture     req nonzero("MBAFIR");
    };

    register MBAFIR_ACT1
    {
        name        "Centaur chip MBA target MBAFIR ACT1";
        scomaddr    0x03010607;
        capture     group default;
        capture     req nonzero("MBAFIR");
    };

    ############################################################################
    # Centaur chip MBA target MBASPA
    ############################################################################

    register MBASPA
    {
        name        "Centaur chip MBA target MBASPA";
        scomaddr    0x03010611;
        reset       (&, 0x03010612);
        mask        (|, 0x03010614);
        capture     group default;
    };

    register MBASPA_MASK
    {
        name        "Centaur chip MBA target MBASPA MASK";
        scomaddr    0x03010614;
        capture     group default;
    };

    ############################################################################
    # Centaur chip MBA target MBADDRPHYFIR
    ############################################################################

    register MBADDRPHYFIR
    {
        name        "Centaur chip MBA target MBADDRPHYFIR";
        scomaddr    0x800200900301143F;
        reset       (&, 0x800200910301143F);
        mask        (|, 0x800200950301143F);
        capture     group default;
    };

    register MBADDRPHYFIR_MASK
    {
        name        "Centaur chip MBA target MBADDRPHYFIR MASK";
        scomaddr    0x800200930301143F;
        capture     group default;
    };

    register MBADDRPHYFIR_ACT0
    {
        name        "Centaur chip MBA target MBADDRPHYFIR ACT0";
        scomaddr    0x800200960301143F;
        capture     group default;
        capture     req nonzero("MBADDRPHYFIR");
    };

    register MBADDRPHYFIR_ACT1
    {
        name        "Centaur chip MBA target MBADDRPHYFIR ACT1";
        scomaddr    0x800200970301143F;
        capture     group default;
        capture     req nonzero("MBADDRPHYFIR");
    };

# Include registers not defined by the xml
.include "cen_mba_regs.rule";

};

 ##############################################################################
 #                                                                            #
 # ####                                 #                                     #
 # #   # #   # #    #####  ###      #  # #    ##  ##### ###  ###  #   #  ###  #
 # #   # #   # #    #     #        #  #   #  #  #   #    #  #   # ##  # #     #
 # ####  #   # #    ####   ###    #  ####### #      #    #  #   # # # #  ###  #
 # #  #  #   # #    #         #  #   #     # #  #   #    #  #   # #  ##     # #
 # #   #  ###  #### #####  ###  #    #     #  ##    #   ###  ###  #   #  ###  #
 #                                                                            #
 ##############################################################################

################################################################################
# Summary for MBA
################################################################################

rule rMBA
{
  UNIT_CS:
    summary( 0, rMBACALFIR ) |
    summary( 1, rMBASECUREFIR ) |
    summary( 2, rMBAFIR ) |
    summary( 3, rMBADDRPHYFIR );

  RECOVERABLE:
    summary( 0, rMBACALFIR ) |
    summary( 1, rMBASECUREFIR ) |
    summary( 2, rMBAFIR ) |
    summary( 3, rMBADDRPHYFIR );

  HOST_ATTN:
    summary( 4, rMBASPA );
};

group gMBA attntype UNIT_CS, RECOVERABLE, HOST_ATTN filter singlebit
{
    (rMBA, bit(0)) ? analyze(gMBACALFIR);
    (rMBA, bit(1)) ? analyze(gMBASECUREFIR);
    (rMBA, bit(2)) ? analyze(gMBAFIR);
    (rMBA, bit(3)) ? analyze(gMBADDRPHYFIR);
    (rMBA, bit(4)) ? analyze(gMBASPA);
};

################################################################################
# Centaur chip MBA target MBACALFIR
################################################################################

rule rMBACALFIR
{
  UNIT_CS:
    MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 & ~MBACALFIR_ACT1;
  RECOVERABLE:
    MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 &  MBACALFIR_ACT1;
};

# RCD parity errors (bits 4 and 7) given priority over potential side effects
# bits 2 and 17.
group gMBACALFIR filter priority( 4, 7 ),
                        cs_root_cause( 0, 1, 2, 4, 5, 6, 7, 8, 9, 11, 13, 15, 17, 18 )
{
    /** MBACALFIR[0]
     *  MBA_RECOVERABLE_ERROR
     */
    (rMBACALFIR, bit(0)) ? self_th_1;

    /** MBACALFIR[1]
     *  MBA_NONRECOVERABLE_ERROR
     */
    (rMBACALFIR, bit(1)) ? self_th_1_UERE;

    /** MBACALFIR[2]
     *  REFRESH_OVERRUN
     */
    (rMBACALFIR, bit(2)) ? self_th_32perDay;

    /** MBACALFIR[3]
     *  WAT_ERROR
     */
    (rMBACALFIR, bit(3)) ? defaultMaskedError;

    /** MBACALFIR[4]
     *  RCD parity error on port 0
     */
    (rMBACALFIR, bit(4)) ? rcd_parity_error_port0_UERE;

    /** MBACALFIR[5]
     *  DDR0_CAL_TIMEOUT_ERR
     */
    (rMBACALFIR, bit(5)) ? self_th_1;

    /** MBACALFIR[6]
     *  DDR1_CAL_TIMEOUT_ERR
     */
    (rMBACALFIR, bit(6)) ? self_th_1;

    /** MBACALFIR[7]
     *  RCD parity error on port 1
     */
    (rMBACALFIR, bit(7)) ? rcd_parity_error_port1_UERE;

    /** MBACALFIR[8]
     *  MBX_TO_MBA_PAR_ERROR
     */
    (rMBACALFIR, bit(8)) ? self_th_1;

    /** MBACALFIR[9]
     *  MBA_WRD_UE
     */
    (rMBACALFIR, bit(9)) ? self_th_1_UERE;

    /** MBACALFIR[10]
     *  MBA_WRD_CE
     */
    (rMBACALFIR, bit(10)) ? threshold_and_mask_self;

    /** MBACALFIR[11]
     *  MBA_MAINT_UE
     */
    (rMBACALFIR, bit(11)) ? self_th_1_UERE;

    /** MBACALFIR[12]
     *  MBA_MAINT_CE
     */
    (rMBACALFIR, bit(12)) ? self_th_32perDay;

    /** MBACALFIR[13]
     *  DDR_CAL_RESET_TIMEOUT
     */
    (rMBACALFIR, bit(13)) ? self_th_1_UERE;

    /** MBACALFIR[14]
     *  WRQ_DATA_CE
     */
    (rMBACALFIR, bit(14)) ? threshold_and_mask_self;

    /** MBACALFIR[15]
     *  WRQ_DATA_UE
     */
    (rMBACALFIR, bit(15)) ? self_th_1_UERE;

    /** MBACALFIR[16]
     *  WRQ_DATA_SUE
     */
    (rMBACALFIR, bit(16)) ? defaultMaskedError;

    /** MBACALFIR[17]
     *  WRQ_RRQ_HANG_ERR
     */
    (rMBACALFIR, bit(17)) ? self_th_1;

    /** MBACALFIR[18]
     *  SM_1HOT_ERR
     */
    (rMBACALFIR, bit(18)) ? self_th_1_UERE;

    /** MBACALFIR[19]
     *  WRD_SCOM_ERROR
     */
    (rMBACALFIR, bit(19)) ? threshold_and_mask_self;

    /** MBACALFIR[20]
     *  RHMR_PRIM_REACHED_MAX
     */
    (rMBACALFIR, bit(20)) ? defaultMaskedError;

    /** MBACALFIR[21]
     *  RHMR_SEC_REACHED_MAX
     */
    (rMBACALFIR, bit(21)) ? defaultMaskedError;

    /** MBACALFIR[22]
     *  RHMR_SEC_ALREADY_FULL
     */
    (rMBACALFIR, bit(22)) ? defaultMaskedError;

    /** MBACALFIR[23]
     *  Reserved
     */
    (rMBACALFIR, bit(23)) ? defaultMaskedError;

    /** MBACALFIR[24]
     *  SCOM FIR error
     */
    (rMBACALFIR, bit(24)) ? threshold_and_mask_self;

    /** MBACALFIR[25]
     *  SCOM FIR error clone
     */
    (rMBACALFIR, bit(25)) ? threshold_and_mask_self;

};

################################################################################
# Centaur chip MBA target MBASECUREFIR
################################################################################

rule rMBASECUREFIR
{
  UNIT_CS:
    MBASECUREFIR;
};

group gMBASECUREFIR filter singlebit, cs_root_cause( 0, 1, 2, 3, 4, 5 )
{
    /** MBASECUREFIR[0]
     *  Invalid MBA_CALQ0 access
     */
    (rMBASECUREFIR, bit(0)) ? level2_th_1_UERE;

    /** MBASECUREFIR[1]
     *  Invalid MBA_CALQ1 access
     */
    (rMBASECUREFIR, bit(1)) ? level2_th_1_UERE;

    /** MBASECUREFIR[2]
     *  Invalid MBA_CAL2Q access
     */
    (rMBASECUREFIR, bit(2)) ? level2_th_1_UERE;

    /** MBASECUREFIR[3]
     *  Invalid MBA_CAL3Q access
     */
    (rMBASECUREFIR, bit(3)) ? level2_th_1_UERE;

    /** MBASECUREFIR[4]
     *  Invalid DDR config reg access
     */
    (rMBASECUREFIR, bit(4)) ? level2_th_1_UERE;

    /** MBASECUREFIR[5]
     *  Invalid SIR mask or action reg access
     */
    (rMBASECUREFIR, bit(5)) ? level2_th_1_UERE;

};

################################################################################
# Centaur chip MBA target MBAFIR
################################################################################

rule rMBAFIR
{
  UNIT_CS:
    MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 & ~MBAFIR_ACT1;
  RECOVERABLE:
    MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 &  MBAFIR_ACT1;
};

group gMBAFIR filter singlebit, cs_root_cause( 3, 5, 6, 7, 8 )
{
    /** MBAFIR[0]
     *  Invalid Maintenance Command
     */
    (rMBAFIR, bit(0)) ? defaultMaskedError;

    /** MBAFIR[1]
     *  Invalid Maintenance Address
     */
    (rMBAFIR, bit(1)) ? defaultMaskedError;

    /** MBAFIR[2]
     *  Multi-address Maintenance Cmd Timeout
     */
    (rMBAFIR, bit(2)) ? self_th_1;

    /** MBAFIR[3]
     *  Internal FSM parity error
     */
    (rMBAFIR, bit(3)) ? self_th_1_UERE;

    /** MBAFIR[4]
     *  MCBIST error
     */
    (rMBAFIR, bit(4)) ? defaultMaskedError;

    /** MBAFIR[5]
     *  SCOM command register parity error
     */
    (rMBAFIR, bit(5)) ? self_th_1_UERE;

    /** MBAFIR[6]
     *  Unrecoverable channel error
     */
    (rMBAFIR, bit(6)) ? self_th_1_UERE;

    /** MBAFIR[7]
     *  UE or CE Error in WRD caw2 data latches
     */
    (rMBAFIR, bit(7)) ? self_th_1_UERE;

    /** MBAFIR[8]
     *  Illegal transition maint state machine
     */
    (rMBAFIR, bit(8)) ? self_th_1_UERE;

    /** MBAFIR[9:14]
     *  RESERVED
     */
    (rMBAFIR, bit(9|10|11|12|13|14)) ? defaultMaskedError;

    /** MBAFIR[15]
     *  SCOM Internal Error
     */
    (rMBAFIR, bit(15)) ? threshold_and_mask_self;

    /** MBAFIR[16]
     *  SCOM Internal Error Copy
     */
    (rMBAFIR, bit(16)) ? threshold_and_mask_self;

};

################################################################################
# Centaur chip MBA target MBASPA
################################################################################

rule rMBASPA
{
  HOST_ATTN:
    MBASPA & ~MBASPA_MASK;
};

group gMBASPA filter singlebit, cs_root_cause
{
    /** MBASPA[0]
     *  Maintenance command complete
     */
    (rMBASPA, bit(0)) ? maint_cmd_complete;

    /** MBASPA[1]
     *  Hard NCE ETE
     */
    (rMBASPA, bit(1)) ? defaultMaskedError;

    /** MBASPA[2]
     *  Soft NCE ETE
     */
    (rMBASPA, bit(2)) ? defaultMaskedError;

    /** MBASPA[3]
     *  Intermittent NCE ETE
     */
    (rMBASPA, bit(3)) ? defaultMaskedError;

    /** MBASPA[4]
     *  Retry CE ETE
     */
    (rMBASPA, bit(4)) ? defaultMaskedError;

    /** MBASPA[5]
     *  Emergency throttle action detected
     */
    (rMBASPA, bit(5)) ? defaultMaskedError;

    /** MBASPA[6]
     *  Firmware generated attention 0
     */
    (rMBASPA, bit(6)) ? defaultMaskedError;

    /** MBASPA[7]
     *  Firmware generated attention 1
     */
    (rMBASPA, bit(7)) ? defaultMaskedError;

    /** MBASPA[8]
     *  WAT debug attention
     */
    (rMBASPA, bit(8)) ? defaultMaskedError;

    /** MBASPA[9]
     *  Spare
     */
    (rMBASPA, bit(9)) ? defaultMaskedError;

    /** MBASPA[10]
     *  MCBIST done
     */
    (rMBASPA, bit(10)) ? defaultMaskedError;

};

################################################################################
# Centaur chip MBA target MBADDRPHYFIR
################################################################################

rule rMBADDRPHYFIR
{
  UNIT_CS:
    MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 & ~MBADDRPHYFIR_ACT1;
  RECOVERABLE:
    MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 &  MBADDRPHYFIR_ACT1;
};

group gMBADDRPHYFIR filter singlebit, cs_root_cause( 48, 49, 51, 52, 56, 57, 59, 60 )
{
    /** MBADDRPHYFIR[48]
     *  FSM Error Checkstop
     */
    (rMBADDRPHYFIR, bit(48)) ? self_th_1_UERE;

    /** MBADDRPHYFIR[49]
     *  Parity Error Checkstop
     */
    (rMBADDRPHYFIR, bit(49)) ? self_th_1_UERE;

    /** MBADDRPHYFIR[50]
     *  Calibration Error RE
     */
    (rMBADDRPHYFIR, bit(50)) ? defaultMaskedError;

    /** MBADDRPHYFIR[51]
     *  FSM Recoverable Error
     */
    (rMBADDRPHYFIR, bit(51)) ? self_th_32perDay;

    /** MBADDRPHYFIR[52]
     *  Parity Recoverable Error
     */
    (rMBADDRPHYFIR, bit(52)) ? self_th_32perDay;

    /** MBADDRPHYFIR[53]
     *  Parity Recoverable Error
     */
    (rMBADDRPHYFIR, bit(53)) ? threshold_and_mask_self;

    /** MBADDRPHYFIR[54:55]
     *  Reserved
     */
    (rMBADDRPHYFIR, bit(54|55)) ? defaultMaskedError;

    /** MBADDRPHYFIR[56]
     *  FSM Error Checkstop
     */
    (rMBADDRPHYFIR, bit(56)) ? self_th_1_UERE;

    /** MBADDRPHYFIR[57]
     *  Parity Error Checkstop
     */
    (rMBADDRPHYFIR, bit(57)) ? self_th_1_UERE;

    /** MBADDRPHYFIR[58]
     *  Calibration Error RE
     */
    (rMBADDRPHYFIR, bit(58)) ? defaultMaskedError;

    /** MBADDRPHYFIR[59]
     *  FSM Recoverable Error
     */
    (rMBADDRPHYFIR, bit(59)) ? self_th_32perDay;

    /** MBADDRPHYFIR[60]
     *  Parity Recoverable Error
     */
    (rMBADDRPHYFIR, bit(60)) ? self_th_32perDay;

};

 ##############################################################################
 #                                                                            #
 #    #                                  ###                                  #
 #   # #    ##  ##### ###  ###  #   #   #   # #     #    ###   ###  ###  ###  #
 #  #   #  #  #   #    #  #   # ##  #   #     #    # #  #     #     #   #     #
 # ####### #      #    #  #   # # # #   #     #   #####  ###   ###  ##   ###  #
 # #     # #  #   #    #  #   # #  ##   #   # #   #   #     #     # #       # #
 # #     #  ##    #   ###  ###  #   #    ###  ### #   #  ###   ###  ###  ###  #
 #                                                                            #
 ##############################################################################

# Include the common action set.
.include "cen_common_actions.rule";
# Include the chip-specific action set.
.include "cen_mba_actions.rule";