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# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/cen/cen_centaur_regs.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2017,2018
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG
############################################################################
# Centaur chip TP_LFIR
############################################################################
register TP_LFIR_MASK_OR
{
name "Centaur chip TP_LFIR MASK atomic OR";
scomaddr 0x0104000f;
capture group never;
access write_only;
};
############################################################################
# Additional regs for CEN target MBSECCFIR
############################################################################
register MBSECCFIR_0_AND
{
name "Centaur chip MBSECCFIR_0 atomic AND";
scomaddr 0x02011441;
capture group never;
access write_only;
};
register MBSECCFIR_0_MASK_AND
{
name "MBU.MBS.ECC01.MBECCFIR_MASK_AND";
scomaddr 0x02011444;
capture group never;
access write_only;
};
register MBSECCFIR_0_MASK_OR
{
name "MBU.MBS.ECC01.MBECCFIR_MASK_OR";
scomaddr 0x02011445;
capture group never;
access write_only;
};
register MBSECCFIR_1_AND
{
name "Centaur chip MBSECCFIR_1 atomic AND";
scomaddr 0x02011481;
capture group never;
access write_only;
};
register MBSECCFIR_1_MASK_AND
{
name "MBU.MBS.ECC23.MBECCFIR_MASK_AND";
scomaddr 0x02011484;
capture group never;
access write_only;
};
register MBSECCFIR_1_MASK_OR
{
name "MBU.MBS.ECC23.MBECCFIR_MASK_OR";
scomaddr 0x02011485;
capture group never;
access write_only;
};
############################################################################
# Memory maintenance threshold control registers
############################################################################
register MBSTR_0
{
name "MBU.MBS.MCBISTS01.SCOMFIR.MBSTRQ";
scomaddr 0x02011655;
capture group default;
capture group MaintCmdRegs_mba0;
};
register MBSTR_1
{
name "MBU.MBS.MCBISTS23.SCOMFIR.MBSTRQ";
scomaddr 0x02011755;
capture group default;
capture group MaintCmdRegs_mba1;
};
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