summaryrefslogtreecommitdiffstats
path: root/src/kernel/segmentmgr.C
blob: 625ba61aa76d6c5bcbcacd5d459b4ab6611495bf (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
#include <assert.h>
#include <arch/ppc.H>
#include <util/singleton.H>

#include <kernel/segmentmgr.H>
#include <kernel/segment.H>

bool SegmentManager::handlePageFault(task_t* i_task, uint64_t i_addr)
{
    return Singleton<SegmentManager>::instance().
                _handlePageFault(i_task, i_addr);
}

void SegmentManager::addSegment(Segment* i_segment, size_t i_segId)
{
    Singleton<SegmentManager>::instance()._addSegment(i_segment, i_segId);
}

void SegmentManager::initSLB()
{
    Singleton<SegmentManager>::instance()._initSLB();
}

bool SegmentManager::_handlePageFault(task_t* i_task, uint64_t i_addr)
{
    // This constant should come from page manager.  Segment size.
    const size_t SLBE_s = 40;

    // Get segment ID from effective address.
    size_t segId = i_addr >> SLBE_s;

    // Call contained segment object to handle page fault.
    if ((segId < MAX_SEGMENTS) && (NULL != iv_segments[segId]))
    {
        return iv_segments[segId]->handlePageFault(i_task, i_addr);
    }

    return false;
}

void SegmentManager::_addSegment(Segment* i_segment, size_t i_segId)
{
    kassert(i_segId < MAX_SEGMENTS);
    iv_segments[i_segId] = i_segment;
}

void SegmentManager::_initSLB()
{
    // Flush SLB.
    asm volatile("slbia" ::: "memory");
    isync(); // Ensure slbia completes prior to slbmtes.

    register uint64_t slbRS, slbRB;

    // Default segment descriptors.
    // ESID = 0, V = 1, Index = 1.
    slbRB = 0x0000000008000001;
    // B = 01 (1TB), VSID = 0, Ks = 0, Kp = 1, NLCLP = 0
    slbRS = 0x4000000000000400;

    // Add all segments to SLB.
    for (size_t i = 0; i < MAX_SEGMENTS; i++)
    {
        // Add segment to SLB.
        if (NULL != iv_segments[i])
        {
            asm volatile("slbmte %0, %1" :: "r"(slbRS), "r"(slbRB) : "memory");
        }

        // Increment ESID, VSID, Index.
        slbRB += 0x0000010000000001;
        slbRS += 0x0000000001000000;
    }

    isync(); // Ensure slbmtes complete prior to continuing on.
}
OpenPOWER on IntegriCloud