1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
|
#ifndef __KERNEL_PPCARCH_H
#define __KERNEL_PPCARCH_H
#include <kernel/types.h>
#include <builtins.h>
ALWAYS_INLINE
inline uint64_t getSRR0()
{
register uint64_t srr0 = 0;
asm volatile("mfsrr0 %0" : "=r" (srr0));
return srr0;
}
ALWAYS_INLINE
inline uint64_t getSRR1()
{
register uint64_t srr1 = 0;
asm volatile("mfsrr1 %0" : "=r" (srr1));
return srr1;
}
ALWAYS_INLINE
inline void setSRR0(uint64_t _srr0)
{
register uint64_t srr0 = _srr0;
asm volatile("mtsrr0 %0" : : "r" (srr0));
}
ALWAYS_INLINE
inline void setSRR1(uint64_t _srr1)
{
register uint64_t srr1 = _srr1;
asm volatile("mtsrr1 %0" : : "r" (srr1));
}
ALWAYS_INLINE
inline uint64_t getHSRR0()
{
register uint64_t hsrr0 = 0;
asm volatile("mfspr %0, 314" : "=r" (hsrr0));
return hsrr0;
}
ALWAYS_INLINE
inline uint64_t getHSRR1()
{
register uint64_t hsrr1 = 0;
asm volatile("mfspr %0, 315" : "=r" (hsrr1));
return hsrr1;
}
ALWAYS_INLINE
inline void setHSRR0(uint64_t _hsrr0)
{
register uint64_t hsrr0 = _hsrr0;
asm volatile("mtspr 314, %0" : : "r" (hsrr0));
}
ALWAYS_INLINE
inline void setHSRR1(uint64_t _hsrr1)
{
register uint64_t hsrr1 = _hsrr1;
asm volatile("mtspr 315, %0" : : "r" (hsrr1));
}
ALWAYS_INLINE
inline uint64_t getPVR()
{
register uint64_t pvr = 0;
asm volatile("mfspr %0, 287" : "=r" (pvr));
return pvr;
}
ALWAYS_INLINE
inline uint64_t getPIR()
{
register uint64_t pir = 0;
asm volatile("mfspr %0, 1023" : "=r" (pir));
return pir;
}
ALWAYS_INLINE
inline uint64_t getSPRG3()
{
register uint64_t sprg3 = 0;
asm volatile("mfsprg3 %0" : "=r" (sprg3));
return sprg3;
}
ALWAYS_INLINE
inline void setSPRG3(uint64_t _sprg3)
{
register uint64_t sprg3 = _sprg3;
asm volatile("mtsprg3 %0" : : "r" (sprg3));
return;
}
ALWAYS_INLINE
inline uint64_t getMSR()
{
register uint64_t msr = 0;
asm volatile("mfmsr %0" : "=r" (msr));
return msr;
}
ALWAYS_INLINE
inline void setMSR(uint64_t _msr)
{
register uint64_t msr = _msr;
asm volatile("mtmsr %0; isync" :: "r" (msr));
}
ALWAYS_INLINE
inline uint64_t getDSISR()
{
register uint64_t dsisr = 0;
asm volatile("mfspr %0, 18" : "=r" (dsisr));
return dsisr;
}
ALWAYS_INLINE
inline uint64_t getDAR()
{
register uint64_t dar = 0;
asm volatile("mfspr %0, 19" : "=r" (dar));
return dar;
}
ALWAYS_INLINE
inline uint64_t getTB()
{
register uint64_t tb = 0;
asm volatile("mfspr %0, 268" : "=r" (tb));
return tb;
}
ALWAYS_INLINE
inline void setDEC(uint64_t _dec)
{
register uint64_t dec = _dec;
asm volatile("mtdec %0" :: "r" (dec));
}
ALWAYS_INLINE
inline void sync()
{
asm volatile("sync" ::: "memory");
}
ALWAYS_INLINE
inline void lwsync()
{
asm volatile("lwsync" ::: "memory");
}
ALWAYS_INLINE
inline void isync()
{
asm volatile("isync" ::: "memory");
}
ALWAYS_INLINE
inline void eieio()
{
asm volatile("eieio" ::: "memory");
}
ALWAYS_INLINE
inline uint64_t getHMER()
{
register uint64_t hmer = 0;
asm volatile("mfspr %0, 336" : "=r" (hmer));
return hmer;
}
ALWAYS_INLINE
inline void setHMER(uint64_t _hmer)
{
register uint64_t hmer = _hmer;
asm volatile("mtspr 336, %0" : : "r" (hmer));
return;
}
ALWAYS_INLINE
inline uint64_t getHEIR()
{
register uint64_t heir = 0;
asm volatile("mfspr %0, 339" : "=r" (heir));
return heir;
}
ALWAYS_INLINE
inline void setThreadPriorityLow()
{
asm volatile("or 1,1,1");
}
ALWAYS_INLINE
inline void setThreadPriorityHigh()
{
asm volatile("or 3,3,3");
}
ALWAYS_INLINE
inline void dcbf(void* _ptr)
{
register void* ptr = _ptr;
asm volatile("dcbf 0, %0" : : "b" (ptr) : "memory");
}
ALWAYS_INLINE
inline void dcbz(void* _ptr)
{
register void* ptr = _ptr;
asm volatile("dcbz 0, %0" : : "b" (ptr) : "memory");
}
ALWAYS_INLINE
inline void icbi(void* _ptr)
{
register void* ptr = _ptr;
asm volatile("icbi 0, %0" : : "b" (ptr) : "memory");
}
ALWAYS_INLINE
inline void doze()
{
asm volatile("doze");
}
ALWAYS_INLINE
inline void setScratch0Spr(uint64_t _data)
{
// Write to SPRC(276) to select the register
// 0x20 selects SCRATCH 0 SPR
// Write to SPRD(277) to write the data
// TODO This is per P7 Pervasive Spec. Is this the same for Salerno/Venice?
register uint64_t address = 0x20;
register uint64_t data = _data;
asm volatile("mtspr 276, %0\n"
"isync\n"
"mtspr 277, %1" :: "r" (address), "r" (data));
}
ALWAYS_INLINE
inline uint64_t getScratch0Spr()
{
// Write to SPRC(276) to select the register
// 0x20 selects SCRATCH 0 SPR
// Read from SPRD(277) to get the data
// TODO This is per P7 Pervasive Spec. Is this the same for Salerno/Venice?
register uint64_t address = 0x20;
register uint64_t data = 0;
asm volatile("mtspr 276, %1\n"
"isync\n"
"mfspr %0, 277" : "=r" (data) : "r" (address));
return data;
}
#endif
|
