blob: a7cce7e6b927191f392d7343870ea988cd31199c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
|
<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_setup_bars.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2018,2019 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<attributes>
<!-- ********************************************************************* -->
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_OMI_INBAND_BAR_BASE_ADDR_OFFSET</id>
<targetType>TARGET_TYPE_OMI, TARGET_TYPE_MC</targetType>
<description>
OMI inband BAR address offset.
Set by platform.
One Axone bar register is set per MC channel for MMIO and another
is set per MC channel for config space. The bar is shared between
both sub-channels each with an OCMB. The upper bit of the bar
size is used to determine which sub-channel is selected. This
means that for two OCMB's their config space is contiguous and
their MMIO space is contiguous. Therefore a single OCMB's MMIO
and config space cannot be contiguous. However, we can still
use one BAR attribute. The p9a_omi_setup_bars procedure can interleave
the config space and MMIO space as shown in the table bellow.
For example, both MMIO and config bar sizes are 2GB. The 2GB
bit becomes the selector for the subchannel. The 4GB bit becomes
the offset applied for MMIO operations.
Value is also set on MC to match the BAR offset of the child OMI with
lowest chip unit.
Each OCMB is assigned one base address attribute.
ocmb | BAR ATTRIBUTE | Type | Base reg - end addr | size | sub-ch
+-----+--------------------+------+-----------------------------------------+------+-------
ocmb0 | 0x0006030200000000 | cnfg | 0x0006030200000000 - 0x000603027FFFFFFF | 2GB | 0
ocmb1 | 0x0006030280000000 | cnfg | 0x0006030280000000 - 0x00060302FFFFFFFF | 2GB | 1
ocmb0 | N/A | mmio | 0x0006030300000000 - 0x000603037FFFFFFF | 2GB | 0
ocmb1 | N/A | mmio | 0x0006030380000000 - 0x00060303FFFFFFFF | 2GB | 1
+-----+--------------------+------+-----------------------------------------+------+-------
ocmb2 | 0x0006030400000000 | cnfg | 0x0006030400000000 - 0x000603047FFFFFFF | 2GB | 0
ocmb3 | 0x0006030480000000 | cnfg | 0x0006030480000000 - 0x00060304FFFFFFFF | 2GB | 1
ocmb2 | N/A | mmio | 0x0006030500000000 - 0x000603057FFFFFFF | 2GB | 0
ocmb3 | N/A | mmio | 0x0006030580000000 - 0x00060305FFFFFFFF | 2GB | 1
Used by p9a_omi_setup_bars
</description>
<valueType>uint64</valueType>
<platInit/>
<persistRuntime/>
</attribute>
<!-- ********************************************************************* -->
</attributes>
|
