path: root/src/import/chips/p9/procedures/xml/attribute_info/memory_spd_attributes.xml

<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
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<!-- $Source: chips/p9/procedures/xml/attribute_info/memory_spd_attributes.xml $ -->
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<!-- IBM CONFIDENTIAL                                                       -->
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<!-- EKB Project                                                            -->
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<!-- COPYRIGHT 2016                                                         -->
<!-- [+] International Business Machines Corp.                              -->
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<!-- IBM_PROLOG_END_TAG                                                     -->

<attributes>
    <attribute>
        <id>ATTR_EFF_DRAM_GEN</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          DRAM Device Type.
          Decodes SPD byte 2.
          Generation of memory: DDR3, DDR4.
          creator: mss_eff_config
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>EMPTY = 0, DDR3 = 1, DDR4 = 2</enum>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dram_gen</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DIMM_TYPE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Base Module Type.
          Decodes SPD Byte 3 (bits 3~0).
          Type of DIMM: RDIMM, UDIMM, LRDIMM as specified by the JEDIC standard.
          creator: mss_eff_config
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum> EMPTY = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3</enum>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dimm_type</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_HYBRID_MEMORY_TYPE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Hybrid Media.
          Decodes SPD Byte 3 (bits 6~4)
          creator: mss_eff_config
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum> NONE = 0, NVDIMM = 1</enum>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_hybrid_memory_type</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_HYBRID</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Hybrid.
          Decodes SPD Byte 3 (bit 7)
          creator: mss_eff_config
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum> NOT_HYBRID = 0, IS_HYBRID= 1</enum>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_hybrid</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_DENSITY</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            DRAM Density.
            Decodes SPD Byte 4 (bits 3~0).
            Total SDRAM capacity per die.
            For multi-die stacks (DDP, QDP, or 3DS), this represents
            the capacity of each DRAM die in the stack.
            creator: mss_eff_config
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2 2</array>
        <mssUnit>Gb</mssUnit>
        <mssAccessorName>eff_dram_density</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_BANK_BITS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Number of DRAM bank address bits.
            Actual number of banks is 2^N, where
            N is the number of bank address bits.
            Decodes SPD Byte 4 (bits 5~4).
            creator: spd_decoder
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dram_bank_bits</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_BANK_GROUP_BITS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Bank Groups Bits.
            Decoded SPD Byte 4 (bits 7~6).
            Actual number of bank groups is 2^N,
            where N is the number of bank address bits.
            This value represents the number of bank groups
            into which the memory array is divided.
            creator: mss_eff_config
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dram_bank_group_bits</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_COLUMN_BITS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Column Address Bits.
            Decoded SPD Byte 5 (bits 2~0).
            Actual number of DRAM columns is 2^N,
            where N is the number of column address bits
            creator: mss_eff_config
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dram_columns_bits</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_ROW_BITS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Row Address Bits.
            Decodes Byte 5 (bits 5~3).
            Number of DRAM column address bits.
            Actual number of DRAM rows is 2^N,
            where N is the number of row address bits
            creator: mss_eff_config
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dram_row_bits</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_PRIM_STACK_TYPE</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Primary SDRAM Package Type.
            Decodes Byte 6.
            This byte defines the primary set of SDRAMs.
            Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = 3DS
            creator: mss_eff_config
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum> SDP = 0, DDP_QDP = 1, 3DS = 2</enum>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_prim_stack_type</mssAccessorName>
    </attribute>
    <attribute>
        <id>ATTR_EFF_DRAM_PPR</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Post Package Repair. Used in various locations and is evaluated in mss_eff_cnfg.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>NOT_SUPPORTED = 0, SUPPORTED = 1</enum>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dram_ppr</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_SOFT_PPR</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Soft Post Package Repair. Used in various locations and is evaluated in mss_eff_cnfg.
            creator: mss_eff_cnfg
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>NOT_SUPPORTED = 0, SUPPORTED = 1</enum>
        <writeable/>
        <array>2 2</array>
        <mssAccessorName>eff_dram_soft_ppr</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TRCD</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Minimum RAS to CAS Delay Time
          in nck (number of clock cyles).
          Decodes SPD byte 25 (7~0) and byte 112 (7~0).
          Each memory channel will have a value.
          creator: eff_config
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_trcd</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TRP</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          SDRAM Row Precharge Delay Time
          in nck (number of clock cycles).
          Decodes SPD byte 26 (bits 7~0) and byte 121 (bits 7~0).
          Each memory channel will have a value.
          creator: eff_config
          consumer: various
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_trp</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TRAS</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Minimum Active to Precharge Delay Time
          in nck (number of clock cycles).
          Decodes SPD byte 27 (bits 3~0) and byte 28 (7~0).
          Each memory channel will have a value.
          creator: mss_eff_cnfg_timing
          consumer: various
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_tras</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TRC</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Minimum Active to Active/Refresh Delay
          in nck (number of clock cyles).
          Decodes SPD byte 27 (bits 7~4), byte 29 (bits 7~0), and byte 120.
          Each memory channel will have a value.
          creator: eff_confg
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_trc</mssAccessorName>
    </attribute>

    <attribute>
      <id>ATTR_EFF_DRAM_TRFC</id>
      <targetType>TARGET_TYPE_MCS</targetType>
      <description>
        DDR4 Spec defined as Refresh Cycle Time (tRFC).
        SPD Spec refers it to the Minimum Refresh Recovery Delay Time.
        In nck (number of clock cyles).
        Decodes SPD byte 31 (bits 15~8) and byte 30 (bits 7~0) for tRFC1.
        Decodes SPD byte 33 (bits 15~8) and byte 32 (bits 7~0) for tRFC2.
        Decodes SPD byte 35 (bits 15~8) and byte 34 (bits 7~0) for tRFC4.
        Selected tRFC value depends on MRW attribute that selects refresh mode.
        For 3DS, The tRFC time to the same logical rank is defined as tRFC_slr and is
        specificed as the value as for a monolithic DDR4 SDRAM of equivalent density.
        creator: eff_config
        consumer: various
        firmware notes: none</description>
    <initToZero></initToZero>
      <valueType>uint16</valueType>
      <writeable/>
      <array> 2 </array>
      <mssUnits> nck </mssUnits>
      <mssAccessorName>eff_dram_trfc</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TFAW</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Minimum Four Activate Window Delay Time
          in nck (number of clock cycles).
          Decodes SPD byte 36 (bits 3~0) and byte 37 (bits 7~0).
          For 3DS, tFAW time to the same logical rank is defined as
          tFAW_slr_x4 or tFAW_slr_x8 (for x4 and x8 devices only) and
          specificed as the value as for a monolithic DDR4 SDRAM
          equivalent density.
          Each memory channel will have a value.
          creator: eff_cnfg
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_tfaw</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TRRD_S</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Minimum Activate to Activate Delay Time, different bank group
          in nck (number of clock cycles).
          Decodes SPD byte 38 (bits 7~0).
          For 3DS, The tRRD_S time to a different bank group in the
          same logical rank is defined as tRRD_slr and is
          specificed as the value as for a monolithic
          DDR4 SDRAM of equivalent density.
          Each memory channel will have a value.
          creator: eff_confg
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_trrd_s</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TRRD_L</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Minimum Activate to Activate Delay Time, same bank group
          in nck (number of clock cycles).
          Decodes SPD byte 39 (bits 7~0).
          For 3DS, The tRRD_L time to the same bank group in the
          same logical rank is defined as tRRD_L_slr and is
          specificed as the value as for a monolithic
          DDR4 SDRAM of equivalent density.
          Each memory channel will have a value.
          creator: eff_confg
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
      <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_trrd_l</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TCCD_L</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Minimum CAS to CAS Delay Time, same bank group
          in nck (number of clock cycles).
          Decodes SPD byte 40 (bits 7~0) and byte 117 (bits 7~0).
          This is for DDR4 MRS6.
          Each memory channel will have a value.
          Creator: eff_config
          Consumer:various
          Firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <enum>4NCK = 4, 5NCK = 5, 6NCK = 6, 7NCK = 7, 8NCK = 8</enum>
        <writeable/>
        <array> 2 </array>
        <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_tccd_l</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TWR</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            Minimum Write Recovery Time.
            Decodes SPD byte 41 (bits 3~0) and byte 42 (bits 7~0).
            Each memory channel will have a value.
            creator: mss_eff_cnfg_timing
            consumer: various
            firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_twr</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TWTR_S</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Minimum Write to Read Time, different bank group
          in nck (number of clock cycles).
          Decodes SPD byte 43 (3~0) and byte 44 (bits 7~0).
          Each memory channel will have a value.
          creator: eff_config
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_twtr_s</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TWTR_L</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Minimum Write to Read Time, same bank group
          in nck (number of clock cycles).
          Decodes byte 43 (7~4) and byte 45 (bits 7~0).
          Each memory channel will have a value.
          creator: eff_config
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <array> 2 </array>
        <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_twtr_l</mssAccessorName>
    </attribute>

    <attribute>
        <id>ATTR_EFF_DRAM_TMAW</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
          Maximum Activate Window
          in nck (number of clock cycles).
          Decodes SPD byte 7 (bits 5~4).
          Depends on tREFI multiplier.
          Each memory channel will have a value.
          creator: mss_eff_cnfg
          consumer: various
          firmware notes: none
        </description>
        <initToZero></initToZero>
        <valueType>uint16</valueType>
        <writeable/>
        <array> 2 </array>
        <mssUnits> nck </mssUnits>
        <mssAccessorName>eff_dram_tmaw</mssAccessorName>
    </attribute>

</attributes>