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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2016,2019 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<attributes>
<attribute>
<id>ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
Each MCA value is a 64-bit vector, where each byte represents an unsupported rank configuration.
Each nibble in the byte represents the total count of ranks (master and slave)
on each DIMM. The left-most nibble represents slot 0 and the right represents 1.
</description>
<valueType>uint64</valueType>
<array>2</array>
<platInit/>
<initToZero/>
<default> 0 </default>
<mssAccessorName>mrw_unsupported_rank_config</mssAccessorName>
</attribute>
</attributes>
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