summaryrefslogtreecommitdiffstats
path: root/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld.H
blob: 5b93db5fbcf78f43a970a1066944120d951e2dd7 (plain) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287
5288
5289
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425
5426
5427
5428
5429
5430
5431
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672
5673
5674
5675
5676
5677
5678
5679
5680
5681
5682
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721
5722
5723
5724
5725
5726
5727
5728
5729
5730
5731
5732
5733
5734
5735
5736
5737
5738
5739
5740
5741
5742
5743
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775
5776
5777
5778
5779
5780
5781
5782
5783
5784
5785
5786
5787
5788
5789
5790
5791
5792
5793
5794
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868
5869
5870
5871
5872
5873
5874
5875
5876
5877
5878
5879
5880
5881
5882
5883
5884
5885
5886
5887
5888
5889
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901
5902
5903
5904
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
5979
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042
6043
6044
6045
6046
6047
6048
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084
6085
6086
6087
6088
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117
6118
6119
6120
6121
6122
6123
6124
6125
6126
6127
6128
6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155
6156
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174
6175
6176
6177
6178
6179
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
6230
6231
6232
6233
6234
6235
6236
6237
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254
6255
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265
6266
6267
6268
6269
6270
6271
6272
6273
6274
6275
6276
6277
6278
6279
6280
6281
6282
6283
6284
6285
6286
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316
6317
6318
6319
6320
6321
6322
6323
6324
6325
6326
6327
6328
6329
6330
6331
6332
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348
6349
6350
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406
6407
6408
6409
6410
6411
6412
6413
6414
6415
6416
6417
6418
6419
6420
6421
6422
6423
6424
6425
6426
6427
6428
6429
6430
6431
6432
6433
6434
6435
6436
6437
6438
6439
6440
6441
6442
6443
6444
6445
6446
6447
6448
6449
6450
6451
6452
6453
6454
6455
6456
6457
6458
6459
6460
6461
6462
6463
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476
6477
6478
6479
6480
6481
6482
6483
6484
6485
6486
6487
6488
6489
6490
6491
6492
6493
6494
6495
6496
6497
6498
6499
6500
6501
6502
6503
6504
6505
6506
6507
6508
6509
6510
6511
6512
6513
6514
6515
6516
6517
6518
6519
6520
6521
6522
6523
6524
6525
6526
6527
6528
6529
6530
6531
6532
6533
6534
6535
6536
6537
6538
6539
6540
6541
6542
6543
6544
6545
6546
6547
6548
6549
6550
6551
6552
6553
6554
6555
6556
6557
6558
6559
6560
6561
6562
6563
6564
6565
6566
6567
6568
6569
6570
6571
6572
6573
6574
6575
6576
6577
6578
6579
6580
6581
6582
6583
6584
6585
6586
6587
6588
6589
6590
6591
6592
6593
6594
6595
6596
6597
6598
6599
6600
6601
6602
6603
6604
6605
6606
6607
6608
6609
6610
6611
6612
6613
6614
6615
6616
6617
6618
6619
6620
6621
6622
6623
6624
6625
6626
6627
6628
6629
6630
6631
6632
6633
6634
6635
6636
6637
6638
6639
6640
6641
6642
6643
6644
6645
6646
6647
6648
6649
6650
6651
6652
6653
6654
6655
6656
6657
6658
6659
6660
6661
6662
6663
6664
6665
6666
6667
6668
6669
6670
6671
6672
6673
6674
6675
6676
6677
6678
6679
6680
6681
6682
6683
6684
6685
6686
6687
6688
6689
6690
6691
6692
6693
6694
6695
6696
6697
6698
6699
6700
6701
6702
6703
6704
6705
6706
6707
6708
6709
6710
6711
6712
6713
6714
6715
6716
6717
6718
6719
6720
6721
6722
6723
6724
6725
6726
6727
6728
6729
6730
6731
6732
6733
6734
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745
6746
6747
6748
6749
6750
6751
6752
6753
6754
6755
6756
6757
6758
6759
6760
6761
6762
6763
6764
6765
6766
6767
6768
6769
6770
6771
6772
6773
6774
6775
6776
6777
6778
6779
6780
6781
6782
6783
6784
6785
6786
6787
6788
6789
6790
6791
6792
6793
6794
6795
6796
6797
6798
6799
6800
6801
6802
6803
6804
6805
6806
6807
6808
6809
6810
6811
6812
6813
6814
6815
6816
6817
6818
6819
6820
6821
6822
6823
6824
6825
6826
6827
6828
6829
6830
6831
6832
6833
6834
6835
6836
6837
6838
6839
6840
6841
6842
6843
6844
6845
6846
6847
6848
6849
6850
6851
6852
6853
6854
6855
6856
6857
6858
6859
6860
6861
6862
6863
6864
6865
6866
6867
6868
6869
6870
6871
6872
6873
6874
6875
6876
6877
6878
6879
6880
6881
6882
6883
6884
6885
6886
6887
6888
6889
6890
6891
6892
6893
6894
6895
6896
6897
6898
6899
6900
6901
6902
6903
6904
6905
6906
6907
6908
6909
6910
6911
6912
6913
6914
6915
6916
6917
6918
6919
6920
6921
6922
6923
6924
6925
6926
6927
6928
6929
6930
6931
6932
6933
6934
6935
6936
6937
6938
6939
6940
6941
6942
6943
6944
6945
6946
6947
6948
6949
6950
6951
6952
6953
6954
6955

/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld.H $ */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2018,2019                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */

#ifndef __EXPLR_SCOM_ADDRESSES_FLD_H
#define __EXPLR_SCOM_ADDRESSES_FLD_H


static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_SPARE                            = 0   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_SPARE_LEN                        = 4   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PM_CDR_TIMER                     = 4   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PM_CDR_TIMER_LEN                 = 4   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PM_DIDT_TIMER                    = 8   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PM_DIDT_TIMER_LEN                = 4   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PSAVE_STS_ENABLE                 = 12  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_RECAL_TIMER                      = 13  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_RECAL_TIMER_LEN                  = 3   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_1US_TMR                          = 16  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_1US_TMR_LEN                      = 12  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_DBG_EN                           = 28  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_DBG_SEL                          = 29  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_DBG_SEL_LEN                      = 3   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_RD_RST                           = 32  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PRE_SCALAR                       = 33  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PRE_SCALAR_LEN                   = 3   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_FREEZE                           = 36  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PORT_SEL                         = 37  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PORT_SEL_LEN                     = 3   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_PS                         = 40  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_PS_LEN                     = 2   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_ES                         = 42  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_ES_LEN                     = 2   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_PS                         = 44  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_PS_LEN                     = 2   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_ES                         = 46  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_ES_LEN                     = 2   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_PS                         = 48  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_PS_LEN                     = 2   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_ES                         = 50  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_ES_LEN                     = 2   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_PS                         = 52  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_PS_LEN                     = 2   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_ES                         = 54  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_ES_LEN                     = 2   ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_PE                         = 56  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_PE                         = 57  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_PE                         = 58  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_PE                         = 59  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_EN                         = 60  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_EN                         = 61  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_EN                         = 62  ;
static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_EN                         = 63  ;

static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_ENABLE                          = 0   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_CFG_SPARE                       = 1   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_CFG_SPARE_LEN                   = 5   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_CFG_TL_CREDITS                  = 6   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_CFG_TL_CREDITS_LEN              = 6   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS                = 12  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS_LEN            = 4   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS                = 16  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS_LEN            = 4   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER              = 20  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER_LEN          = 4   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES             = 24  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES_LEN         = 4   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DEBUG_SELECT                    = 28  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DEBUG_SELECT_LEN                = 3   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DEBUG_ENABLE                    = 31  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DL2TL_DATA_PARITY_INJECT        = 32  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DL2TL_CONTROL_PARITY_INJECT     = 33  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_ECC_UE_INJECTION                = 34  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_ECC_CE_INJECTION                = 35  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_FP_DISABLE                      = 36  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_UNUSED2                         = 37  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TX_LN_REV_ENA                   = 38  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_128_130_ENCODING_ENABLED        = 39  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT                  = 40  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT_LEN              = 4   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_RUNLANE_OVRD_ENABLE             = 44  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_PWRMGT_ENABLE                   = 45  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_X1_BACKOFF_ENABLE               = 46  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_X4_BACKOFF_ENABLE               = 47  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_SUPPORTED_MODES                 = 48  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_SUPPORTED_MODES_LEN             = 4   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TRAIN_MODE                      = 52  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TRAIN_MODE_LEN                  = 4   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_VERSION                         = 56  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_VERSION_LEN                     = 6   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_RETRAIN                         = 62  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_RESET                           = 63  ;

static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_CFG1_SPARE                      = 0   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_CFG1_SPARE_LEN                  = 2   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_LANE_WIDTH                      = 2   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_LANE_WIDTH_LEN                  = 2   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_PREIPL_PRBS_ENA                 = 4   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME                = 5   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME_LEN            = 3   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_B_HYSTERESIS                    = 8   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_B_HYSTERESIS_LEN                = 4   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_A_HYSTERESIS                    = 12  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_A_HYSTERESIS_LEN                = 4   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_B_PATTERN_LENGTH                = 16  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_B_PATTERN_LENGTH_LEN            = 2   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_A_PATTERN_LENGTH                = 18  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_A_PATTERN_LENGTH_LEN            = 2   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_TX_PERF_DEGRADED                = 20  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_TX_PERF_DEGRADED_LEN            = 2   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RX_PERF_DEGRADED                = 22  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RX_PERF_DEGRADED_LEN            = 2   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_TX_LANES_DISABLE                = 24  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_TX_LANES_DISABLE_LEN            = 8   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RX_LANES_DISABLE                = 32  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RX_LANES_DISABLE_LEN            = 8   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_CFG1_SPARE1                     = 40  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_CFG1_SPARE1_LEN                 = 4   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RESET_ERR_HLD                   = 44  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RESET_ERR_CAP                   = 45  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RESET_TSHD_REG                  = 46  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RESET_RMT_MSG                   = 47  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_DIRECTION            = 48  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_RATE                 = 49  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_RATE_LEN             = 3   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_LANE                 = 52  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_LANE_LEN             = 3   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_ERROR                = 55  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_TIME                       = 56  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_TIME_LEN                   = 4   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_THRESHOLD                  = 60  ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_THRESHOLD_LEN              = 3   ;
static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_ENA                        = 63  ;

static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_BITS0                          = 32  ;
static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_BITS0_LEN                      = 32  ;

static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_RESERVED                          = 0   ;
static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_RESERVED_LEN                      = 55  ;
static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_PRBS7_RESET                       = 55  ;
static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_PRBS7_STATUS                      = 56  ;
static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_PRBS7_STATUS_LEN                  = 8   ;

static const uint8_t EXPLR_DLX_DL0_DLX_CONFIG_CFG_DLX0                         = 32  ;
static const uint8_t EXPLR_DLX_DL0_DLX_CONFIG_CFG_DLX0_LEN                     = 32  ;

static const uint8_t EXPLR_DLX_DL0_DLX_INFO_STS                                = 0   ;
static const uint8_t EXPLR_DLX_DL0_DLX_INFO_STS_LEN                            = 64  ;

static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L7                           = 0   ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L7_LEN                       = 8   ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L6                           = 8   ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L6_LEN                       = 8   ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L5                           = 16  ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L5_LEN                       = 8   ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L4                           = 24  ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L4_LEN                       = 8   ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L3                           = 32  ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L3_LEN                       = 8   ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L2                           = 40  ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L2_LEN                       = 8   ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L1                           = 48  ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L1_LEN                       = 8   ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L0                           = 56  ;
static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L0_LEN                       = 8   ;

static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_11                         = 16  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_11_LEN                     = 4   ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_10                         = 20  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_10_LEN                     = 4   ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_9                          = 24  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_9_LEN                      = 4   ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_8                          = 28  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_8_LEN                      = 4   ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_7                          = 32  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_7_LEN                      = 4   ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_6                          = 36  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_6_LEN                      = 4   ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_5                          = 40  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_5_LEN                      = 4   ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_4                          = 44  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_4_LEN                      = 4   ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_3                          = 48  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_3_LEN                      = 4   ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_2                          = 52  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_2_LEN                      = 4   ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_1                          = 56  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_1_LEN                      = 4   ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_0                          = 60  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_0_LEN                      = 4   ;

static const uint8_t EXPLR_DLX_DL0_ERROR_CAPTURE_INFO                          = 1   ;
static const uint8_t EXPLR_DLX_DL0_ERROR_CAPTURE_INFO_LEN                      = 63  ;

static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_47                          = 16  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_46                          = 17  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_45                          = 18  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_44                          = 19  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_43                          = 20  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_42                          = 21  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_41                          = 22  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_40                          = 23  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_39                          = 24  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_38                          = 25  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_37                          = 26  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_36                          = 27  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_35                          = 28  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_34                          = 29  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_33                          = 30  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_32                          = 31  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_31                          = 32  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_30                          = 33  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_29                          = 34  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_28                          = 35  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_27                          = 36  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_26                          = 37  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_25                          = 38  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_24                          = 39  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_23                          = 40  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_22                          = 41  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_21                          = 42  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_20                          = 43  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_19                          = 44  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_18                          = 45  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_17                          = 46  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_16                          = 47  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_15                          = 48  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_14                          = 49  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_13                          = 50  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_12                          = 51  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_11                          = 52  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_10                          = 53  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_09                          = 54  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_08                          = 55  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_07                          = 56  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_06                          = 57  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_05                          = 58  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_04                          = 59  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_03                          = 60  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_02                          = 61  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_01                          = 62  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_00                          = 63  ;

static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_47                               = 16  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_46                               = 17  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_45                               = 18  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_44                               = 19  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_43                               = 20  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_42                               = 21  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_41                               = 22  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_40                               = 23  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_39                               = 24  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_38                               = 25  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_37                               = 26  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_36                               = 27  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_35                               = 28  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_34                               = 29  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_33                               = 30  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_32                               = 31  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_31                               = 32  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_30                               = 33  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_29                               = 34  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_28                               = 35  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_27                               = 36  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_26                               = 37  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_25                               = 38  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_24                               = 39  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_23                               = 40  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_22                               = 41  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_21                               = 42  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_20                               = 43  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_19                               = 44  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_18                               = 45  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_17                               = 46  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_16                               = 47  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_15                               = 48  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_14                               = 49  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_13                               = 50  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_12                               = 51  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_11                               = 52  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_10                               = 53  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_09                               = 54  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_08                               = 55  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_07                               = 56  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_06                               = 57  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_05                               = 58  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_04                               = 59  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_03                               = 60  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_02                               = 61  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_01                               = 62  ;
static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_00                               = 63  ;

static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TRAINED_MODE                     = 0   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TRAINED_MODE_LEN                 = 4   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RX_LANE_REVERSED                 = 4   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TX_LANE_REVERSED                 = 5   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD0                            = 6   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ACK_PTRS_EQUAL                   = 7   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD1                            = 8   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD1_LEN                        = 4   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_REQUESTED_LN_WIDTH               = 12  ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_REQUESTED_LN_WIDTH_LEN           = 2   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ACTUAL_LN_WIDTH                  = 14  ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ACTUAL_LN_WIDTH_LEN              = 2   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TX_TRAINED_LANES                 = 16  ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TX_TRAINED_LANES_LEN             = 8   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RX_TRAINED_LANES                 = 24  ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RX_TRAINED_LANES_LEN             = 8   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ENDPOINT_INFO                    = 32  ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ENDPOINT_INFO_LEN                = 16  ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD2                            = 48  ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TRAINING_STATE_MACHINE           = 49  ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TRAINING_STATE_MACHINE_LEN       = 3   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD3                            = 52  ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD3_LEN                        = 3   ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_DESKEW_DONE                      = 55  ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_LANES_DISABLED                   = 56  ;
static const uint8_t EXPLR_DLX_DL0_STATUS_STS_LANES_DISABLED_LEN               = 8   ;

static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_PATTERN_A            = 0   ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_PATTERN_A_LEN        = 8   ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_PATTERN_B            = 8   ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_PATTERN_B_LEN        = 8   ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_SYNC_PATTERN            = 16  ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_SYNC_PATTERN_LEN        = 8   ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_PHY_INIT_DONE           = 24  ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_PHY_INIT_DONE_LEN       = 8   ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_BLOCK_LOCKED            = 32  ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_BLOCK_LOCKED_LEN        = 8   ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS1                  = 40  ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS1_LEN              = 8   ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS2                  = 48  ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS2_LEN              = 8   ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS3                  = 56  ;
static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS3_LEN              = 8   ;

static const uint8_t EXPLR_DLX_ERR_HOLD_LAT_FIR_MASK_PAR                       = 0   ;
static const uint8_t EXPLR_DLX_ERR_HOLD_LAT_FIR_ACTION0_PAR                    = 1   ;
static const uint8_t EXPLR_DLX_ERR_HOLD_LAT_FIR_ACTION1_PAR                    = 2   ;

static const uint8_t EXPLR_DLX_ERR_MASK_LAT_FIR_PAR                            = 0   ;
static const uint8_t EXPLR_DLX_ERR_MASK_LAT_FIR_ACTION0_PAR                    = 1   ;
static const uint8_t EXPLR_DLX_ERR_MASK_LAT_FIR_ACTION1_PAR                    = 2   ;

static const uint8_t EXPLR_DLX_MC_OMI_FIR_ACTION0_REG_ACTION0                  = 0   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_ACTION0_REG_ACTION0_LEN              = 64  ;

static const uint8_t EXPLR_DLX_MC_OMI_FIR_ACTION1_REG_ACTION1                  = 0   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_ACTION1_REG_ACTION1_LEN              = 64  ;

static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL0_ERROR                   = 0   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL0_ERROR_LEN               = 20  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL1_ERROR                   = 20  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL1_ERROR_LEN               = 20  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL2_ERROR                   = 40  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL2_ERROR_LEN               = 20  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_PERF_MON_WRAPPED            = 60  ;

static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_FATAL_ERROR                  = 0   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_DATA_UE                      = 1   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_FLIT_CE                      = 2   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_CRC_ERROR                    = 3   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_NACK                         = 4   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_X4_MODE                      = 5   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_EDPL                         = 6   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_TIMEOUT                      = 7   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_REMOTE_RETRAIN               = 8   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ERROR_RETRAIN                = 9   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_EDPL_RETRAIN                 = 10  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_TRAINED                      = 11  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR0                = 12  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR1                = 13  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR2                = 14  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR3                = 15  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR4                = 16  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR5                = 17  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR6                = 18  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR7                = 19  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_FATAL_ERROR                  = 20  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_DATA_UE                      = 21  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_FLIT_CE                      = 22  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_CRC_ERROR                    = 23  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_NACK                         = 24  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_X4_MODE                      = 25  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_EDPL                         = 26  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_TIMEOUT                      = 27  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_REMOTE_RETRAIN               = 28  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ERROR_RETRAIN                = 29  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_EDPL_RETRAIN                 = 30  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_TRAINED                      = 31  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR0                = 32  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR1                = 33  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR2                = 34  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR3                = 35  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR4                = 36  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR5                = 37  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR6                = 38  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR7                = 39  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_FATAL_ERROR                  = 40  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_DATA_UE                      = 41  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_FLIT_CE                      = 42  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_CRC_ERROR                    = 43  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_NACK                         = 44  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_X4_MODE                      = 45  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_EDPL                         = 46  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_TIMEOUT                      = 47  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_REMOTE_RETRAIN               = 48  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ERROR_RETRAIN                = 49  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_EDPL_RETRAIN                 = 50  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_TRAINED                      = 51  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR0                = 52  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR1                = 53  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR2                = 54  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR3                = 55  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR4                = 56  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR5                = 57  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR6                = 58  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR7                = 59  ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_PERF_MON_WRAPPED                 = 60  ;

static const uint8_t EXPLR_DLX_MC_OMI_FIR_WOF_REG_WOF                          = 0   ;
static const uint8_t EXPLR_DLX_MC_OMI_FIR_WOF_REG_WOF_LEN                      = 64  ;

static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU3                               = 0   ;
static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU3_LEN                           = 16  ;
static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU2                               = 16  ;
static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU2_LEN                           = 16  ;
static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU1                               = 32  ;
static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU1_LEN                           = 16  ;
static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU0                               = 48  ;
static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU0_LEN                           = 16  ;

static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ_MODE      = 0   ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ           = 1   ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ_MODE      = 2   ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ           = 3   ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_RESERVED_4                     = 4   ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_DISABLE_2N_MODE                = 5   ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_RESERVED_6_14                  = 6   ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_RESERVED_6_14_LEN              = 9   ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_READ_RESPONSE_DELAY_ENABLE     = 15  ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0      = 16  ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0_LEN  = 16  ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1      = 32  ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1_LEN  = 16  ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2      = 48  ;
static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2_LEN  = 16  ;

static const uint8_t EXPLR_MCBIST_CCS_CNTLQ_START                              = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_CNTLQ_STOP                               = 1   ;
static const uint8_t EXPLR_MCBIST_CCS_CNTLQ_UNPAUSE                            = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA0Q_DATA_0_63                   = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA0Q_DATA_0_63_LEN               = 64  ;

static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_DATA_64_79                  = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_DATA_64_79_LEN              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_NTTM_READ_DELAY             = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_NTTM_READ_DELAY_LEN         = 16  ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0               = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0_LEN           = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS                 = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS                 = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS                 = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS                 = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_31                 = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_31_LEN             = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_28_31              = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_28_31_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13            = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13_LEN        = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_17              = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_1            = 15  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_RESETN                  = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1                = 17  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_0            = 19  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ACTN                    = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_16              = 21  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_15              = 22  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_14              = 23  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CKE                     = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CKE_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_28                 = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_28_LEN             = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1                 = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1                 = 34  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3                 = 36  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CID_2                   = 38  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_39                 = 39  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_NESTED_LOOP_CNT             = 40  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_NESTED_LOOP_CNT_LEN         = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ODT                     = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_52_54              = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_52_54_LEN          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_PAUSE_INSTR                 = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CAL_TYPE                = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CAL_TYPE_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_PARITY                  = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_2                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE             = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE_LEN         = 2   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_IDLES                       = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_IDLES_LEN                   = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT              = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT_LEN          = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA          = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA_LEN      = 20  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_READ_COMPARE_REQUIRED       = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_DDR_CAL_RANK                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_DDR_CAL_RANK_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_DDR_CALIBRATION_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_END                         = 58  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_GOTO_CMD                    = 59  ;
static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_GOTO_CMD_LEN                = 5   ;

static const uint8_t EXPLR_MCBIST_CCS_MODEQ_STOP_ON_ERR                        = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_UE_DISABLE                         = 1   ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL             = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL_LEN         = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_RESERVED_4_6                       = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_RESERVED_4_6_LEN                   = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_TRACE_SELECT_DQBYPASS              = 7   ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT                = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_LEN            = 16  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_CFG_PARITY_AFTER_CMD               = 24  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_NESTED_LOOP_ENABLE                 = 25  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_COPY_CKE_TO_SPARE_CKE              = 26  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CHK              = 27  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CORRECTION       = 28  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_CFG_DGEN_FIXED_MODE                = 29  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT           = 30  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13              = 32  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13_LEN          = 14  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_17                = 46  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_1              = 47  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1                  = 48  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1_LEN              = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_0              = 50  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ACTN                      = 51  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_16                = 52  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_15                = 53  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_14                = 54  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_NTTM_MODE                          = 55  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY                   = 56  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN               = 4   ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2                    = 60  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE                  = 61  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_PARITY                    = 62  ;
static const uint8_t EXPLR_MCBIST_CCS_MODEQ_PAUSE_DISABLE                      = 63  ;

static const uint8_t EXPLR_MCBIST_CCS_STATQ_IP                                 = 0   ;
static const uint8_t EXPLR_MCBIST_CCS_STATQ_DONE                               = 1   ;
static const uint8_t EXPLR_MCBIST_CCS_STATQ_FAIL                               = 2   ;
static const uint8_t EXPLR_MCBIST_CCS_STATQ_FAIL_TYPE                          = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_STATQ_FAIL_TYPE_LEN                      = 3   ;
static const uint8_t EXPLR_MCBIST_CCS_STATQ_MCBIST_SUBTEST_IP                  = 6   ;
static const uint8_t EXPLR_MCBIST_CCS_STATQ_FAIL_RCD                           = 7   ;
static const uint8_t EXPLR_MCBIST_CCS_STATQ_PAUSED                             = 8   ;
static const uint8_t EXPLR_MCBIST_CCS_STATQ_CE                                 = 9   ;

static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_ENABLE                      = 0   ;
static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01           = 1   ;
static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01_LEN       = 11  ;
static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23           = 12  ;
static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23_LEN       = 11  ;
static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01               = 23  ;
static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01_LEN           = 11  ;
static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23               = 34  ;
static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23_LEN           = 11  ;
static const uint8_t EXPLR_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_TRIGGER            = 45  ;
static const uint8_t EXPLR_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_RESET              = 46  ;
static const uint8_t EXPLR_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_ARM                = 47  ;

static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_ENABLE                      = 0   ;
static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT            = 1   ;
static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT_LEN        = 2   ;
static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL             = 3   ;
static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL_LEN         = 20  ;
static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL               = 23  ;
static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL_LEN           = 20  ;
static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL                 = 43  ;
static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL_LEN             = 20  ;
static const uint8_t EXPLR_MCBIST_DBGCFG1Q_RESERVED_63                         = 63  ;

static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL              = 0   ;
static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL_LEN          = 20  ;
static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL              = 20  ;
static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL_LEN          = 20  ;
static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL              = 40  ;
static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL_LEN          = 20  ;
static const uint8_t EXPLR_MCBIST_DBGCFG2Q_RESERVED_60_63                      = 60  ;
static const uint8_t EXPLR_MCBIST_DBGCFG2Q_RESERVED_60_63_LEN                  = 4   ;

static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL              = 0   ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL_LEN          = 20  ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL             = 20  ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL_LEN         = 3   ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL             = 23  ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL_LEN         = 3   ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL             = 26  ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL_LEN         = 3   ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL             = 29  ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL_LEN         = 3   ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_OUTPUT_PULSE                = 32  ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE       = 33  ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE_LEN   = 4   ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE        = 37  ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE_LEN    = 4   ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE      = 41  ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN  = 4   ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE                   = 45  ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE_LEN               = 6   ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE                   = 51  ;
static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE_LEN               = 8   ;

static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_A                    = 0   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_A_LEN                = 4   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_B                    = 4   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_B_LEN                = 4   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_C                    = 8   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_C_LEN                = 4   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_D                    = 12  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_D_LEN                = 4   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_A                    = 16  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_A_LEN                = 4   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_B                    = 20  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_B_LEN                = 4   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_C                    = 24  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_C_LEN                = 4   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_D                    = 28  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_D_LEN                = 4   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TLXR_SHIFT_SEL                  = 32  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TLXT_SHIFT_SEL                  = 33  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_WDF_SHIFT_SEL                   = 34  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_RDF_SHIFT_SEL                   = 35  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_SRQ_SHIFT_SEL                   = 36  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_MCB_SHIFT_SEL                   = 37  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_MMIO_SHIFT_SEL                  = 38  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DLX_SHIFT_SEL                   = 39  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE0_TRACE_ERR_SEL            = 40  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE0_TRACE_ERR_SEL_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE1_TRACE_ERR_SEL            = 44  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE1_TRACE_ERR_SEL_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_SLICE_SEL_A                 = 48  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_SLICE_SEL_A_LEN             = 4   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_SLICE_SEL_B                 = 52  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_SLICE_SEL_B_LEN             = 4   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_RESERVED_56                     = 56  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_GROUP_SEL0                  = 57  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_GROUP_SEL0_LEN              = 3   ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_RESERVED_60                     = 60  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_GROUP_SEL1                  = 61  ;
static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_GROUP_SEL1_LEN              = 3   ;

static const uint8_t EXPLR_MCBIST_ERR_HOLD_LAT_FIR_MASK_PAR                    = 0   ;
static const uint8_t EXPLR_MCBIST_ERR_HOLD_LAT_FIR_ACTION0_PAR                 = 1   ;
static const uint8_t EXPLR_MCBIST_ERR_HOLD_LAT_FIR_ACTION1_PAR                 = 2   ;

static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBECTLQ_PE                        = 0   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCS_STATQ_PE                      = 1   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCS_MODEQ_PE                      = 2   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_RCD_LRDIM_CNTL_WORD0_15Q_PE       = 3   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCSARRERRINJQ_PE                  = 4   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCS_FIXED_DATA0Q_PE               = 5   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCS_FIXED_DATA1Q_PE               = 6   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAMR0A0Q_PE                     = 7   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAMR1A0Q_PE                     = 8   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAMR2A0Q_PE                     = 9   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAMR3A0Q_PE                     = 10  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSA0Q_PE                        = 11  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSA1Q_PE                        = 12  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBEA0Q_PE                        = 13  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBEA1Q_PE                        = 14  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSA2Q_PE                        = 15  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSA3Q_PE                        = 16  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBEA2Q_PE                        = 17  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBEA3Q_PE                        = 18  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBLFSRA0Q_PE                     = 19  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBACQ_PE                         = 20  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAGRAQ_PE                       = 21  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBRDS0Q_PE                       = 22  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBRDS1Q_PE                       = 23  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBDRSRQ_PE                       = 24  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBDRCRQ_PE                       = 25  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD0Q_PE                        = 26  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD1Q_PE                        = 27  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD2Q_PE                        = 28  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD3Q_PE                        = 29  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD4Q_PE                        = 30  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD5Q_PE                        = 31  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD6Q_PE                        = 32  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD7Q_PE                        = 33  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFDSPQ_PE                       = 34  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFDQ_PE                         = 35  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBPARMQ_PE                       = 36  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_RUNTIMECTRQ_PE                    = 37  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBRCRQ_PE                        = 38  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCB_CNTLSTATQ_PE                  = 39  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBCFGQ_PE                        = 40  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBMCATQ_PE                       = 41  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSEC0Q_PE                        = 42  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSEC1Q_PE                        = 43  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSTRQ_PE                         = 44  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC0Q_PE                     = 45  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC1Q_PE                     = 46  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC2Q_PE                     = 47  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC3Q_PE                     = 48  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC4Q_PE                     = 49  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC5Q_PE                     = 50  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC6Q_PE                     = 51  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC7Q_PE                     = 52  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC8Q_PE                     = 53  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSMODESQ_PE                      = 54  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSTATQ_PE                       = 55  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSMSECQ_PE                       = 56  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBNCER0Q_PE                       = 57  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBRCER0Q_PE                       = 58  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBMPER0Q_PE                       = 59  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBUER0Q_PE                        = 60  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBAUER0Q_PE                       = 61  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_DBG_BUS_CFGQ_PE                   = 62  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MASK1Q_PE                         = 63  ;

static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MASK0Q_PE                         = 0   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MBSEVR0Q_PE                       = 1   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_DBGCFG0Q_PE                       = 2   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_DBGCFG1Q_PE                       = 3   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_DBGCFG2Q_PE                       = 4   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_DBGCFG3Q_PE                       = 5   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0AQ_PE                      = 6   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0BQ_PE                      = 7   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0CQ_PE                      = 8   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0DQ_PE                      = 9   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0EQ_PE                      = 10  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1AQ_PE                      = 11  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1BQ_PE                      = 12  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1CQ_PE                      = 13  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1DQ_PE                      = 14  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1EQ_PE                      = 15  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2AQ_PE                      = 16  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2BQ_PE                      = 17  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2CQ_PE                      = 18  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2DQ_PE                      = 19  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2EQ_PE                      = 20  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3AQ_PE                      = 21  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3BQ_PE                      = 22  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3CQ_PE                      = 23  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3DQ_PE                      = 24  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3EQ_PE                      = 25  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR0Q_PE                        = 26  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR1Q_PE                        = 27  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR2Q_PE                        = 28  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR3Q_PE                        = 29  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR4Q_PE                        = 30  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR5Q_PE                        = 31  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR6Q_PE                        = 32  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR7Q_PE                        = 33  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MBXLT0Q_PE                        = 34  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MBXLT1Q_PE                        = 35  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MBXLT2Q_PE                        = 36  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_CCS_CNTLQ_PE                      = 37  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCB_CNTLQ_PE                      = 38  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCB_FIR_CCS                       = 39  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCB_FIR_MCBFSM                    = 40  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_CCS_ARRAY_UNCORRECTED_CE          = 41  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_CCS_ARRAY_UE                      = 42  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_CCS_ARRAY_SCOM_ECC                = 43  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_RESERVED_44_63                    = 44  ;
static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_RESERVED_44_63_LEN                = 20  ;

static const uint8_t EXPLR_MCBIST_ERR_MASK_LAT_FIR_PAR                         = 0   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK_LAT_FIR_ACTION0_PAR                 = 1   ;
static const uint8_t EXPLR_MCBIST_ERR_MASK_LAT_FIR_ACTION1_PAR                 = 2   ;

static const uint8_t EXPLR_MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP       = 0   ;
static const uint8_t EXPLR_MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN   = 38  ;
static const uint8_t EXPLR_MCBIST_MBAUER0Q_RESERVED_38_39                      = 38  ;
static const uint8_t EXPLR_MCBIST_MBAUER0Q_RESERVED_38_39_LEN                  = 2   ;

static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBECTLQ_PE                    = 0   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCS_STATQ_PE                  = 1   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCS_MODEQ_PE                  = 2   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_RCD_LRDIM_CNTL_WORD0_15Q_PE   = 3   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCSARRERRINJQ_PE              = 4   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCS_FIXED_DATA0Q_PE           = 5   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCS_FIXED_DATA1Q_PE           = 6   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAMR0A0Q_PE                 = 7   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAMR1A0Q_PE                 = 8   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAMR2A0Q_PE                 = 9   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAMR3A0Q_PE                 = 10  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSA0Q_PE                    = 11  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSA1Q_PE                    = 12  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBEA0Q_PE                    = 13  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBEA1Q_PE                    = 14  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSA2Q_PE                    = 15  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSA3Q_PE                    = 16  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBEA2Q_PE                    = 17  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBEA3Q_PE                    = 18  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBLFSRA0Q_PE                 = 19  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBACQ_PE                     = 20  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAGRAQ_PE                   = 21  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBRDS0Q_PE                   = 22  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBRDS1Q_PE                   = 23  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBDRSRQ_PE                   = 24  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBDRCRQ_PE                   = 25  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD0Q_PE                    = 26  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD1Q_PE                    = 27  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD2Q_PE                    = 28  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD3Q_PE                    = 29  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD4Q_PE                    = 30  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD5Q_PE                    = 31  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD6Q_PE                    = 32  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD7Q_PE                    = 33  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFDSPQ_PE                   = 34  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFDQ_PE                     = 35  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBPARMQ_PE                   = 36  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_RUNTIMECTRQ_PE                = 37  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBRCRQ_PE                    = 38  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCB_CNTLSTATQ_PE              = 39  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBCFGQ_PE                    = 40  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBMCATQ_PE                   = 41  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSEC0Q_PE                    = 42  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSEC1Q_PE                    = 43  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSTRQ_PE                     = 44  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC0Q_PE                 = 45  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC1Q_PE                 = 46  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC2Q_PE                 = 47  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC3Q_PE                 = 48  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC4Q_PE                 = 49  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC5Q_PE                 = 50  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC6Q_PE                 = 51  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC7Q_PE                 = 52  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC8Q_PE                 = 53  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSMODESQ_PE                  = 54  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSTATQ_PE                   = 55  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSMSECQ_PE                   = 56  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBNCER0Q_PE                   = 57  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBRCER0Q_PE                   = 58  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBMPER0Q_PE                   = 59  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBUER0Q_PE                    = 60  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBAUER0Q_PE                   = 61  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_DBG_BUS_CFGQ_PE               = 62  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_ERR_MASK1Q_PE                 = 63  ;

static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_ERR_MASK0Q_PE                 = 0   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MBSEVR0Q_PE                   = 1   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_DBGCFG0Q_PE                   = 2   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_DBGCFG1Q_PE                   = 3   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_DBGCFG2Q_PE                   = 4   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_DBGCFG3Q_PE                   = 5   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0AQ_PE                  = 6   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0BQ_PE                  = 7   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0CQ_PE                  = 8   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0DQ_PE                  = 9   ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0EQ_PE                  = 10  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1AQ_PE                  = 11  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1BQ_PE                  = 12  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1CQ_PE                  = 13  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1DQ_PE                  = 14  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1EQ_PE                  = 15  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2AQ_PE                  = 16  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2BQ_PE                  = 17  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2CQ_PE                  = 18  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2DQ_PE                  = 19  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2EQ_PE                  = 20  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3AQ_PE                  = 21  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3BQ_PE                  = 22  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3CQ_PE                  = 23  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3DQ_PE                  = 24  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3EQ_PE                  = 25  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR0Q_PE                    = 26  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR1Q_PE                    = 27  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR2Q_PE                    = 28  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR3Q_PE                    = 29  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR4Q_PE                    = 30  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR5Q_PE                    = 31  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR6Q_PE                    = 32  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR7Q_PE                    = 33  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MBXLT0Q_PE                    = 34  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MBXLT1Q_PE                    = 35  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MBXLT2Q_PE                    = 36  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_CCS_CNTLQ_PE                  = 37  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCB_CNTLQ_PE                  = 38  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCB_FIR_CCS_ERR               = 39  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCB_FIR_MCBFSM_ERR            = 40  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_CCS_ARRAY_UNCORRECTED_CE_ERR  = 41  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_CCS_ARRAY_UE_ERR              = 42  ;
static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_CCS_ARRAY_SCOM_ECC_ERR        = 43  ;

static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_CE_INJ                    = 0   ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_CHIP_KILL_INJ             = 1   ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_UE_INJ                    = 2   ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_SUE_INJ                   = 3   ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL               = 4   ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL_LEN           = 7   ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_RESERVE_11                           = 11  ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_SCOM_CMD_REG_INJ_MODE                = 12  ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_SCOM_CMD_REG_INJ                     = 13  ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_MCBIST_FSM_INJ_MODE                  = 14  ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_MCBIST_FSM_INJ_REG                   = 15  ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_CCS_FSM_INJ_MODE                     = 16  ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_CCS_FSM_INJ_REG                      = 17  ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_RESERVED_18_31                       = 18  ;
static const uint8_t EXPLR_MCBIST_MBECTLQ_RESERVED_18_31_LEN                   = 14  ;

static const uint8_t EXPLR_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP       = 0   ;
static const uint8_t EXPLR_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN   = 38  ;
static const uint8_t EXPLR_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE          = 38  ;
static const uint8_t EXPLR_MCBIST_MBMPER0Q_RESERVED_39                         = 39  ;

static const uint8_t EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP       = 0   ;
static const uint8_t EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN   = 38  ;
static const uint8_t EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE          = 38  ;
static const uint8_t EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE          = 39  ;

static const uint8_t EXPLR_MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP       = 0   ;
static const uint8_t EXPLR_MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN   = 38  ;
static const uint8_t EXPLR_MCBIST_MBRCER0Q_RESERVED_38_39                      = 38  ;
static const uint8_t EXPLR_MCBIST_MBRCER0Q_RESERVED_38_39_LEN                  = 2   ;

static const uint8_t EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT                = 0   ;
static const uint8_t EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT_LEN            = 12  ;
static const uint8_t EXPLR_MCBIST_MBSEC0Q_SOFT_CE_COUNT                        = 12  ;
static const uint8_t EXPLR_MCBIST_MBSEC0Q_SOFT_CE_COUNT_LEN                    = 12  ;
static const uint8_t EXPLR_MCBIST_MBSEC0Q_HARD_CE_COUNT                        = 24  ;
static const uint8_t EXPLR_MCBIST_MBSEC0Q_HARD_CE_COUNT_LEN                    = 12  ;
static const uint8_t EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT               = 36  ;
static const uint8_t EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT_LEN           = 12  ;
static const uint8_t EXPLR_MCBIST_MBSEC0Q_SOFT_MCE_COUNT                       = 48  ;
static const uint8_t EXPLR_MCBIST_MBSEC0Q_SOFT_MCE_COUNT_LEN                   = 12  ;

static const uint8_t EXPLR_MCBIST_MBSEC1Q_HARD_MCE_COUNT                       = 0   ;
static const uint8_t EXPLR_MCBIST_MBSEC1Q_HARD_MCE_COUNT_LEN                   = 12  ;
static const uint8_t EXPLR_MCBIST_MBSEC1Q_ICE_COUNT                            = 12  ;
static const uint8_t EXPLR_MCBIST_MBSEC1Q_ICE_COUNT_LEN                        = 12  ;
static const uint8_t EXPLR_MCBIST_MBSEC1Q_UE_COUNT                             = 24  ;
static const uint8_t EXPLR_MCBIST_MBSEC1Q_UE_COUNT_LEN                         = 12  ;
static const uint8_t EXPLR_MCBIST_MBSEC1Q_AUE                                  = 36  ;
static const uint8_t EXPLR_MCBIST_MBSEC1Q_AUE_LEN                              = 12  ;
static const uint8_t EXPLR_MCBIST_MBSEC1Q_RCE_COUNT                            = 48  ;
static const uint8_t EXPLR_MCBIST_MBSEC1Q_RCE_COUNT_LEN                        = 12  ;

static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD    = 0   ;
static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN = 8   ;
static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD = 8   ;
static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 8   ;
static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD    = 16  ;
static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN = 8   ;
static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD = 24  ;
static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 8   ;
static const uint8_t EXPLR_MCBIST_MBSEVR0Q_RESERVED_32_63                      = 32  ;
static const uint8_t EXPLR_MCBIST_MBSEVR0Q_RESERVED_32_63_LEN                  = 32  ;

static const uint8_t EXPLR_MCBIST_MBSMODESQ_CFG_DDR4E_BLIND_STEER_MODE         = 0   ;
static const uint8_t EXPLR_MCBIST_MBSMODESQ_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS = 1   ;
static const uint8_t EXPLR_MCBIST_MBSMODESQ_RESERVE_2_15                       = 2   ;
static const uint8_t EXPLR_MCBIST_MBSMODESQ_RESERVE_2_15_LEN                   = 14  ;

static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT                   = 0   ;
static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT_LEN               = 8   ;
static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT                   = 8   ;
static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT_LEN               = 8   ;
static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT                   = 16  ;
static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT_LEN               = 8   ;
static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT                   = 24  ;
static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT_LEN               = 8   ;

static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00           = 0   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01           = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02           = 16  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03           = 24  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04           = 32  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05           = 40  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06           = 48  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07           = 56  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07_LEN       = 8   ;

static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08           = 0   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09           = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10           = 16  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11           = 24  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12           = 32  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13           = 40  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14           = 48  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15           = 56  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15_LEN       = 8   ;

static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16           = 0   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17           = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18           = 16  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19           = 24  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20           = 32  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21           = 40  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22           = 48  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23           = 56  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23_LEN       = 8   ;

static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24           = 0   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25           = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26           = 16  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27           = 24  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28           = 32  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29           = 40  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30           = 48  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31           = 56  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31_LEN       = 8   ;

static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32           = 0   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33           = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34           = 16  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35           = 24  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36           = 32  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37           = 40  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38           = 48  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39           = 56  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39_LEN       = 8   ;

static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40           = 0   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41           = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42           = 16  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43           = 24  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44           = 32  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45           = 40  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46           = 48  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47           = 56  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47_LEN       = 8   ;

static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48           = 0   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49           = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50           = 16  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51           = 24  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52           = 32  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53           = 40  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54           = 48  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55           = 56  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55_LEN       = 8   ;

static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56           = 0   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57           = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58           = 16  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59           = 24  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60           = 32  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61           = 40  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62           = 48  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63           = 56  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63_LEN       = 8   ;

static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64           = 0   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65           = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66           = 16  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67           = 24  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68           = 32  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69           = 40  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70           = 48  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70_LEN       = 8   ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71           = 56  ;
static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71_LEN       = 8   ;

static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT                = 0   ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT               = 4   ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT_LEN           = 4   ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD               = 8   ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD_LEN           = 4   ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE                    = 12  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE_LEN                = 4   ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE                    = 16  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE_LEN                = 4   ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT                = 20  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT_LEN            = 4   ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT               = 24  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT_LEN           = 4   ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD               = 28  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN           = 4   ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_SCE                      = 32  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_RESERVED_33                           = 33  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_MPE                      = 34  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_UE                       = 35  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_SUE                      = 36  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_AUE                      = 37  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_RCD                      = 38  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_RESERVE_39_52                         = 39  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_RESERVE_39_52_LEN                     = 14  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE               = 53  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE_LEN           = 2   ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE      = 55  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE     = 56  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE      = 57  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_MCB_ERROR                   = 58  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_MCB_LOG_FULL                = 59  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_MAINT_RCE_WITH_CE                 = 60  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE      = 61  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE     = 62  ;
static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE      = 63  ;

static const uint8_t EXPLR_MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP         = 0   ;
static const uint8_t EXPLR_MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN     = 38  ;
static const uint8_t EXPLR_MCBIST_MBUER0Q_RESERVED_38_39                       = 38  ;
static const uint8_t EXPLR_MCBIST_MBUER0Q_RESERVED_38_39_LEN                   = 2   ;

static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_VALID                          = 0   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_D_VALUE                        = 1   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_12GB_ENABLE                          = 2   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_3_4                         = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_3_4_LEN                     = 2   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_M0_VALID                       = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_M1_VALID                       = 6   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_7_8                         = 7   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_7_8_LEN                     = 2   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_S0_VALID                       = 9   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_S1_VALID                       = 10  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_S2_VALID                       = 11  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_B2_VALID                       = 12  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_ROW15_VALID                    = 13  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_ROW16_VALID                    = 14  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_ROW17_VALID                    = 15  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_VALID                          = 16  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_D_VALUE                        = 17  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_18_20                       = 18  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_18_20_LEN                   = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_M0_VALID                       = 21  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_M1_VALID                       = 22  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_23_24                       = 23  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_23_24_LEN                   = 2   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_S0_VALID                       = 25  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_S1_VALID                       = 26  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_S2_VALID                       = 27  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_B2_VALID                       = 28  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_ROW15_VALID                    = 29  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_ROW16_VALID                    = 30  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_ROW17_VALID                    = 31  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_ENAB_ROW_ADDR_HASH                   = 32  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_D_BIT_MAP                            = 33  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_D_BIT_MAP_LEN                        = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_M0_BIT_MAP                           = 38  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_M0_BIT_MAP_LEN                       = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_M1_BIT_MAP                           = 43  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_M1_BIT_MAP_LEN                       = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_48                          = 48  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_R17_BIT_MAP                          = 49  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_R17_BIT_MAP_LEN                      = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_R16_BIT_MAP                          = 54  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_R16_BIT_MAP_LEN                      = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_R15_BIT_MAP                          = 59  ;
static const uint8_t EXPLR_MCBIST_MBXLT0Q_R15_BIT_MAP_LEN                      = 5   ;

static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_0_2                          = 0   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_0_2_LEN                      = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_S0_BIT_MAP                            = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_S0_BIT_MAP_LEN                        = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_8_10                         = 8   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_8_10_LEN                     = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_S1_BIT_MAP                            = 11  ;
static const uint8_t EXPLR_MCBIST_MBXLT1_S1_BIT_MAP_LEN                        = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_16_18                        = 16  ;
static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_16_18_LEN                    = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_S2_BIT_MAP                            = 19  ;
static const uint8_t EXPLR_MCBIST_MBXLT1_S2_BIT_MAP_LEN                        = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_24_29                        = 24  ;
static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_24_29_LEN                    = 6   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_COL3_BIT_MAP                          = 30  ;
static const uint8_t EXPLR_MCBIST_MBXLT1_COL3_BIT_MAP_LEN                      = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_COL4_BIT_MAP                          = 35  ;
static const uint8_t EXPLR_MCBIST_MBXLT1_COL4_BIT_MAP_LEN                      = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_40_42                        = 40  ;
static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_40_42_LEN                    = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_COL5_BIT_MAP                          = 43  ;
static const uint8_t EXPLR_MCBIST_MBXLT1_COL5_BIT_MAP_LEN                      = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_48_50                        = 48  ;
static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_48_50_LEN                    = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_COL6_BIT_MAP                          = 51  ;
static const uint8_t EXPLR_MCBIST_MBXLT1_COL6_BIT_MAP_LEN                      = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_56_58                        = 56  ;
static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_56_58_LEN                    = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT1_COL7_BIT_MAP                          = 59  ;
static const uint8_t EXPLR_MCBIST_MBXLT1_COL7_BIT_MAP_LEN                      = 5   ;

static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_0_2                          = 0   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_0_2_LEN                      = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_COL8_BIT_MAP                          = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_COL8_BIT_MAP_LEN                      = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_8_10                         = 8   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_8_10_LEN                     = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_COL9_BIT_MAP                          = 11  ;
static const uint8_t EXPLR_MCBIST_MBXLT2_COL9_BIT_MAP_LEN                      = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_16_18                        = 16  ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_16_18_LEN                    = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_BANK0_BIT_MAP                         = 19  ;
static const uint8_t EXPLR_MCBIST_MBXLT2_BANK0_BIT_MAP_LEN                     = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_24_26                        = 24  ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_24_26_LEN                    = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_BANK1_BIT_MAP                         = 27  ;
static const uint8_t EXPLR_MCBIST_MBXLT2_BANK1_BIT_MAP_LEN                     = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_32_34                        = 32  ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_32_34_LEN                    = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_BANK2_BIT_MAP                         = 35  ;
static const uint8_t EXPLR_MCBIST_MBXLT2_BANK2_BIT_MAP_LEN                     = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_40_42                        = 40  ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_40_42_LEN                    = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_BANK_GROUP0_BIT_MAP                   = 43  ;
static const uint8_t EXPLR_MCBIST_MBXLT2_BANK_GROUP0_BIT_MAP_LEN               = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_48_50                        = 48  ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_48_50_LEN                    = 3   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_BANK_GROUP1_BIT_MAP                   = 51  ;
static const uint8_t EXPLR_MCBIST_MBXLT2_BANK_GROUP1_BIT_MAP_LEN               = 5   ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_56_63                        = 56  ;
static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_56_63_LEN                    = 8   ;

static const uint8_t EXPLR_MCBIST_MCBACQ_CFG_ADDRESS_COUNTER                   = 0   ;
static const uint8_t EXPLR_MCBIST_MCBACQ_CFG_ADDRESS_COUNTER_LEN               = 38  ;

static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH                     = 0   ;
static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE               = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE_LEN           = 4   ;
static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_MAINT_ADDR_MODE_EN              = 10  ;
static const uint8_t EXPLR_MCBIST_MCBAGRAQ_RESERVED_11                         = 11  ;
static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_MAINT_DETECT_SRANK_BOUNDARIES   = 12  ;
static const uint8_t EXPLR_MCBIST_MCBAGRAQ_RESERVED_13_31                      = 13  ;
static const uint8_t EXPLR_MCBIST_MCBAGRAQ_RESERVED_13_31_LEN                  = 19  ;

static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT              = 0   ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT_LEN          = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0                   = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0_LEN               = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1                   = 12  ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1_LEN               = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_RESERVED_18_23                    = 18  ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_RESERVED_18_23_LEN                = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0                   = 24  ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0_LEN               = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1                   = 30  ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1_LEN               = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2                   = 36  ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2_LEN               = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2                    = 42  ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2_LEN                = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1                    = 48  ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1_LEN                = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0                    = 54  ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0_LEN                = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_RESERVED_60_63                    = 60  ;
static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_RESERVED_60_63_LEN                = 4   ;

static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1              = 0   ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1_LEN          = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0              = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0_LEN          = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17                    = 12  ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17_LEN                = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16                    = 18  ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16_LEN                = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15                    = 24  ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15_LEN                = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14                    = 30  ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14_LEN                = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13                    = 36  ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13_LEN                = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12                    = 42  ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12_LEN                = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11                    = 48  ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11_LEN                = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10                    = 54  ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10_LEN                = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_RESERVED_60_63                    = 60  ;
static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_RESERVED_60_63_LEN                = 4   ;

static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9                     = 0   ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8                     = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7                     = 12  ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6                     = 18  ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5                     = 24  ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4                     = 30  ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3                     = 36  ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2                     = 42  ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1                     = 48  ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0                     = 54  ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_RESERVED_60_63                    = 60  ;
static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_RESERVED_60_63_LEN                = 4   ;

static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9                     = 0   ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8                     = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7                     = 12  ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6                     = 18  ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5                     = 24  ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4                     = 30  ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3                     = 36  ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2                     = 42  ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2_LEN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_RESERVED_48_63                    = 48  ;
static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_RESERVED_48_63_LEN                = 16  ;

static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_0_7                         = 0   ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_0_7_LEN                     = 8   ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE                 = 8   ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE_LEN             = 2   ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESET_KEEPER                         = 10  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS     = 11  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_CCS_RETRY_DIS                    = 12  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_13_33                       = 13  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_13_33_LEN                   = 21  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK    = 34  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_RESET_CNTS_START_OF_RANK         = 35  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_LOG_COUNTS_IN_TRACE              = 36  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_SKIP_INVALID_ADDR_DIMM_DIS           = 37  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_EN              = 38  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL    = 39  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = 2   ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_RAND_ADDR_ALL_ADDR_MODE_EN           = 41  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME             = 42  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME_LEN         = 14  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_MCB_LEN64                        = 56  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE              = 57  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE_LEN          = 2   ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST   = 59  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR    = 60  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST = 61  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_62_63                       = 62  ;
static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_62_63_LEN                   = 2   ;

static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT                        = 0   ;
static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT_LEN                    = 4   ;
static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED                   = 4   ;
static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN               = 16  ;
static const uint8_t EXPLR_MCBIST_MCBDRCRQ_RESERVED_20                         = 20  ;
static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE                  = 21  ;
static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE_LEN              = 2   ;
static const uint8_t EXPLR_MCBIST_MCBDRCRQ_RESERVED_23_63                      = 23  ;
static const uint8_t EXPLR_MCBIST_MCBDRCRQ_RESERVED_23_63_LEN                  = 41  ;

static const uint8_t EXPLR_MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED                   = 0   ;
static const uint8_t EXPLR_MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED_LEN               = 64  ;

static const uint8_t EXPLR_MCBIST_MCBEA0Q_CFG_END_ADDR_0                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBEA0Q_CFG_END_ADDR_0_LEN                   = 38  ;

static const uint8_t EXPLR_MCBIST_MCBEA1Q_CFG_END_ADDR_1                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBEA1Q_CFG_END_ADDR_1_LEN                   = 38  ;

static const uint8_t EXPLR_MCBIST_MCBEA2Q_CFG_END_ADDR_2                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBEA2Q_CFG_END_ADDR_2_LEN                   = 38  ;

static const uint8_t EXPLR_MCBIST_MCBEA3Q_CFG_END_ADDR_3                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBEA3Q_CFG_END_ADDR_3_LEN                   = 38  ;

static const uint8_t EXPLR_MCBIST_MCBFD0Q_CFG_FIXED_SEED                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBFD0Q_CFG_FIXED_SEED_LEN                   = 64  ;

static const uint8_t EXPLR_MCBIST_MCBFD1Q_CFG_FIXED_SEED                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBFD1Q_CFG_FIXED_SEED_LEN                   = 64  ;

static const uint8_t EXPLR_MCBIST_MCBFD2Q_CFG_FIXED_SEED                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBFD2Q_CFG_FIXED_SEED_LEN                   = 64  ;

static const uint8_t EXPLR_MCBIST_MCBFD3Q_CFG_FIXED_SEED                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBFD3Q_CFG_FIXED_SEED_LEN                   = 64  ;

static const uint8_t EXPLR_MCBIST_MCBFD4Q_CFG_FIXED_SEED                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBFD4Q_CFG_FIXED_SEED_LEN                   = 64  ;

static const uint8_t EXPLR_MCBIST_MCBFD5Q_CFG_FIXED_SEED                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBFD5Q_CFG_FIXED_SEED_LEN                   = 64  ;

static const uint8_t EXPLR_MCBIST_MCBFD6Q_CFG_FIXED_SEED                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBFD6Q_CFG_FIXED_SEED_LEN                   = 64  ;

static const uint8_t EXPLR_MCBIST_MCBFD7Q_CFG_FIXED_SEED                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBFD7Q_CFG_FIXED_SEED_LEN                   = 64  ;

static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED1                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED1_LEN                   = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED2                       = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED2_LEN                   = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED3                       = 16  ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED3_LEN                   = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED4                       = 24  ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED4_LEN                   = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED5                       = 32  ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED5_LEN                   = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED6                       = 40  ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED6_LEN                   = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED7                       = 48  ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED7_LEN                   = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED8                       = 56  ;
static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED8_LEN                   = 8   ;

static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED1                     = 0   ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED1_LEN                 = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED2                     = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED2_LEN                 = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED3                     = 16  ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED3_LEN                 = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED4                     = 24  ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED4_LEN                 = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED5                     = 32  ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED5_LEN                 = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED6                     = 40  ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED6_LEN                 = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED7                     = 48  ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED7_LEN                 = 8   ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED8                     = 56  ;
static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED8_LEN                 = 8   ;

static const uint8_t EXPLR_MCBIST_MCBISTFIRACT0_FIR_ACTION0                    = 0   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRACT0_FIR_ACTION0_LEN                = 20  ;

static const uint8_t EXPLR_MCBIST_MCBISTFIRACT1_FIR_ACTION1                    = 0   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRACT1_FIR_ACTION1_LEN                = 20  ;

static const uint8_t EXPLR_MCBIST_MCBISTFIRMASK_FIR_MASK                       = 0   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRMASK_FIR_MASK_LEN                   = 20  ;

static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INVALID_MAINT_ADDRESS             = 0   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_COMMAND_ADDRESS_TIMEOUT           = 1   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INTERNAL_FSM_ERROR                = 2   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_CCS_ARRAY_UNCORRECT_CE_OR_UE      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_MCBIST_DATA_ERROR                 = 4   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_HARD_NCE_ETE_ATTN                 = 5   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_SOFT_NCE_ETE_ATTN                 = 6   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INT_NCE_ETE_ATTN                  = 7   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_RCE_ETE_ATTN                      = 8   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_ICE_ETE_ATTN                      = 9   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE           = 10  ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_MCBIST_CCS_SUBTEST_DONE           = 11  ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN                    = 12  ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_SCOM_RECOVERABLE_REG_PE           = 13  ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_SCOM_FATAL_REG_PE                 = 14  ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_WAT_DEBUG_REG_PE                  = 15  ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_RESERVED_16                       = 16  ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_RESERVED_17                       = 17  ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR               = 18  ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR_CLONE         = 19  ;

static const uint8_t EXPLR_MCBIST_MCBISTFIRWOF_FIR_WOF                         = 0   ;
static const uint8_t EXPLR_MCBIST_MCBISTFIRWOF_FIR_WOF_LEN                     = 20  ;

static const uint8_t EXPLR_MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0                  = 0   ;
static const uint8_t EXPLR_MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0_LEN              = 38  ;
static const uint8_t EXPLR_MCBIST_MCBLFSRA0Q_RESERVED_38_63                    = 38  ;
static const uint8_t EXPLR_MCBIST_MCBLFSRA0Q_RESERVED_38_63_LEN                = 26  ;

static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP               = 0   ;
static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP_LEN           = 38  ;
static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP               = 38  ;
static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP_LEN           = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_DIMM_TRAP               = 40  ;

static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE            = 0   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD      = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD      = 5   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_3RD_CMD      = 6   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_REV_MODE      = 7   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_RAND_MODE     = 8   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE          = 9   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ECC_MODE           = 12  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DONE               = 13  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL           = 14  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE            = 16  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_1ST_CMD      = 20  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_2ND_CMD      = 21  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_3RD_CMD      = 22  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_REV_MODE      = 23  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_RAND_MODE     = 24  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE          = 25  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ECC_MODE           = 28  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DONE               = 29  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL           = 30  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE            = 32  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_1ST_CMD      = 36  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_2ND_CMD      = 37  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_3RD_CMD      = 38  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_REV_MODE      = 39  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_RAND_MODE     = 40  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE          = 41  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ECC_MODE           = 44  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DONE               = 45  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL           = 46  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE            = 48  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_1ST_CMD      = 52  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_2ND_CMD      = 53  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_3RD_CMD      = 54  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_REV_MODE      = 55  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_RAND_MODE     = 56  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE          = 57  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ECC_MODE           = 60  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DONE               = 61  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL           = 62  ;
static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL_LEN       = 2   ;

static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE            = 0   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_1ST_CMD      = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_2ND_CMD      = 5   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_3RD_CMD      = 6   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_REV_MODE      = 7   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_RAND_MODE     = 8   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE          = 9   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ECC_MODE           = 12  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DONE               = 13  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL           = 14  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE            = 16  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_1ST_CMD      = 20  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_2ND_CMD      = 21  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_3RD_CMD      = 22  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_REV_MODE      = 23  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_RAND_MODE     = 24  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE          = 25  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ECC_MODE           = 28  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DONE               = 29  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL           = 30  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE            = 32  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_1ST_CMD      = 36  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_2ND_CMD      = 37  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_3RD_CMD      = 38  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_REV_MODE      = 39  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_RAND_MODE     = 40  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE          = 41  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ECC_MODE           = 44  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DONE               = 45  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL           = 46  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE            = 48  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_1ST_CMD      = 52  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_2ND_CMD      = 53  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_3RD_CMD      = 54  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_REV_MODE      = 55  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_RAND_MODE     = 56  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE          = 57  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ECC_MODE           = 60  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DONE               = 61  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL           = 62  ;
static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL_LEN       = 2   ;

static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE            = 0   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_1ST_CMD      = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_2ND_CMD      = 5   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_3RD_CMD      = 6   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_REV_MODE      = 7   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_RAND_MODE     = 8   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE          = 9   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ECC_MODE           = 12  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DONE               = 13  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL           = 14  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE            = 16  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_1ST_CMD      = 20  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_2ND_CMD      = 21  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_3RD_CMD      = 22  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_REV_MODE      = 23  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_RAND_MODE     = 24  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE          = 25  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ECC_MODE           = 28  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DONE               = 29  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL           = 30  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE            = 32  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_1ST_CMD      = 36  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_2ND_CMD      = 37  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_3RD_CMD      = 38  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_REV_MODE      = 39  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_RAND_MODE     = 40  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE          = 41  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ECC_MODE           = 44  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DONE               = 45  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL           = 46  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE            = 48  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_1ST_CMD      = 52  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_2ND_CMD      = 53  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_3RD_CMD      = 54  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_REV_MODE      = 55  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_RAND_MODE     = 56  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE          = 57  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ECC_MODE           = 60  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DONE               = 61  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL           = 62  ;
static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL_LEN       = 2   ;

static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE            = 0   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_1ST_CMD      = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_2ND_CMD      = 5   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_3RD_CMD      = 6   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_REV_MODE      = 7   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_RAND_MODE     = 8   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE          = 9   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ECC_MODE           = 12  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DONE               = 13  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL           = 14  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE            = 16  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_1ST_CMD      = 20  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_2ND_CMD      = 21  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_3RD_CMD      = 22  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_REV_MODE      = 23  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_RAND_MODE     = 24  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE          = 25  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ECC_MODE           = 28  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DONE               = 29  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL           = 30  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE            = 32  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_1ST_CMD      = 36  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_2ND_CMD      = 37  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_3RD_CMD      = 38  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_REV_MODE      = 39  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_RAND_MODE     = 40  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE          = 41  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ECC_MODE           = 44  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DONE               = 45  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL           = 46  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE            = 48  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_1ST_CMD      = 52  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_2ND_CMD      = 53  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_3RD_CMD      = 54  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_REV_MODE      = 55  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_RAND_MODE     = 56  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE          = 57  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ECC_MODE           = 60  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DONE               = 61  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL           = 62  ;
static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL_LEN       = 2   ;

static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE            = 0   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_1ST_CMD      = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_2ND_CMD      = 5   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_3RD_CMD      = 6   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_REV_MODE      = 7   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_RAND_MODE     = 8   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE          = 9   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ECC_MODE           = 12  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DONE               = 13  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL           = 14  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE            = 16  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_1ST_CMD      = 20  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_2ND_CMD      = 21  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_3RD_CMD      = 22  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_REV_MODE      = 23  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_RAND_MODE     = 24  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE          = 25  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ECC_MODE           = 28  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DONE               = 29  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL           = 30  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE            = 32  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_1ST_CMD      = 36  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_2ND_CMD      = 37  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_3RD_CMD      = 38  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_REV_MODE      = 39  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_RAND_MODE     = 40  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE          = 41  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ECC_MODE           = 44  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DONE               = 45  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL           = 46  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE            = 48  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_1ST_CMD      = 52  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_2ND_CMD      = 53  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_3RD_CMD      = 54  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_REV_MODE      = 55  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_RAND_MODE     = 56  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE          = 57  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ECC_MODE           = 60  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DONE               = 61  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL           = 62  ;
static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL_LEN       = 2   ;

static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE            = 0   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_1ST_CMD      = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_2ND_CMD      = 5   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_3RD_CMD      = 6   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_REV_MODE      = 7   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_RAND_MODE     = 8   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE          = 9   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ECC_MODE           = 12  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DONE               = 13  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL           = 14  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE            = 16  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_1ST_CMD      = 20  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_2ND_CMD      = 21  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_3RD_CMD      = 22  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_REV_MODE      = 23  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_RAND_MODE     = 24  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE          = 25  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ECC_MODE           = 28  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DONE               = 29  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL           = 30  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE            = 32  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_1ST_CMD      = 36  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_2ND_CMD      = 37  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_3RD_CMD      = 38  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_REV_MODE      = 39  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_RAND_MODE     = 40  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE          = 41  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ECC_MODE           = 44  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DONE               = 45  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL           = 46  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE            = 48  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_1ST_CMD      = 52  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_2ND_CMD      = 53  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_3RD_CMD      = 54  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_REV_MODE      = 55  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_RAND_MODE     = 56  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE          = 57  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ECC_MODE           = 60  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DONE               = 61  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL           = 62  ;
static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL_LEN       = 2   ;

static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE            = 0   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_1ST_CMD      = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_2ND_CMD      = 5   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_3RD_CMD      = 6   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_REV_MODE      = 7   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_RAND_MODE     = 8   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE          = 9   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ECC_MODE           = 12  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DONE               = 13  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL           = 14  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE            = 16  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_1ST_CMD      = 20  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_2ND_CMD      = 21  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_3RD_CMD      = 22  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_REV_MODE      = 23  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_RAND_MODE     = 24  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE          = 25  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ECC_MODE           = 28  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DONE               = 29  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL           = 30  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE            = 32  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_1ST_CMD      = 36  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_2ND_CMD      = 37  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_3RD_CMD      = 38  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_REV_MODE      = 39  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_RAND_MODE     = 40  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE          = 41  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ECC_MODE           = 44  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DONE               = 45  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL           = 46  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE            = 48  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_1ST_CMD      = 52  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_2ND_CMD      = 53  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_3RD_CMD      = 54  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_REV_MODE      = 55  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_RAND_MODE     = 56  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE          = 57  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ECC_MODE           = 60  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DONE               = 61  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL           = 62  ;
static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL_LEN       = 2   ;

static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE            = 0   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_1ST_CMD      = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_2ND_CMD      = 5   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_3RD_CMD      = 6   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_REV_MODE      = 7   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_RAND_MODE     = 8   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE          = 9   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ECC_MODE           = 12  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DONE               = 13  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL           = 14  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE            = 16  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_1ST_CMD      = 20  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_2ND_CMD      = 21  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_3RD_CMD      = 22  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_REV_MODE      = 23  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_RAND_MODE     = 24  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE          = 25  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ECC_MODE           = 28  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DONE               = 29  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL           = 30  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE            = 32  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_1ST_CMD      = 36  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_2ND_CMD      = 37  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_3RD_CMD      = 38  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_REV_MODE      = 39  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_RAND_MODE     = 40  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE          = 41  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ECC_MODE           = 44  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DONE               = 45  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL           = 46  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL_LEN       = 2   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE            = 48  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE_LEN        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_1ST_CMD      = 52  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_2ND_CMD      = 53  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_3RD_CMD      = 54  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_REV_MODE      = 55  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_RAND_MODE     = 56  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE          = 57  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE_LEN      = 3   ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ECC_MODE           = 60  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DONE               = 61  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL           = 62  ;
static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL_LEN       = 2   ;

static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP                     = 0   ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_LEN                 = 12  ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE                = 12  ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER         = 13  ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER_LEN     = 12  ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE_BLIND_STEER    = 25  ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_RESERVED_26_49                      = 26  ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_RESERVED_26_49_LEN                  = 24  ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_RANDCMD_WGT                     = 50  ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_RANDCMD_WGT_LEN                 = 3   ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_RESERVED_53_59                      = 53  ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_RESERVED_53_59_LEN                  = 7   ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_EN_RANDCMD_GAP                  = 60  ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_RANDGAP_WGT                     = 61  ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_RANDGAP_WGT_LEN                 = 2   ;
static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_BC4_EN                          = 63  ;

static const uint8_t EXPLR_MCBIST_MCBRCRQ_RESERVED_0_31                        = 0   ;
static const uint8_t EXPLR_MCBIST_MCBRCRQ_RESERVED_0_31_LEN                    = 32  ;
static const uint8_t EXPLR_MCBIST_MCBRCRQ_CFG_RUNTIME_MCBALL                   = 32  ;
static const uint8_t EXPLR_MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST                  = 33  ;
static const uint8_t EXPLR_MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST_LEN              = 5   ;
static const uint8_t EXPLR_MCBIST_MCBRCRQ_CFG_RUNTIME_OVERHEAD                 = 38  ;
static const uint8_t EXPLR_MCBIST_MCBRCRQ_RESERVED_39                          = 39  ;

static const uint8_t EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0                     = 0   ;
static const uint8_t EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0_LEN                 = 24  ;
static const uint8_t EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1                     = 24  ;
static const uint8_t EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1_LEN                 = 24  ;

static const uint8_t EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2                     = 0   ;
static const uint8_t EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2_LEN                 = 24  ;
static const uint8_t EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING              = 24  ;
static const uint8_t EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING_LEN          = 40  ;

static const uint8_t EXPLR_MCBIST_MCBSA0Q_CFG_START_ADDR_0                     = 0   ;
static const uint8_t EXPLR_MCBIST_MCBSA0Q_CFG_START_ADDR_0_LEN                 = 38  ;

static const uint8_t EXPLR_MCBIST_MCBSA1Q_CFG_START_ADDR_1                     = 0   ;
static const uint8_t EXPLR_MCBIST_MCBSA1Q_CFG_START_ADDR_1_LEN                 = 38  ;

static const uint8_t EXPLR_MCBIST_MCBSA2Q_CFG_START_ADDR_2                     = 0   ;
static const uint8_t EXPLR_MCBIST_MCBSA2Q_CFG_START_ADDR_2_LEN                 = 38  ;

static const uint8_t EXPLR_MCBIST_MCBSA3Q_CFG_START_ADDR_3                     = 0   ;
static const uint8_t EXPLR_MCBIST_MCBSA3Q_CFG_START_ADDR_3_LEN                 = 38  ;

static const uint8_t EXPLR_MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR = 0   ;
static const uint8_t EXPLR_MCBIST_MCBSTATQ_RESERVED_1_3                        = 1   ;
static const uint8_t EXPLR_MCBIST_MCBSTATQ_RESERVED_1_3_LEN                    = 3   ;
static const uint8_t EXPLR_MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR        = 4   ;
static const uint8_t EXPLR_MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR_LEN    = 5   ;
static const uint8_t EXPLR_MCBIST_MCBSTATQ_RESERVED_9_15                       = 9   ;
static const uint8_t EXPLR_MCBIST_MCBSTATQ_RESERVED_9_15_LEN                   = 7   ;

static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_START                              = 0   ;
static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_STOP                               = 1   ;
static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESERVED_2_5                       = 2   ;
static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESERVED_2_5_LEN                   = 4   ;
static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESET_TRAP_CNFG                    = 6   ;
static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESET_ERROR_LOGS                   = 7   ;
static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESUME_FROM_PAUSE                  = 8   ;

static const uint8_t EXPLR_MCBIST_MCB_CNTLSTATQ_IP                             = 0   ;
static const uint8_t EXPLR_MCBIST_MCB_CNTLSTATQ_DONE                           = 1   ;
static const uint8_t EXPLR_MCBIST_MCB_CNTLSTATQ_FAIL                           = 2   ;

static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM              = 0   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_LEN          = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1        = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1_LEN    = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2        = 8   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2_LEN    = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3        = 12  ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3_LEN    = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4        = 16  ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4_LEN    = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5        = 20  ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5_LEN    = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6        = 24  ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6_LEN    = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7        = 28  ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7_LEN    = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8        = 32  ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8_LEN    = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9        = 36  ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9_LEN    = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10       = 40  ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10_LEN   = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11       = 44  ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11_LEN   = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12       = 48  ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12_LEN   = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13       = 52  ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13_LEN   = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14       = 56  ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14_LEN   = 4   ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15       = 60  ;
static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15_LEN   = 4   ;

static const uint8_t EXPLR_MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR                  = 0   ;
static const uint8_t EXPLR_MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR_LEN              = 37  ;

static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ASEL                 = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ASEL_LEN             = 8   ;
static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_BSEL                 = 8   ;
static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_BSEL_LEN             = 8   ;
static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ABSEL                = 16  ;
static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ABSEL_LEN            = 8   ;
static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ETSEL                = 24  ;
static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ETSEL_LEN            = 8   ;
static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_CMSEL                = 32  ;
static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_CMSEL_LEN            = 8   ;
static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_CYSEL                = 40  ;
static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_CYSEL_LEN            = 8   ;

static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_WAT_MSKA                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_WAT_MSKA_LEN                   = 44  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_WAT_ENABLE                     = 44  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_INT_ARM_MODE                   = 45  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_EXT_ARM_MODE                   = 46  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_TIMER_STATE_MODE               = 47  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_SET_LEVEL_ON_PULSE             = 48  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_RESET_LEVEL_ON_PULSE           = 49  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_ENABLE_EXT_RESET_LEVEL         = 50  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_STATE_SET_DOM                  = 51  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_STATE_FOLLOW_LEVEL             = 52  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_NOT_PATA_MODE                  = 53  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_NOT_PATB_MODE                  = 54  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_NOT_PATA_MODE2                 = 55  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_NOT_PATB_MODE2                 = 56  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_SLIDE_TRIG                     = 57  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_TRIGB_DELAY_SEL                = 58  ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_TRIGB_DELAY_SEL_LEN            = 2   ;
static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_FORCE_TEST_MODE                = 60  ;

static const uint8_t EXPLR_MCBIST_WATCFG0CQ_CFG_WAT_MSKB                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG0CQ_CFG_WAT_MSKB_LEN                   = 44  ;

static const uint8_t EXPLR_MCBIST_WATCFG0DQ_CFG_WAT_PATA                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG0DQ_CFG_WAT_PATA_LEN                   = 44  ;

static const uint8_t EXPLR_MCBIST_WATCFG0EQ_CFG_WAT_PATB                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG0EQ_CFG_WAT_PATB_LEN                   = 44  ;

static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ASEL                 = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ASEL_LEN             = 8   ;
static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_BSEL                 = 8   ;
static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_BSEL_LEN             = 8   ;
static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ABSEL                = 16  ;
static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ABSEL_LEN            = 8   ;
static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ETSEL                = 24  ;
static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ETSEL_LEN            = 8   ;
static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_CMSEL                = 32  ;
static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_CMSEL_LEN            = 8   ;
static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_CYSEL                = 40  ;
static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_CYSEL_LEN            = 8   ;

static const uint8_t EXPLR_MCBIST_WATCFG1BQ_CFG_WAT_MSKA                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG1BQ_CFG_WAT_MSKA_LEN                   = 44  ;
static const uint8_t EXPLR_MCBIST_WATCFG1BQ_CFG_WAT_CNTL                       = 44  ;
static const uint8_t EXPLR_MCBIST_WATCFG1BQ_CFG_WAT_CNTL_LEN                   = 17  ;

static const uint8_t EXPLR_MCBIST_WATCFG1CQ_CFG_WAT_MSKB                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG1CQ_CFG_WAT_MSKB_LEN                   = 44  ;

static const uint8_t EXPLR_MCBIST_WATCFG1DQ_CFG_WAT_PATA                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG1DQ_CFG_WAT_PATA_LEN                   = 44  ;

static const uint8_t EXPLR_MCBIST_WATCFG1EQ_CFG_WAT_PATB                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG1EQ_CFG_WAT_PATB_LEN                   = 44  ;

static const uint8_t EXPLR_MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL                  = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL_LEN              = 48  ;

static const uint8_t EXPLR_MCBIST_WATCFG2BQ_CFG_WAT_MSKA                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG2BQ_CFG_WAT_MSKA_LEN                   = 44  ;
static const uint8_t EXPLR_MCBIST_WATCFG2BQ_CFG_WAT_CNTL                       = 44  ;
static const uint8_t EXPLR_MCBIST_WATCFG2BQ_CFG_WAT_CNTL_LEN                   = 17  ;

static const uint8_t EXPLR_MCBIST_WATCFG2CQ_CFG_WAT_MSKB                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG2CQ_CFG_WAT_MSKB_LEN                   = 44  ;

static const uint8_t EXPLR_MCBIST_WATCFG2DQ_CFG_WAT_PATA                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG2DQ_CFG_WAT_PATA_LEN                   = 44  ;

static const uint8_t EXPLR_MCBIST_WATCFG2EQ_CFG_WAT_PATB                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG2EQ_CFG_WAT_PATB_LEN                   = 44  ;

static const uint8_t EXPLR_MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL                  = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL_LEN              = 48  ;

static const uint8_t EXPLR_MCBIST_WATCFG3BQ_CFG_WAT_MSKA                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG3BQ_CFG_WAT_MSKA_LEN                   = 44  ;
static const uint8_t EXPLR_MCBIST_WATCFG3BQ_CFG_WAT_CNTL                       = 44  ;
static const uint8_t EXPLR_MCBIST_WATCFG3BQ_CFG_WAT_CNTL_LEN                   = 17  ;

static const uint8_t EXPLR_MCBIST_WATCFG3CQ_CFG_WAT_MSKB                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG3CQ_CFG_WAT_MSKB_LEN                   = 44  ;

static const uint8_t EXPLR_MCBIST_WATCFG3DQ_CFG_WAT_PATA                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG3DQ_CFG_WAT_PATA_LEN                   = 44  ;

static const uint8_t EXPLR_MCBIST_WATCFG3EQ_CFG_WAT_PATB                       = 0   ;
static const uint8_t EXPLR_MCBIST_WATCFG3EQ_CFG_WAT_PATB_LEN                   = 44  ;

static const uint8_t EXPLR_MMIO_MCFGERR_RESP_CODE                              = 16  ;
static const uint8_t EXPLR_MMIO_MCFGERR_RESP_CODE_LEN                          = 4   ;
static const uint8_t EXPLR_MMIO_MCFGERR_BDI                                    = 20  ;
static const uint8_t EXPLR_MMIO_MCFGERR_ERROR_TYPE                             = 21  ;
static const uint8_t EXPLR_MMIO_MCFGERR_ERROR_TYPE_LEN                         = 3   ;
static const uint8_t EXPLR_MMIO_MCFGERR_DEVICE                                 = 24  ;
static const uint8_t EXPLR_MMIO_MCFGERR_DEVICE_LEN                             = 5   ;
static const uint8_t EXPLR_MMIO_MCFGERR_FUNCTION                               = 29  ;
static const uint8_t EXPLR_MMIO_MCFGERR_FUNCTION_LEN                           = 3   ;
static const uint8_t EXPLR_MMIO_MCFGERR_DEV_FUNC_MISMATCH                      = 32  ;
static const uint8_t EXPLR_MMIO_MCFGERR_DETECT_BAD_OP                          = 33  ;
static const uint8_t EXPLR_MMIO_MCFGERR_TBIT_IS_1                              = 34  ;
static const uint8_t EXPLR_MMIO_MCFGERR_DATA_IS_BAD                            = 35  ;
static const uint8_t EXPLR_MMIO_MCFGERR_PL_IS_INVALID                          = 36  ;
static const uint8_t EXPLR_MMIO_MCFGERR_BAD_OP_OR_ALIGN                        = 37  ;
static const uint8_t EXPLR_MMIO_MCFGERR_ADDR_NO_IMPLEMENTED                    = 38  ;
static const uint8_t EXPLR_MMIO_MCFGERR_RDATA_VLD                              = 39  ;
static const uint8_t EXPLR_MMIO_MCFGERR_TBIT                                   = 40  ;
static const uint8_t EXPLR_MMIO_MCFGERR_PLEN                                   = 41  ;
static const uint8_t EXPLR_MMIO_MCFGERR_PLEN_LEN                               = 3   ;
static const uint8_t EXPLR_MMIO_MCFGERR_PORTNUM                                = 44  ;
static const uint8_t EXPLR_MMIO_MCFGERR_PORTNUM_LEN                            = 2   ;
static const uint8_t EXPLR_MMIO_MCFGERR_DL                                     = 46  ;
static const uint8_t EXPLR_MMIO_MCFGERR_DL_LEN                                 = 2   ;
static const uint8_t EXPLR_MMIO_MCFGERR_CAPPTAG                                = 48  ;
static const uint8_t EXPLR_MMIO_MCFGERR_CAPPTAG_LEN                            = 16  ;

static const uint8_t EXPLR_MMIO_MCFGERRA_ADDR                                  = 0   ;
static const uint8_t EXPLR_MMIO_MCFGERRA_ADDR_LEN                              = 64  ;

static const uint8_t EXPLR_MMIO_MCHOLD_FIR_MASK_PAR_ERR                        = 0   ;
static const uint8_t EXPLR_MMIO_MCHOLD_FIR_ACTION0_PAR_ERR                     = 1   ;
static const uint8_t EXPLR_MMIO_MCHOLD_FIR_ACTION1_PAR_ERR                     = 2   ;

static const uint8_t EXPLR_MMIO_MCMASK_MASK_FIR_MASK_PAR_ERR                   = 0   ;
static const uint8_t EXPLR_MMIO_MCMASK_MASK_FIR_ACTION0_PAR_ERR                = 1   ;
static const uint8_t EXPLR_MMIO_MCMASK_MASK_FIR_ACTION1_PAR_ERR                = 2   ;

static const uint8_t EXPLR_MMIO_MDBELL_MDBELL                                  = 0   ;

static const uint8_t EXPLR_MMIO_MDBELLC_MDBELL_MDBELL                          = 0   ;

static const uint8_t EXPLR_MMIO_MDEBUG0_DBGBUS_64_87                           = 0   ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGBUS_64_87_LEN                       = 24  ;
static const uint8_t EXPLR_MMIO_MDEBUG0_SPARE                                  = 24  ;
static const uint8_t EXPLR_MMIO_MDEBUG0_SPARE_LEN                              = 8   ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL7                                = 32  ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL7_LEN                            = 4   ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL6                                = 36  ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL6_LEN                            = 4   ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL5                                = 40  ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL5_LEN                            = 4   ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL4                                = 44  ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL4_LEN                            = 4   ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL3                                = 48  ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL3_LEN                            = 4   ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL2                                = 52  ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL2_LEN                            = 4   ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL1                                = 56  ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL1_LEN                            = 4   ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL0                                = 60  ;
static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL0_LEN                            = 4   ;

static const uint8_t EXPLR_MMIO_MDEBUG1_DBGBUS_0_63                            = 0   ;
static const uint8_t EXPLR_MMIO_MDEBUG1_DBGBUS_0_63_LEN                        = 64  ;

static const uint8_t EXPLR_MMIO_MENTERP_MMIO_ENTERPRISE_MODE                   = 0   ;
static const uint8_t EXPLR_MMIO_MENTERP_HALF_DIMM_MODE                         = 1   ;
static const uint8_t EXPLR_MMIO_MENTERP_CFG_ENTERPRISE_MODE                    = 2   ;

static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BITS                              = 0   ;
static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BITS_LEN                          = 44  ;
static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BITS_44_46                        = 44  ;
static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BITS_44_46_LEN                    = 3   ;
static const uint8_t EXPLR_MMIO_MERRCTL_PASID_CHK_DIS                          = 47  ;
static const uint8_t EXPLR_MMIO_MERRCTL_ACTAG_CHK_DIS                          = 48  ;
static const uint8_t EXPLR_MMIO_MERRCTL_MSCC_RNGE_CHK_DIS                      = 49  ;
static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BIT_50                            = 50  ;
static const uint8_t EXPLR_MMIO_MERRCTL_HOLD_ACUM                              = 51  ;
static const uint8_t EXPLR_MMIO_MERRCTL_SNSC_MASTER_ENABLE                     = 52  ;
static const uint8_t EXPLR_MMIO_MERRCTL_TRAP_CLEAR                             = 53  ;
static const uint8_t EXPLR_MMIO_MERRCTL_WDATA_P                                = 54  ;
static const uint8_t EXPLR_MMIO_MERRCTL_RNW                                    = 55  ;
static const uint8_t EXPLR_MMIO_MERRCTL_ADDR                                   = 56  ;
static const uint8_t EXPLR_MMIO_MERRCTL_ADDR_LEN                               = 8   ;

static const uint8_t EXPLR_MMIO_MFIR_AFU_DESC_UNIMP                            = 0   ;
static const uint8_t EXPLR_MMIO_MFIR_MMIO_ERR                                  = 1   ;
static const uint8_t EXPLR_MMIO_MFIR_SCOM_ERR                                  = 2   ;
static const uint8_t EXPLR_MMIO_MFIR_FSM_PERR                                  = 3   ;
static const uint8_t EXPLR_MMIO_MFIR_FIFO_OVERFLOW                             = 4   ;
static const uint8_t EXPLR_MMIO_MFIR_CTL_REG_PERR                              = 5   ;
static const uint8_t EXPLR_MMIO_MFIR_INFO_REG_PERR                             = 6   ;
static const uint8_t EXPLR_MMIO_MFIR_SNSC_BOTH_STARTS_ERR                      = 7   ;
static const uint8_t EXPLR_MMIO_MFIR_SNSC_MULT_SEQ_PERR                        = 8   ;
static const uint8_t EXPLR_MMIO_MFIR_SNSC_FSM_PERR                             = 9   ;
static const uint8_t EXPLR_MMIO_MFIR_SNSC_REG_PERR                             = 10  ;
static const uint8_t EXPLR_MMIO_MFIR_ACTAG_PASID_CFG_ERR                       = 11  ;

static const uint8_t EXPLR_MMIO_MFIRACT0_FIR_ACTION0                           = 0   ;
static const uint8_t EXPLR_MMIO_MFIRACT0_FIR_ACTION0_LEN                       = 12  ;

static const uint8_t EXPLR_MMIO_MFIRACT1_FIR_ACTION1                           = 0   ;
static const uint8_t EXPLR_MMIO_MFIRACT1_FIR_ACTION1_LEN                       = 12  ;

static const uint8_t EXPLR_MMIO_MFIRMASK_FIR_MASK                              = 0   ;
static const uint8_t EXPLR_MMIO_MFIRMASK_FIR_MASK_LEN                          = 12  ;

static const uint8_t EXPLR_MMIO_MFIRWOF_FIR_WOF                                = 0   ;
static const uint8_t EXPLR_MMIO_MFIRWOF_FIR_WOF_LEN                            = 12  ;

static const uint8_t EXPLR_MMIO_MHOLD0_O0MBIT_O0DID_PERR                       = 0   ;
static const uint8_t EXPLR_MMIO_MHOLD0_O0CCD_PERR                              = 1   ;
static const uint8_t EXPLR_MMIO_MHOLD0_O0BAR0_PERR                             = 2   ;
static const uint8_t EXPLR_MMIO_MHOLD0_O0BAR1_PERR                             = 3   ;
static const uint8_t EXPLR_MMIO_MHOLD0_O0BAR2_PERR                             = 4   ;
static const uint8_t EXPLR_MMIO_MHOLD0_O0SSYSID_PERR                           = 5   ;
static const uint8_t EXPLR_MMIO_MHOLD0_O0CAPPTR_O0ROMBAR_PERR                  = 6   ;
static const uint8_t EXPLR_MMIO_MHOLD0_OVPD_PERR                               = 7   ;
static const uint8_t EXPLR_MMIO_MHOLD0_ODSNLO_ODSNCAP_PERR                     = 8   ;
static const uint8_t EXPLR_MMIO_MHOLD0_ODSNHI_PERR                             = 9   ;
static const uint8_t EXPLR_MMIO_MHOLD0_OTLVID_OTLCAP_PERR                      = 10  ;
static const uint8_t EXPLR_MMIO_MHOLD0_OVERCAP_OTLID_PERR                      = 11  ;
static const uint8_t EXPLR_MMIO_MHOLD0_OVERCFG_PERR                            = 12  ;
static const uint8_t EXPLR_MMIO_MHOLD0_ORTCAP_PERR                             = 13  ;
static const uint8_t EXPLR_MMIO_MHOLD0_OTTCFG_PERR                             = 14  ;
static const uint8_t EXPLR_MMIO_MHOLD0_ORRCAP10_PERR                           = 15  ;
static const uint8_t EXPLR_MMIO_MHOLD0_ORRCAP32_PERR                           = 16  ;
static const uint8_t EXPLR_MMIO_MHOLD0_ORRCAP54_PERR                           = 17  ;
static const uint8_t EXPLR_MMIO_MHOLD0_ORRCAP76_PERR                           = 18  ;
static const uint8_t EXPLR_MMIO_MHOLD0_OTRCFG10_PERR                           = 19  ;
static const uint8_t EXPLR_MMIO_MHOLD0_OTRCFG32_PERR                           = 20  ;
static const uint8_t EXPLR_MMIO_MHOLD0_OTRCFG54_PERR                           = 21  ;
static const uint8_t EXPLR_MMIO_MHOLD0_OTRCFG76_PERR                           = 22  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O0FNVID_O0FNCAP_PERR                    = 23  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O0ACTAG_O0FNID_PERR                     = 24  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O0VSVID_O0VSCAP_PERR                    = 25  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O0VSID_PERR                             = 26  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1MBIT_O1DID_PERR                       = 27  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1CCD_PERR                              = 28  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1BAR0_PERR                             = 29  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1BAR1_PERR                             = 30  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1BAR2_PERR                             = 31  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1SSYSID_PERR                           = 32  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1CAPPTR_O1ROMBAR_PERR                  = 33  ;
static const uint8_t EXPLR_MMIO_MHOLD0_OPASID_PERR                             = 34  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1FNVID_O1FNCAP_PERR                    = 35  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1ACTAG_O1FNID_PERR                     = 36  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1INFVID_O1INFCAP_PERR                  = 37  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1INFOFF_O1INFID_PERR                   = 38  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1INFDAT_PERR                           = 39  ;
static const uint8_t EXPLR_MMIO_MHOLD0_OCTRLVID_OCTRLCAP_PERR                  = 40  ;
static const uint8_t EXPLR_MMIO_MHOLD0_OCTRLENB_OCTRLID_PERR                   = 41  ;
static const uint8_t EXPLR_MMIO_MHOLD0_OCTRLPID_PERR                           = 42  ;
static const uint8_t EXPLR_MMIO_MHOLD0_OCTRLTAG_PERR                           = 43  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1VSVID_O1VSCAP_PERR                    = 44  ;
static const uint8_t EXPLR_MMIO_MHOLD0_O1VSID_PERR                             = 45  ;
static const uint8_t EXPLR_MMIO_MHOLD0_AFU_DESC_UNIMP                          = 46  ;
static const uint8_t EXPLR_MMIO_MHOLD0_MMIO_ERR                                = 47  ;
static const uint8_t EXPLR_MMIO_MHOLD0_SCOM_ERR                                = 48  ;
static const uint8_t EXPLR_MMIO_MHOLD0_SCOM_CCMD_FSMPERR                       = 49  ;
static const uint8_t EXPLR_MMIO_MHOLD0_SCOM_CRESP_FSMPERR                      = 50  ;
static const uint8_t EXPLR_MMIO_MHOLD0_CTL_MMIO_FSMPERR                        = 51  ;
static const uint8_t EXPLR_MMIO_MHOLD0_CTL_CCMD_FSMPERR                        = 52  ;
static const uint8_t EXPLR_MMIO_MHOLD0_CTL_CRESP_FSMPERR                       = 53  ;
static const uint8_t EXPLR_MMIO_MHOLD0_PIB_FSMPERR                             = 54  ;
static const uint8_t EXPLR_MMIO_MHOLD0_CMUX_ARBPERR                            = 55  ;
static const uint8_t EXPLR_MMIO_MHOLD0_CFG_CMDFIFO_OVRFLOW                     = 56  ;
static const uint8_t EXPLR_MMIO_MHOLD0_CFG_RESPFIFO_OVRFLOW                    = 57  ;
static const uint8_t EXPLR_MMIO_MHOLD0_CFGP_FIFO_OVRFLOW                       = 58  ;
static const uint8_t EXPLR_MMIO_MHOLD0_MERRCTL_PERR                            = 59  ;
static const uint8_t EXPLR_MMIO_MHOLD0_MHOLD1_PERR                             = 60  ;
static const uint8_t EXPLR_MMIO_MHOLD0_MMASK1_PERR                             = 61  ;
static const uint8_t EXPLR_MMIO_MHOLD0_MDBELL_PERR                             = 62  ;
static const uint8_t EXPLR_MMIO_MHOLD0_MSCCRNGE_PERR                           = 63  ;

static const uint8_t EXPLR_MMIO_MHOLD1_ONAME0_ODESCTML_PERR                    = 0   ;
static const uint8_t EXPLR_MMIO_MHOLD1_ONAME21_PERR                            = 1   ;
static const uint8_t EXPLR_MMIO_MHOLD1_ONAME43_PERR                            = 2   ;
static const uint8_t EXPLR_MMIO_MHOLD1_OAFUVER_ONAME5_PERR                     = 3   ;
static const uint8_t EXPLR_MMIO_MHOLD1_OGMMIOOF_PERR                           = 4   ;
static const uint8_t EXPLR_MMIO_MHOLD1_OGMMIOSZ_PERR                           = 5   ;
static const uint8_t EXPLR_MMIO_MHOLD1_OPMMIOOOF_PERR                          = 6   ;
static const uint8_t EXPLR_MMIO_MHOLD1_OPMMIOST_PERR                           = 7   ;
static const uint8_t EXPLR_MMIO_MHOLD1_OMEMADDR_PERR                           = 8   ;
static const uint8_t EXPLR_MMIO_MHOLD1_OWWID10_PERR                            = 9   ;
static const uint8_t EXPLR_MMIO_MHOLD1_OWWID32_PERR                            = 10  ;
static const uint8_t EXPLR_MMIO_MHOLD1_MHOLD0_PERR                             = 11  ;
static const uint8_t EXPLR_MMIO_MHOLD1_MMASK0_PERR                             = 12  ;
static const uint8_t EXPLR_MMIO_MHOLD1_MMIOERR_PERR                            = 13  ;
static const uint8_t EXPLR_MMIO_MHOLD1_MMIOEWD_PERR                            = 14  ;
static const uint8_t EXPLR_MMIO_MHOLD1_SCOMEWD_PERR                            = 15  ;
static const uint8_t EXPLR_MMIO_MHOLD1_MCFGERRA_PERR                           = 16  ;
static const uint8_t EXPLR_MMIO_MHOLD1_MCFGERRB_PERR                           = 17  ;
static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_BOTH_STARTS_ERR                    = 18  ;
static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_MULT_SEQ_PERR                      = 19  ;
static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_FSM_PERR                           = 20  ;
static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_OCTHERM_PERR                       = 21  ;
static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_D0THERM_PERR                       = 22  ;
static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_D1THERM_PERR                       = 23  ;
static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_RDWR_PERR                          = 24  ;
static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_ACTPWRUP_PERR                      = 25  ;
static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_FRAMESR_PERR                       = 26  ;
static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_HISTOBASELOW_PERR                  = 27  ;
static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_HISTOBASEHIGH_PERR                 = 28  ;
static const uint8_t EXPLR_MMIO_MHOLD1_O0VSTLXA_PERR                           = 29  ;
static const uint8_t EXPLR_MMIO_MHOLD1_O0VSTLXB_PERR                           = 30  ;
static const uint8_t EXPLR_MMIO_MHOLD1_O0VSDLXA_PERR                           = 31  ;
static const uint8_t EXPLR_MMIO_MHOLD1_O0VSDLXB_PERR                           = 32  ;
static const uint8_t EXPLR_MMIO_MHOLD1_O0VSFLSH_PERR                           = 33  ;
static const uint8_t EXPLR_MMIO_MHOLD1_BAD_FUNC_ACTAG_LENGTH                   = 34  ;
static const uint8_t EXPLR_MMIO_MHOLD1_BAD_AFU_ACTAG_LENGTH                    = 35  ;
static const uint8_t EXPLR_MMIO_MHOLD1_BAD_FUNC_PASID_LENGTH                   = 36  ;
static const uint8_t EXPLR_MMIO_MHOLD1_BAD_AFU_PASID_LENGTH                    = 37  ;
static const uint8_t EXPLR_MMIO_MHOLD1_MENTRP_PERR                             = 38  ;
static const uint8_t EXPLR_MMIO_MHOLD1_OSYSMEML_PERR                           = 39  ;
static const uint8_t EXPLR_MMIO_MHOLD1_MDEBUG0_PERR                            = 40  ;
static const uint8_t EXPLR_MMIO_MHOLD1_MDEBUG1_PERR                            = 41  ;

static const uint8_t EXPLR_MMIO_MMASK0_MSK                                     = 0   ;
static const uint8_t EXPLR_MMIO_MMASK0_MSK_LEN                                 = 64  ;

static const uint8_t EXPLR_MMIO_MMASK1_MSK                                     = 0   ;
static const uint8_t EXPLR_MMIO_MMASK1_MSK_LEN                                 = 42  ;

static const uint8_t EXPLR_MMIO_MMIOERR_WDATA_P                                = 0   ;
static const uint8_t EXPLR_MMIO_MMIOERR_WDATA_P_LEN                            = 8   ;
static const uint8_t EXPLR_MMIO_MMIOERR_INFO                                   = 8   ;
static const uint8_t EXPLR_MMIO_MMIOERR_INFO_LEN                               = 16  ;
static const uint8_t EXPLR_MMIO_MMIOERR_PLEN                                   = 25  ;
static const uint8_t EXPLR_MMIO_MMIOERR_PLEN_LEN                               = 3   ;
static const uint8_t EXPLR_MMIO_MMIOERR_RNW                                    = 28  ;
static const uint8_t EXPLR_MMIO_MMIOERR_ADDR                                   = 29  ;
static const uint8_t EXPLR_MMIO_MMIOERR_ADDR_LEN                               = 35  ;

static const uint8_t EXPLR_MMIO_MMIOEWD_WDATA                                  = 0   ;
static const uint8_t EXPLR_MMIO_MMIOEWD_WDATA_LEN                              = 64  ;

static const uint8_t EXPLR_MMIO_MPIBERR0_ERRINFO                               = 0   ;
static const uint8_t EXPLR_MMIO_MPIBERR0_ERRINFO_LEN                           = 64  ;

static const uint8_t EXPLR_MMIO_MPIBERR1_ERRINFO                               = 0   ;
static const uint8_t EXPLR_MMIO_MPIBERR1_ERRINFO_LEN                           = 64  ;

static const uint8_t EXPLR_MMIO_MPIBERR2_ERRINFO                               = 0   ;
static const uint8_t EXPLR_MMIO_MPIBERR2_ERRINFO_LEN                           = 64  ;

static const uint8_t EXPLR_MMIO_MPIBERR3_ERRINFO                               = 0   ;
static const uint8_t EXPLR_MMIO_MPIBERR3_ERRINFO_LEN                           = 64  ;

static const uint8_t EXPLR_MMIO_MSCCRNGE_LOWER                                 = 0   ;
static const uint8_t EXPLR_MMIO_MSCCRNGE_LOWER_LEN                             = 29  ;
static const uint8_t EXPLR_MMIO_MSCCRNGE_UPPER                                 = 32  ;
static const uint8_t EXPLR_MMIO_MSCCRNGE_UPPER_LEN                             = 32  ;

static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_ACTAG_BASE                      = 4   ;
static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_ACTAG_BASE_LEN                  = 12  ;
static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_ACTAG_LENGTH                    = 20  ;
static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_ACTAG_LENGTH_LEN                = 12  ;
static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_AFU_PRESENT                     = 32  ;
static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_MAX_AFU_INDEX                   = 34  ;
static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_MAX_AFU_INDEX_LEN               = 6   ;
static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_FUNCTION_RESET                  = 40  ;
static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_DVSEC_ID                        = 48  ;
static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_DVSEC_ID_LEN                    = 16  ;

static const uint8_t EXPLR_MMIO_O0BAR0_BAR_ADDRESS                             = 0   ;
static const uint8_t EXPLR_MMIO_O0BAR0_BAR_ADDRESS_LEN                         = 60  ;
static const uint8_t EXPLR_MMIO_O0BAR0_PREFETCHABLE                            = 60  ;
static const uint8_t EXPLR_MMIO_O0BAR0_TYPE                                    = 61  ;
static const uint8_t EXPLR_MMIO_O0BAR0_TYPE_LEN                                = 2   ;
static const uint8_t EXPLR_MMIO_O0BAR0_ADDRESS_SPACE                           = 63  ;

static const uint8_t EXPLR_MMIO_O0BAR1_BAR_ADDRESS                             = 0   ;
static const uint8_t EXPLR_MMIO_O0BAR1_BAR_ADDRESS_LEN                         = 60  ;
static const uint8_t EXPLR_MMIO_O0BAR1_PREFETCHABLE                            = 60  ;
static const uint8_t EXPLR_MMIO_O0BAR1_TYPE                                    = 61  ;
static const uint8_t EXPLR_MMIO_O0BAR1_TYPE_LEN                                = 2   ;
static const uint8_t EXPLR_MMIO_O0BAR1_ADDRESS_SPACE                           = 63  ;

static const uint8_t EXPLR_MMIO_O0BAR2_BAR_ADDRESS                             = 0   ;
static const uint8_t EXPLR_MMIO_O0BAR2_BAR_ADDRESS_LEN                         = 60  ;
static const uint8_t EXPLR_MMIO_O0BAR2_PREFETCHABLE                            = 60  ;
static const uint8_t EXPLR_MMIO_O0BAR2_TYPE                                    = 61  ;
static const uint8_t EXPLR_MMIO_O0BAR2_TYPE_LEN                                = 2   ;
static const uint8_t EXPLR_MMIO_O0BAR2_ADDRESS_SPACE                           = 63  ;

static const uint8_t EXPLR_MMIO_O0CAPPTR_O0ROMBAR_ROM_BASE                     = 32  ;
static const uint8_t EXPLR_MMIO_O0CAPPTR_O0ROMBAR_ROM_BASE_LEN                 = 21  ;
static const uint8_t EXPLR_MMIO_O0CAPPTR_O0ROMBAR_ROM_ENABLE                   = 63  ;

static const uint8_t EXPLR_MMIO_O0CCD_MULTI_FUNCTION                           = 8   ;
static const uint8_t EXPLR_MMIO_O0CCD_CLASS_CODE                               = 32  ;
static const uint8_t EXPLR_MMIO_O0CCD_CLASS_CODE_LEN                           = 24  ;
static const uint8_t EXPLR_MMIO_O0CCD_REVISION_ID                              = 56  ;
static const uint8_t EXPLR_MMIO_O0CCD_REVISION_ID_LEN                          = 8   ;

static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_CAPABILITIES_LIST                 = 11  ;
static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_MEMORY_SPACE                      = 30  ;
static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_DEVICE_ID                         = 32  ;
static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_DEVICE_ID_LEN                     = 16  ;
static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_VENDOR_ID                         = 48  ;
static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_VENDOR_ID_LEN                     = 16  ;

static const uint8_t EXPLR_MMIO_O0SSYSID_SUBSYSTEM_ID                          = 0   ;
static const uint8_t EXPLR_MMIO_O0SSYSID_SUBSYSTEM_ID_LEN                      = 16  ;
static const uint8_t EXPLR_MMIO_O0SSYSID_SUBSYSTEM_VENDOR_ID                   = 16  ;
static const uint8_t EXPLR_MMIO_O0SSYSID_SUBSYSTEM_VENDOR_ID_LEN               = 16  ;

static const uint8_t EXPLR_MMIO_O0VSDLXA_DLX_PORT1                             = 0   ;
static const uint8_t EXPLR_MMIO_O0VSDLXA_DLX_PORT1_LEN                         = 32  ;
static const uint8_t EXPLR_MMIO_O0VSDLXA_DLX_PORT0                             = 32  ;
static const uint8_t EXPLR_MMIO_O0VSDLXA_DLX_PORT0_LEN                         = 32  ;

static const uint8_t EXPLR_MMIO_O0VSDLXB_DLX_PORT3                             = 0   ;
static const uint8_t EXPLR_MMIO_O0VSDLXB_DLX_PORT3_LEN                         = 32  ;
static const uint8_t EXPLR_MMIO_O0VSDLXB_DLX_PORT2                             = 32  ;
static const uint8_t EXPLR_MMIO_O0VSDLXB_DLX_PORT2_LEN                         = 32  ;

static const uint8_t EXPLR_MMIO_O0VSFLSH_DATA                                  = 0   ;
static const uint8_t EXPLR_MMIO_O0VSFLSH_DATA_LEN                              = 32  ;
static const uint8_t EXPLR_MMIO_O0VSFLSH_CONTROL                               = 44  ;
static const uint8_t EXPLR_MMIO_O0VSFLSH_CONTROL_LEN                           = 20  ;

static const uint8_t EXPLR_MMIO_O0VSID_VENDOR_UNIQUE                           = 32  ;
static const uint8_t EXPLR_MMIO_O0VSID_VENDOR_UNIQUE_LEN                       = 16  ;
static const uint8_t EXPLR_MMIO_O0VSID_DVSEC_ID                                = 48  ;
static const uint8_t EXPLR_MMIO_O0VSID_DVSEC_ID_LEN                            = 16  ;

static const uint8_t EXPLR_MMIO_O0VSTLXA_TLX_PORT1                             = 0   ;
static const uint8_t EXPLR_MMIO_O0VSTLXA_TLX_PORT1_LEN                         = 32  ;
static const uint8_t EXPLR_MMIO_O0VSTLXA_TLX_PORT0                             = 32  ;
static const uint8_t EXPLR_MMIO_O0VSTLXA_TLX_PORT0_LEN                         = 32  ;

static const uint8_t EXPLR_MMIO_O0VSTLXB_TLX_PORT3                             = 0   ;
static const uint8_t EXPLR_MMIO_O0VSTLXB_TLX_PORT3_LEN                         = 32  ;
static const uint8_t EXPLR_MMIO_O0VSTLXB_TLX_PORT2                             = 32  ;
static const uint8_t EXPLR_MMIO_O0VSTLXB_TLX_PORT2_LEN                         = 32  ;

static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_ACTAG_BASE                      = 4   ;
static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_ACTAG_BASE_LEN                  = 12  ;
static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_ACTAG_LENGTH                    = 20  ;
static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_ACTAG_LENGTH_LEN                = 12  ;
static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_AFU_PRESENT                     = 32  ;
static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_MAX_AFU_INDEX                   = 34  ;
static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_MAX_AFU_INDEX_LEN               = 6   ;
static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_FUNCTION_RESET                  = 40  ;
static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_DVSEC_ID                        = 48  ;
static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_DVSEC_ID_LEN                    = 16  ;

static const uint8_t EXPLR_MMIO_O1BAR0_BAR_ADDRESS                             = 0   ;
static const uint8_t EXPLR_MMIO_O1BAR0_BAR_ADDRESS_LEN                         = 29  ;
static const uint8_t EXPLR_MMIO_O1BAR0_PREFETCHABLE                            = 60  ;
static const uint8_t EXPLR_MMIO_O1BAR0_TYPE                                    = 61  ;
static const uint8_t EXPLR_MMIO_O1BAR0_TYPE_LEN                                = 2   ;
static const uint8_t EXPLR_MMIO_O1BAR0_ADDRESS_SPACE                           = 63  ;

static const uint8_t EXPLR_MMIO_O1BAR1_BAR_ADDRESS                             = 0   ;
static const uint8_t EXPLR_MMIO_O1BAR1_BAR_ADDRESS_LEN                         = 60  ;
static const uint8_t EXPLR_MMIO_O1BAR1_PREFETCHABLE                            = 60  ;
static const uint8_t EXPLR_MMIO_O1BAR1_TYPE                                    = 61  ;
static const uint8_t EXPLR_MMIO_O1BAR1_TYPE_LEN                                = 2   ;
static const uint8_t EXPLR_MMIO_O1BAR1_ADDRESS_SPACE                           = 63  ;

static const uint8_t EXPLR_MMIO_O1BAR2_BAR_ADDRESS                             = 0   ;
static const uint8_t EXPLR_MMIO_O1BAR2_BAR_ADDRESS_LEN                         = 60  ;
static const uint8_t EXPLR_MMIO_O1BAR2_PREFETCHABLE                            = 60  ;
static const uint8_t EXPLR_MMIO_O1BAR2_TYPE                                    = 61  ;
static const uint8_t EXPLR_MMIO_O1BAR2_TYPE_LEN                                = 2   ;
static const uint8_t EXPLR_MMIO_O1BAR2_ADDRESS_SPACE                           = 63  ;

static const uint8_t EXPLR_MMIO_O1CAPPTR_O1ROMBAR_ROM_BASE                     = 32  ;
static const uint8_t EXPLR_MMIO_O1CAPPTR_O1ROMBAR_ROM_BASE_LEN                 = 21  ;
static const uint8_t EXPLR_MMIO_O1CAPPTR_O1ROMBAR_ROM_ENABLE                   = 63  ;

static const uint8_t EXPLR_MMIO_O1CCD_MULTI_FUNCTION                           = 8   ;
static const uint8_t EXPLR_MMIO_O1CCD_CLASS_CODE                               = 32  ;
static const uint8_t EXPLR_MMIO_O1CCD_CLASS_CODE_LEN                           = 24  ;
static const uint8_t EXPLR_MMIO_O1CCD_REVISION_ID                              = 56  ;
static const uint8_t EXPLR_MMIO_O1CCD_REVISION_ID_LEN                          = 8   ;

static const uint8_t EXPLR_MMIO_O1INFDAT_AFU_DESCRIPTOR_DATA                   = 32  ;
static const uint8_t EXPLR_MMIO_O1INFDAT_AFU_DESCRIPTOR_DATA_LEN               = 32  ;

static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_DATA_VALID                    = 0   ;
static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_AFU_DESCRIPTOR_OFFSET         = 1   ;
static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_AFU_DESCRIPTOR_OFFSET_LEN     = 31  ;
static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_AFU_INFO_INDEX                = 42  ;
static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_AFU_INFO_INDEX_LEN            = 6   ;
static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_DVSEC_ID                      = 48  ;
static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_DVSEC_ID_LEN                  = 16  ;

static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_CAPABILITIES_LIST                 = 11  ;
static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_MEMORY_SPACE                      = 30  ;
static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_DEVICE_ID                         = 32  ;
static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_DEVICE_ID_LEN                     = 16  ;
static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_VENDOR_ID                         = 48  ;
static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_VENDOR_ID_LEN                     = 16  ;

static const uint8_t EXPLR_MMIO_O1SSYSID_SUBSYSTEM_ID                          = 0   ;
static const uint8_t EXPLR_MMIO_O1SSYSID_SUBSYSTEM_ID_LEN                      = 16  ;
static const uint8_t EXPLR_MMIO_O1SSYSID_SUBSYSTEM_VENDOR_ID                   = 16  ;
static const uint8_t EXPLR_MMIO_O1SSYSID_SUBSYSTEM_VENDOR_ID_LEN               = 16  ;

static const uint8_t EXPLR_MMIO_O1VSID_VENDOR_UNIQUE                           = 32  ;
static const uint8_t EXPLR_MMIO_O1VSID_VENDOR_UNIQUE_LEN                       = 16  ;
static const uint8_t EXPLR_MMIO_O1VSID_DVSEC_ID                                = 48  ;
static const uint8_t EXPLR_MMIO_O1VSID_DVSEC_ID_LEN                            = 16  ;

static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_VERSION_MAJOR               = 0   ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_VERSION_MAJOR_LEN           = 8   ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_VERSION_MINOR               = 8   ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_VERSION_MINOR_LEN           = 8   ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_C_TYPE                      = 16  ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_C_TYPE_LEN                  = 3   ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_M_TYPE                      = 19  ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_M_TYPE_LEN                  = 3   ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_PROFILE                         = 24  ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_PROFILE_LEN                     = 8   ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_23                   = 32  ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_23_LEN               = 8   ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_22                   = 40  ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_22_LEN               = 8   ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_21                   = 48  ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_21_LEN               = 8   ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_20                   = 56  ;
static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_20_LEN               = 8   ;

static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_AFU_UNIQUE                    = 0   ;
static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_AFU_UNIQUE_LEN                = 4   ;
static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_FENCE_AFU                     = 6   ;
static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_ENABLE_AFU                    = 7   ;
static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_RESET_AFU                     = 8   ;
static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_TERMINATE_VALID               = 11  ;
static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_PASID_TERMINATION_VALUE       = 12  ;
static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_PASID_TERMINATION_VALUE_LEN   = 20  ;
static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_AFU_CONTROL_INDEX             = 42  ;
static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_AFU_CONTROL_INDEX_LEN         = 6   ;
static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_DVSEC_ID                      = 48  ;
static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_DVSEC_ID_LEN                  = 16  ;

static const uint8_t EXPLR_MMIO_OCTRLPID_METADATA_SUPPORTED                    = 0   ;
static const uint8_t EXPLR_MMIO_OCTRLPID_METADATA_ENABLED                      = 1   ;
static const uint8_t EXPLR_MMIO_OCTRLPID_HTRL                                  = 2   ;
static const uint8_t EXPLR_MMIO_OCTRLPID_HTRL_LEN                              = 3   ;
static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_BASE                            = 12  ;
static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_BASE_LEN                        = 20  ;
static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_LENGTH_ENABLED                  = 51  ;
static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_LENGTH_ENABLED_LEN              = 5   ;
static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_LENGTH_SUPPORTED                = 59  ;
static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_LENGTH_SUPPORTED_LEN            = 5   ;

static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_BASE                        = 20  ;
static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_BASE_LEN                    = 12  ;
static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_LENGTH_ENABLED              = 36  ;
static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_LENGTH_ENABLED_LEN          = 12  ;
static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_LENGTH_SUPPORTED            = 52  ;
static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_LENGTH_SUPPORTED_LEN        = 12  ;

static const uint8_t EXPLR_MMIO_ODSNHI_DSN_HIGH                                = 32  ;
static const uint8_t EXPLR_MMIO_ODSNHI_DSN_HIGH_LEN                            = 32  ;

static const uint8_t EXPLR_MMIO_ODSNLO_ODSNCAP_DSN_LOW                         = 0   ;
static const uint8_t EXPLR_MMIO_ODSNLO_ODSNCAP_DSN_LOW_LEN                     = 32  ;

static const uint8_t EXPLR_MMIO_OGMMIOOF_OFFSET                                = 0   ;
static const uint8_t EXPLR_MMIO_OGMMIOOF_OFFSET_LEN                            = 48  ;
static const uint8_t EXPLR_MMIO_OGMMIOOF_BAR                                   = 61  ;
static const uint8_t EXPLR_MMIO_OGMMIOOF_BAR_LEN                               = 3   ;

static const uint8_t EXPLR_MMIO_OGMMIOSZ_SIZE                                  = 32  ;
static const uint8_t EXPLR_MMIO_OGMMIOSZ_SIZE_LEN                              = 32  ;

static const uint8_t EXPLR_MMIO_OMEMADDR_ADDR                                  = 0   ;
static const uint8_t EXPLR_MMIO_OMEMADDR_ADDR_LEN                              = 64  ;

static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_3                   = 0   ;
static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_3_LEN               = 8   ;
static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_2                   = 8   ;
static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_2_LEN               = 8   ;
static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_1                   = 16  ;
static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_1_LEN               = 8   ;
static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_0                   = 24  ;
static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_0_LEN               = 8   ;

static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_11                          = 0   ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_11_LEN                      = 8   ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_10                          = 8   ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_10_LEN                      = 8   ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_9                           = 16  ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_9_LEN                       = 8   ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_8                           = 24  ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_8_LEN                       = 8   ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_7                           = 32  ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_7_LEN                       = 8   ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_6                           = 40  ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_6_LEN                       = 8   ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_5                           = 48  ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_5_LEN                       = 8   ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_4                           = 56  ;
static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_4_LEN                       = 8   ;

static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_19                          = 0   ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_19_LEN                      = 8   ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_18                          = 8   ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_18_LEN                      = 8   ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_17                          = 16  ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_17_LEN                      = 8   ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_16                          = 24  ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_16_LEN                      = 8   ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_15                          = 32  ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_15_LEN                      = 8   ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_14                          = 40  ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_14_LEN                      = 8   ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_13                          = 48  ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_13_LEN                      = 8   ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_12                          = 56  ;
static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_12_LEN                      = 8   ;

static const uint8_t EXPLR_MMIO_OPASID_MAX_PASID_WIDTH                         = 19  ;
static const uint8_t EXPLR_MMIO_OPASID_MAX_PASID_WIDTH_LEN                     = 5   ;

static const uint8_t EXPLR_MMIO_OPMMIOOF_OFFSET                                = 0   ;
static const uint8_t EXPLR_MMIO_OPMMIOOF_OFFSET_LEN                            = 48  ;
static const uint8_t EXPLR_MMIO_OPMMIOOF_BAR                                   = 61  ;
static const uint8_t EXPLR_MMIO_OPMMIOOF_BAR_LEN                               = 3   ;

static const uint8_t EXPLR_MMIO_OPMMIOST_MEM_SIZE                              = 24  ;
static const uint8_t EXPLR_MMIO_OPMMIOST_MEM_SIZE_LEN                          = 8   ;
static const uint8_t EXPLR_MMIO_OPMMIOST_STRIDE                                = 32  ;
static const uint8_t EXPLR_MMIO_OPMMIOST_STRIDE_LEN                            = 16  ;

static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_55                           = 0   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_55_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_54                           = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_54_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_53                           = 8   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_53_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_52                           = 12  ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_52_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_51                           = 16  ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_51_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_50                           = 20  ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_50_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_49                           = 24  ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_49_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_48                           = 28  ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_48_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_63                           = 32  ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_63_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_62                           = 36  ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_62_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_61                           = 40  ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_61_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_60                           = 44  ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_60_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_59                           = 48  ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_59_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_58                           = 52  ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_58_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_57                           = 56  ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_57_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_56                           = 60  ;
static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_56_LEN                       = 4   ;

static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_39                           = 0   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_39_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_38                           = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_38_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_37                           = 8   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_37_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_36                           = 12  ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_36_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_35                           = 16  ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_35_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_34                           = 20  ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_34_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_33                           = 24  ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_33_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_32                           = 28  ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_32_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_47                           = 32  ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_47_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_46                           = 36  ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_46_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_45                           = 40  ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_45_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_44                           = 44  ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_44_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_43                           = 48  ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_43_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_42                           = 52  ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_42_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_41                           = 56  ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_41_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_40                           = 60  ;
static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_40_LEN                       = 4   ;

static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_23                           = 0   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_23_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_22                           = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_22_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_21                           = 8   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_21_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_20                           = 12  ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_20_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_19                           = 16  ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_19_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_18                           = 20  ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_18_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_17                           = 24  ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_17_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_16                           = 28  ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_16_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_31                           = 32  ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_31_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_30                           = 36  ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_30_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_29                           = 40  ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_29_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_28                           = 44  ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_28_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_27                           = 48  ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_27_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_26                           = 52  ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_26_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_25                           = 56  ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_25_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_24                           = 60  ;
static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_24_LEN                       = 4   ;

static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_7                            = 0   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_7_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_6                            = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_6_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_5                            = 8   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_5_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_4                            = 12  ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_4_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_3                            = 16  ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_3_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_2                            = 20  ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_2_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_1                            = 24  ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_1_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_0                            = 28  ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_0_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_15                           = 32  ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_15_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_14                           = 36  ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_14_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_13                           = 40  ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_13_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_12                           = 44  ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_12_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_11                           = 48  ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_11_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_10                           = 52  ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_10_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_9                            = 56  ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_9_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_8                            = 60  ;
static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_8_LEN                        = 4   ;

static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_31                             = 0   ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_30                             = 1   ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_29                             = 2   ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_28                             = 3   ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_27                             = 4   ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_26                             = 5   ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_25                             = 6   ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_24                             = 7   ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_23                             = 8   ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_22                             = 9   ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_21                             = 10  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_20                             = 11  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_19                             = 12  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_18                             = 13  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_17                             = 14  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_16                             = 15  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_15                             = 16  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_14                             = 17  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_13                             = 18  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_12                             = 19  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_11                             = 20  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_10                             = 21  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_9                              = 22  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_8                              = 23  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_7                              = 24  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_6                              = 25  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_5                              = 26  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_4                              = 27  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_3                              = 28  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_2                              = 29  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_1                              = 30  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_0                              = 31  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_63                             = 32  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_62                             = 33  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_61                             = 34  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_60                             = 35  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_59                             = 36  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_58                             = 37  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_57                             = 38  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_56                             = 39  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_55                             = 40  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_54                             = 41  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_53                             = 42  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_52                             = 43  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_51                             = 44  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_50                             = 45  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_49                             = 46  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_48                             = 47  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_47                             = 48  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_46                             = 49  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_45                             = 50  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_44                             = 51  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_43                             = 52  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_42                             = 53  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_41                             = 54  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_40                             = 55  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_39                             = 56  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_38                             = 57  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_37                             = 58  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_36                             = 59  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_35                             = 60  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_34                             = 61  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_33                             = 62  ;
static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_32                             = 63  ;

static const uint8_t EXPLR_MMIO_OSYSMEML_SYSLEN                                = 0   ;
static const uint8_t EXPLR_MMIO_OSYSMEML_SYSLEN_LEN                            = 48  ;

static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_55                           = 0   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_55_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_54                           = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_54_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_53                           = 8   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_53_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_52                           = 12  ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_52_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_51                           = 16  ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_51_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_50                           = 20  ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_50_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_49                           = 24  ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_49_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_48                           = 28  ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_48_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_63                           = 32  ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_63_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_62                           = 36  ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_62_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_61                           = 40  ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_61_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_60                           = 44  ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_60_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_59                           = 48  ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_59_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_58                           = 52  ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_58_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_57                           = 56  ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_57_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_56                           = 60  ;
static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_56_LEN                       = 4   ;

static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_39                           = 0   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_39_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_38                           = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_38_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_37                           = 8   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_37_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_36                           = 12  ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_36_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_35                           = 16  ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_35_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_34                           = 20  ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_34_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_33                           = 24  ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_33_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_32                           = 28  ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_32_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_47                           = 32  ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_47_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_46                           = 36  ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_46_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_45                           = 40  ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_45_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_44                           = 44  ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_44_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_43                           = 48  ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_43_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_42                           = 52  ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_42_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_41                           = 56  ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_41_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_40                           = 60  ;
static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_40_LEN                       = 4   ;

static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_23                           = 0   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_23_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_22                           = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_22_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_21                           = 8   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_21_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_20                           = 12  ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_20_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_19                           = 16  ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_19_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_18                           = 20  ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_18_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_17                           = 24  ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_17_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_16                           = 28  ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_16_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_31                           = 32  ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_31_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_30                           = 36  ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_30_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_29                           = 40  ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_29_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_28                           = 44  ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_28_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_27                           = 48  ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_27_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_26                           = 52  ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_26_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_25                           = 56  ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_25_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_24                           = 60  ;
static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_24_LEN                       = 4   ;

static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_7                            = 0   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_7_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_6                            = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_6_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_5                            = 8   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_5_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_4                            = 12  ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_4_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_3                            = 16  ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_3_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_2                            = 20  ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_2_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_1                            = 24  ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_1_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_0                            = 28  ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_0_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_15                           = 32  ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_15_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_14                           = 36  ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_14_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_13                           = 40  ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_13_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_12                           = 44  ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_12_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_11                           = 48  ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_11_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_10                           = 52  ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_10_LEN                       = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_9                            = 56  ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_9_LEN                        = 4   ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_8                            = 60  ;
static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_8_LEN                        = 4   ;

static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_31                             = 0   ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_30                             = 1   ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_29                             = 2   ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_28                             = 3   ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_27                             = 4   ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_26                             = 5   ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_25                             = 6   ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_24                             = 7   ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_23                             = 8   ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_22                             = 9   ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_21                             = 10  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_20                             = 11  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_19                             = 12  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_18                             = 13  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_17                             = 14  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_16                             = 15  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_15                             = 16  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_14                             = 17  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_13                             = 18  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_12                             = 19  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_11                             = 20  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_10                             = 21  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_9                              = 22  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_8                              = 23  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_7                              = 24  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_6                              = 25  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_5                              = 26  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_4                              = 27  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_3                              = 28  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_2                              = 29  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_1                              = 30  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_0                              = 31  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_63                             = 32  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_62                             = 33  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_61                             = 34  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_60                             = 35  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_59                             = 36  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_58                             = 37  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_57                             = 38  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_56                             = 39  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_55                             = 40  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_54                             = 41  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_53                             = 42  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_52                             = 43  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_51                             = 44  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_50                             = 45  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_49                             = 46  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_48                             = 47  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_47                             = 48  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_46                             = 49  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_45                             = 50  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_44                             = 51  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_43                             = 52  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_42                             = 53  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_41                             = 54  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_40                             = 55  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_39                             = 56  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_38                             = 57  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_37                             = 58  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_36                             = 59  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_35                             = 60  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_34                             = 61  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_33                             = 62  ;
static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_32                             = 63  ;

static const uint8_t EXPLR_MMIO_OVERCAP_OTLID_TL_MAJOR_VERSION_CAPABILITY      = 0   ;
static const uint8_t EXPLR_MMIO_OVERCAP_OTLID_TL_MAJOR_VERSION_CAPABILITY_LEN  = 8   ;
static const uint8_t EXPLR_MMIO_OVERCAP_OTLID_TL_MINOR_VERSION_CAPABILITY      = 8   ;
static const uint8_t EXPLR_MMIO_OVERCAP_OTLID_TL_MINOR_VERSION_CAPABILITY_LEN  = 8   ;

static const uint8_t EXPLR_MMIO_OVERCFG_TL_MAJOR_VERSION_CONFIGURATION         = 32  ;
static const uint8_t EXPLR_MMIO_OVERCFG_TL_MAJOR_VERSION_CONFIGURATION_LEN     = 8   ;
static const uint8_t EXPLR_MMIO_OVERCFG_TL_MINOR_VERSION_CONFIGURATION         = 40  ;
static const uint8_t EXPLR_MMIO_OVERCFG_TL_MINOR_VERSION_CONFIGURATION_LEN     = 8   ;
static const uint8_t EXPLR_MMIO_OVERCFG_LONG_BACK_OFF_TIMER                    = 56  ;
static const uint8_t EXPLR_MMIO_OVERCFG_LONG_BACK_OFF_TIMER_LEN                = 4   ;
static const uint8_t EXPLR_MMIO_OVERCFG_SHORT_BACK_OFF_TIMER                   = 60  ;
static const uint8_t EXPLR_MMIO_OVERCFG_SHORT_BACK_OFF_TIMER_LEN               = 4   ;

static const uint8_t EXPLR_MMIO_OVPD_DATA                                      = 0   ;
static const uint8_t EXPLR_MMIO_OVPD_DATA_LEN                                  = 32  ;
static const uint8_t EXPLR_MMIO_OVPD_FLAG                                      = 32  ;
static const uint8_t EXPLR_MMIO_OVPD_ADDRESS                                   = 33  ;
static const uint8_t EXPLR_MMIO_OVPD_ADDRESS_LEN                               = 15  ;
static const uint8_t EXPLR_MMIO_OVPD_NEXT_POINTER                              = 48  ;
static const uint8_t EXPLR_MMIO_OVPD_NEXT_POINTER_LEN                          = 8   ;
static const uint8_t EXPLR_MMIO_OVPD_CAPABILITY_ID                             = 56  ;
static const uint8_t EXPLR_MMIO_OVPD_CAPABILITY_ID_LEN                         = 8   ;

static const uint8_t EXPLR_MMIO_OWWID10_ID                                     = 0   ;
static const uint8_t EXPLR_MMIO_OWWID10_ID_LEN                                 = 64  ;

static const uint8_t EXPLR_MMIO_OWWID32_ID                                     = 0   ;
static const uint8_t EXPLR_MMIO_OWWID32_ID_LEN                                 = 64  ;

static const uint8_t EXPLR_MMIO_SCOMEWD_WDATA                                  = 0   ;
static const uint8_t EXPLR_MMIO_SCOMEWD_WDATA_LEN                              = 64  ;

static const uint8_t EXPLR_MMIO_SNSC_ACTPWRUP_ACTSCOUNT                        = 0   ;
static const uint8_t EXPLR_MMIO_SNSC_ACTPWRUP_ACTSCOUNT_LEN                    = 32  ;
static const uint8_t EXPLR_MMIO_SNSC_ACTPWRUP_POWERUPSCOUNT                    = 32  ;
static const uint8_t EXPLR_MMIO_SNSC_ACTPWRUP_POWERUPSCOUNT_LEN                = 32  ;

static const uint8_t EXPLR_MMIO_SNSC_D0THERM_ERRORBIT                          = 47  ;
static const uint8_t EXPLR_MMIO_SNSC_D0THERM_THERMALDATA                       = 48  ;
static const uint8_t EXPLR_MMIO_SNSC_D0THERM_THERMALDATA_LEN                   = 16  ;

static const uint8_t EXPLR_MMIO_SNSC_D1THERM_ERRORBIT                          = 47  ;
static const uint8_t EXPLR_MMIO_SNSC_D1THERM_THERMALDATA                       = 48  ;
static const uint8_t EXPLR_MMIO_SNSC_D1THERM_THERMALDATA_LEN                   = 16  ;

static const uint8_t EXPLR_MMIO_SNSC_FRAMESR_FRAMECOUNT                        = 0   ;
static const uint8_t EXPLR_MMIO_SNSC_FRAMESR_FRAMECOUNT_LEN                    = 32  ;
static const uint8_t EXPLR_MMIO_SNSC_FRAMESR_SELFREFRESHCOUNT                  = 32  ;
static const uint8_t EXPLR_MMIO_SNSC_FRAMESR_SELFREFRESHCOUNT_LEN              = 8   ;

static const uint8_t EXPLR_MMIO_SNSC_HISTOBASELOW_HISTOGRAMBASECOUNT           = 0   ;
static const uint8_t EXPLR_MMIO_SNSC_HISTOBASELOW_HISTOGRAMBASECOUNT_LEN       = 32  ;
static const uint8_t EXPLR_MMIO_SNSC_HISTOBASELOW_HISTOGRAMLOWCOUNT            = 32  ;
static const uint8_t EXPLR_MMIO_SNSC_HISTOBASELOW_HISTOGRAMLOWCOUNT_LEN        = 32  ;

static const uint8_t EXPLR_MMIO_SNSC_HISTOMEDHIGH_HISTOGRAMMEDCOUNT            = 0   ;
static const uint8_t EXPLR_MMIO_SNSC_HISTOMEDHIGH_HISTOGRAMMEDCOUNT_LEN        = 32  ;
static const uint8_t EXPLR_MMIO_SNSC_HISTOMEDHIGH_HISTOGRAMHIGHCOUNT           = 32  ;
static const uint8_t EXPLR_MMIO_SNSC_HISTOMEDHIGH_HISTOGRAMHIGHCOUNT_LEN       = 32  ;

static const uint8_t EXPLR_MMIO_SNSC_OCTHERM_ERRORBIT                          = 47  ;
static const uint8_t EXPLR_MMIO_SNSC_OCTHERM_THERMALDATA                       = 48  ;
static const uint8_t EXPLR_MMIO_SNSC_OCTHERM_THERMALDATA_LEN                   = 16  ;

static const uint8_t EXPLR_MMIO_SNSC_RDWR_READSCOUNT                           = 0   ;
static const uint8_t EXPLR_MMIO_SNSC_RDWR_READSCOUNT_LEN                       = 32  ;
static const uint8_t EXPLR_MMIO_SNSC_RDWR_WRITESCOUNT                          = 32  ;
static const uint8_t EXPLR_MMIO_SNSC_RDWR_WRITESCOUNT_LEN                      = 32  ;

static const uint8_t EXPLR_MMIO_SNSC_STATEREG_STREGISTER                       = 0   ;
static const uint8_t EXPLR_MMIO_SNSC_STATEREG_STREGISTER_LEN                   = 22  ;

static const uint8_t EXPLR_RDF_AACR_ADDRESS                                    = 0   ;
static const uint8_t EXPLR_RDF_AACR_ADDRESS_LEN                                = 7   ;
static const uint8_t EXPLR_RDF_AACR_AUTOINC                                    = 7   ;

static const uint8_t EXPLR_RDF_AADR_DATA                                       = 0   ;
static const uint8_t EXPLR_RDF_AADR_DATA_LEN                                   = 64  ;

static const uint8_t EXPLR_RDF_AAER_DATA                                       = 0   ;
static const uint8_t EXPLR_RDF_AAER_DATA_LEN                                   = 8   ;

static const uint8_t EXPLR_RDF_ACTION0_FIR                                     = 0   ;
static const uint8_t EXPLR_RDF_ACTION0_FIR_LEN                                 = 64  ;

static const uint8_t EXPLR_RDF_ACTION1_FIR                                     = 0   ;
static const uint8_t EXPLR_RDF_ACTION1_FIR_LEN                                 = 64  ;

static const uint8_t EXPLR_RDF_CERR0_MSR_PE                                    = 12  ;
static const uint8_t EXPLR_RDF_CERR0_EICR_PE                                   = 13  ;
static const uint8_t EXPLR_RDF_CERR0_HWMSX_PE                                  = 16  ;
static const uint8_t EXPLR_RDF_CERR0_HWMSX_PE_LEN                              = 8   ;
static const uint8_t EXPLR_RDF_CERR0_FWMSX_PE                                  = 24  ;
static const uint8_t EXPLR_RDF_CERR0_FWMSX_PE_LEN                              = 8   ;
static const uint8_t EXPLR_RDF_CERR0_RSPAR_PE                                  = 32  ;
static const uint8_t EXPLR_RDF_CERR0_AACR_PE                                   = 41  ;
static const uint8_t EXPLR_RDF_CERR0_MCBCM_PE                                  = 44  ;
static const uint8_t EXPLR_RDF_CERR0_RECR_PE                                   = 45  ;
static const uint8_t EXPLR_RDF_CERR0_DBGR_PE                                   = 46  ;
static const uint8_t EXPLR_RDF_CERR0_MASK0_PE                                  = 48  ;
static const uint8_t EXPLR_RDF_CERR0_MASK1_PE                                  = 49  ;
static const uint8_t EXPLR_RDF_CERR0_CGDR_PE                                   = 50  ;

static const uint8_t EXPLR_RDF_CERR1_ECC_CTL_AF_PERR                           = 0   ;
static const uint8_t EXPLR_RDF_CERR1_ECC_CTL_TCHN_PERR                         = 1   ;
static const uint8_t EXPLR_RDF_CERR1_ECC_CTL_CMPMODE_ERR                       = 2   ;
static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_PCX_PERR                         = 3   ;
static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_SYND_PERR                        = 4   ;
static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_2SYM_PERR                        = 5   ;
static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_CPLX_PERR                        = 6   ;
static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_EP2_PERR                         = 7   ;
static const uint8_t EXPLR_RDF_CERR1_READ_ECC_DATAPATH_PARITY_ERROR            = 8   ;
static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_CMX_PERR                         = 9   ;
static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_VP1_PERR                         = 10  ;
static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_VP2_PERR                         = 11  ;
static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_SYG_PERR                         = 12  ;
static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_EF1_PERR                         = 13  ;
static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_MK3_PERR                         = 14  ;
static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_E1A_PERR                         = 15  ;
static const uint8_t EXPLR_RDF_CERR1_UNEXPECTED_RDDATA_VALID                   = 16  ;
static const uint8_t EXPLR_RDF_CERR1_MISSING_RDDATA_VALID                      = 17  ;
static const uint8_t EXPLR_RDF_CERR1_RBUF_ECC_ERR_CE_DW0                       = 20  ;
static const uint8_t EXPLR_RDF_CERR1_RBUF_ECC_ERR_UE_DW0                       = 21  ;
static const uint8_t EXPLR_RDF_CERR1_RBUF_ECC_ERR_CE_DW1                       = 22  ;
static const uint8_t EXPLR_RDF_CERR1_RBUF_ECC_ERR_UE_DW1                       = 23  ;
static const uint8_t EXPLR_RDF_CERR1_RD_BUFF_ECC_ERR_SYNDROME                  = 24  ;
static const uint8_t EXPLR_RDF_CERR1_RD_BUFF_ECC_ERR_SYNDROME_LEN              = 8   ;

static const uint8_t EXPLR_RDF_CGDR_CGDIS_PCTL                                 = 0   ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_RESP                                 = 1   ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_RMW                                  = 2   ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_LPTR                                 = 3   ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_AHASH                                = 4   ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_STG                                  = 5   ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_OUT                                  = 6   ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_TLM                                  = 7   ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_BD                                   = 8   ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_DCMP                                 = 9   ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_RBCTL                                = 10  ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_RBRMW                                = 11  ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_RBTRC                                = 12  ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_MPE                                  = 13  ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_CONF                                 = 14  ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_HWMS                                 = 15  ;
static const uint8_t EXPLR_RDF_CGDR_PSDIS_ZERO_SYND                            = 16  ;
static const uint8_t EXPLR_RDF_CGDR_PSDIS_SAME_MARKS                           = 17  ;
static const uint8_t EXPLR_RDF_CGDR_PSDIS_SAME_STEER                           = 18  ;
static const uint8_t EXPLR_RDF_CGDR_CGDIS_SPARE                                = 19  ;

static const uint8_t EXPLR_RDF_CTCR_MPE_TIMER                                  = 0   ;
static const uint8_t EXPLR_RDF_CTCR_MPE_TIMER_LEN                              = 6   ;
static const uint8_t EXPLR_RDF_CTCR_MPE_TIMEBASE                               = 6   ;
static const uint8_t EXPLR_RDF_CTCR_MPE_TIMEBASE_LEN                           = 3   ;
static const uint8_t EXPLR_RDF_CTCR_UE_TIMER                                   = 9   ;
static const uint8_t EXPLR_RDF_CTCR_UE_TIMER_LEN                               = 6   ;
static const uint8_t EXPLR_RDF_CTCR_UE_TIMEBASE                                = 15  ;
static const uint8_t EXPLR_RDF_CTCR_UE_TIMEBASE_LEN                            = 3   ;
static const uint8_t EXPLR_RDF_CTCR_UE_LOCKOUT_ENABLE                          = 18  ;

static const uint8_t EXPLR_RDF_DBGR_PRIMARY_SELECT                             = 0   ;
static const uint8_t EXPLR_RDF_DBGR_PRIMARY_SELECT_LEN                         = 4   ;
static const uint8_t EXPLR_RDF_DBGR_SECONDARY_SELECT                           = 4   ;
static const uint8_t EXPLR_RDF_DBGR_SECONDARY_SELECT_LEN                       = 4   ;
static const uint8_t EXPLR_RDF_DBGR_EPX_CHIP                                   = 8   ;
static const uint8_t EXPLR_RDF_DBGR_EPX_SYMS                                   = 9   ;
static const uint8_t EXPLR_RDF_DBGR_TRACE_ALWAYS                               = 10  ;
static const uint8_t EXPLR_RDF_DBGR_WAT_ENABLE                                 = 11  ;
static const uint8_t EXPLR_RDF_DBGR_WAT_ACTION_SELECT                          = 12  ;
static const uint8_t EXPLR_RDF_DBGR_WAT_SOURCE                                 = 13  ;
static const uint8_t EXPLR_RDF_DBGR_WAT_SOURCE_LEN                             = 2   ;

static const uint8_t EXPLR_RDF_EICR_ADDRESS                                    = 0   ;
static const uint8_t EXPLR_RDF_EICR_ADDRESS_LEN                                = 37  ;
static const uint8_t EXPLR_RDF_EICR_RESERVED                                   = 37  ;
static const uint8_t EXPLR_RDF_EICR_PERSIST                                    = 38  ;
static const uint8_t EXPLR_RDF_EICR_PERSIST_LEN                                = 2   ;
static const uint8_t EXPLR_RDF_EICR_REGION                                     = 40  ;
static const uint8_t EXPLR_RDF_EICR_REGION_LEN                                 = 3   ;
static const uint8_t EXPLR_RDF_EICR_TYPE                                       = 43  ;
static const uint8_t EXPLR_RDF_EICR_TYPE_LEN                                   = 5   ;
static const uint8_t EXPLR_RDF_EICR_MISC                                       = 48  ;
static const uint8_t EXPLR_RDF_EICR_MISC_LEN                                   = 6   ;

static const uint8_t EXPLR_RDF_ELPR_LOG_FULL                                   = 0   ;
static const uint8_t EXPLR_RDF_ELPR_LOG_POINTER                                = 2   ;
static const uint8_t EXPLR_RDF_ELPR_LOG_POINTER_LEN                            = 6   ;

static const uint8_t EXPLR_RDF_ERR_HOLD_LAT_FIR_MASK_PAR                       = 0   ;
static const uint8_t EXPLR_RDF_ERR_HOLD_LAT_FIR_ACTION0_PAR                    = 1   ;
static const uint8_t EXPLR_RDF_ERR_HOLD_LAT_FIR_ACTION1_PAR                    = 2   ;

static const uint8_t EXPLR_RDF_ERR_MASK_LAT_FIR_PAR                            = 0   ;
static const uint8_t EXPLR_RDF_ERR_MASK_LAT_FIR_ACTION0_PAR                    = 1   ;
static const uint8_t EXPLR_RDF_ERR_MASK_LAT_FIR_ACTION1_PAR                    = 2   ;

static const uint8_t EXPLR_RDF_FIR_MAINLINE_MPE_RANK_0_TO_7                    = 0   ;
static const uint8_t EXPLR_RDF_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN                = 8   ;
static const uint8_t EXPLR_RDF_FIR_MAINLINE_NCE                                = 8   ;
static const uint8_t EXPLR_RDF_FIR_MAINLINE_TCE                                = 9   ;
static const uint8_t EXPLR_RDF_FIR_MAINLINE_SCE                                = 10  ;
static const uint8_t EXPLR_RDF_FIR_MAINLINE_MCE                                = 11  ;
static const uint8_t EXPLR_RDF_FIR_MAINLINE_SUE                                = 12  ;
static const uint8_t EXPLR_RDF_FIR_MAINLINE_AUE                                = 13  ;
static const uint8_t EXPLR_RDF_FIR_MAINLINE_UE                                 = 14  ;
static const uint8_t EXPLR_RDF_FIR_MAINLINE_RCD                                = 15  ;
static const uint8_t EXPLR_RDF_FIR_MAINLINE_IAUE                               = 16  ;
static const uint8_t EXPLR_RDF_FIR_MAINLINE_IUE                                = 17  ;
static const uint8_t EXPLR_RDF_FIR_MAINLINE_IRCD                               = 18  ;
static const uint8_t EXPLR_RDF_FIR_MAINLINE_IMPE                               = 19  ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7                 = 20  ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7_LEN             = 8   ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_NCE                             = 28  ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_TCE                             = 29  ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_SCE                             = 30  ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_MCE                             = 31  ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_SUE                             = 32  ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_AUE                             = 33  ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_UE                              = 34  ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_RCD                             = 35  ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_IAUE                            = 36  ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_IUE                             = 37  ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_IRCD                            = 38  ;
static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_IMPE                            = 39  ;
static const uint8_t EXPLR_RDF_FIR_RDDATA_VALID_ERROR                          = 40  ;
static const uint8_t EXPLR_RDF_FIR_SCOM_PARITY_CLASS_STATUS                    = 41  ;
static const uint8_t EXPLR_RDF_FIR_SCOM_PARITY_CLASS_RECOVERABLE               = 42  ;
static const uint8_t EXPLR_RDF_FIR_SCOM_PARITY_CLASS_UNRECOVERABLE             = 43  ;
static const uint8_t EXPLR_RDF_FIR_ECC_CORRECTOR_INTERNAL_PARITY_ERROR         = 44  ;
static const uint8_t EXPLR_RDF_FIR_ECC_RBUF_CE_DW0                             = 45  ;
static const uint8_t EXPLR_RDF_FIR_ECC_RBUF_CE_DW1                             = 46  ;
static const uint8_t EXPLR_RDF_FIR_ECC_RBUF_UE_DW0                             = 47  ;
static const uint8_t EXPLR_RDF_FIR_ECC_RBUF_UE_DW1                             = 48  ;
static const uint8_t EXPLR_RDF_FIR_RESERVED_49_59                              = 49  ;
static const uint8_t EXPLR_RDF_FIR_RESERVED_49_59_LEN                          = 11  ;
static const uint8_t EXPLR_RDF_FIR_SCOM_PARITY_DEBUG_WAT                       = 60  ;
static const uint8_t EXPLR_RDF_FIR_RESERVED                                    = 61  ;
static const uint8_t EXPLR_RDF_FIR_INTERNAL_SCOM_ERROR                         = 62  ;
static const uint8_t EXPLR_RDF_FIR_INTERNAL_SCOM_ERROR_COPY                    = 63  ;

static const uint8_t EXPLR_RDF_FWMS0_MARK                                      = 0   ;
static const uint8_t EXPLR_RDF_FWMS0_MARK_LEN                                  = 8   ;
static const uint8_t EXPLR_RDF_FWMS0_TYPE                                      = 8   ;
static const uint8_t EXPLR_RDF_FWMS0_REGION                                    = 9   ;
static const uint8_t EXPLR_RDF_FWMS0_REGION_LEN                                = 3   ;
static const uint8_t EXPLR_RDF_FWMS0_ADDRESS                                   = 12  ;
static const uint8_t EXPLR_RDF_FWMS0_ADDRESS_LEN                               = 11  ;
static const uint8_t EXPLR_RDF_FWMS0_EXIT_1                                    = 23  ;

static const uint8_t EXPLR_RDF_FWMS1_MARK                                      = 0   ;
static const uint8_t EXPLR_RDF_FWMS1_MARK_LEN                                  = 8   ;
static const uint8_t EXPLR_RDF_FWMS1_TYPE                                      = 8   ;
static const uint8_t EXPLR_RDF_FWMS1_REGION                                    = 9   ;
static const uint8_t EXPLR_RDF_FWMS1_REGION_LEN                                = 3   ;
static const uint8_t EXPLR_RDF_FWMS1_ADDRESS                                   = 12  ;
static const uint8_t EXPLR_RDF_FWMS1_ADDRESS_LEN                               = 11  ;
static const uint8_t EXPLR_RDF_FWMS1_EXIT_1                                    = 23  ;

static const uint8_t EXPLR_RDF_FWMS2_MARK                                      = 0   ;
static const uint8_t EXPLR_RDF_FWMS2_MARK_LEN                                  = 8   ;
static const uint8_t EXPLR_RDF_FWMS2_TYPE                                      = 8   ;
static const uint8_t EXPLR_RDF_FWMS2_REGION                                    = 9   ;
static const uint8_t EXPLR_RDF_FWMS2_REGION_LEN                                = 3   ;
static const uint8_t EXPLR_RDF_FWMS2_ADDRESS                                   = 12  ;
static const uint8_t EXPLR_RDF_FWMS2_ADDRESS_LEN                               = 11  ;
static const uint8_t EXPLR_RDF_FWMS2_EXIT_1                                    = 23  ;

static const uint8_t EXPLR_RDF_FWMS3_MARK                                      = 0   ;
static const uint8_t EXPLR_RDF_FWMS3_MARK_LEN                                  = 8   ;
static const uint8_t EXPLR_RDF_FWMS3_TYPE                                      = 8   ;
static const uint8_t EXPLR_RDF_FWMS3_REGION                                    = 9   ;
static const uint8_t EXPLR_RDF_FWMS3_REGION_LEN                                = 3   ;
static const uint8_t EXPLR_RDF_FWMS3_ADDRESS                                   = 12  ;
static const uint8_t EXPLR_RDF_FWMS3_ADDRESS_LEN                               = 11  ;
static const uint8_t EXPLR_RDF_FWMS3_EXIT_1                                    = 23  ;

static const uint8_t EXPLR_RDF_FWMS4_MARK                                      = 0   ;
static const uint8_t EXPLR_RDF_FWMS4_MARK_LEN                                  = 8   ;
static const uint8_t EXPLR_RDF_FWMS4_TYPE                                      = 8   ;
static const uint8_t EXPLR_RDF_FWMS4_REGION                                    = 9   ;
static const uint8_t EXPLR_RDF_FWMS4_REGION_LEN                                = 3   ;
static const uint8_t EXPLR_RDF_FWMS4_ADDRESS                                   = 12  ;
static const uint8_t EXPLR_RDF_FWMS4_ADDRESS_LEN                               = 11  ;
static const uint8_t EXPLR_RDF_FWMS4_EXIT_1                                    = 23  ;

static const uint8_t EXPLR_RDF_FWMS5_MARK                                      = 0   ;
static const uint8_t EXPLR_RDF_FWMS5_MARK_LEN                                  = 8   ;
static const uint8_t EXPLR_RDF_FWMS5_TYPE                                      = 8   ;
static const uint8_t EXPLR_RDF_FWMS5_REGION                                    = 9   ;
static const uint8_t EXPLR_RDF_FWMS5_REGION_LEN                                = 3   ;
static const uint8_t EXPLR_RDF_FWMS5_ADDRESS                                   = 12  ;
static const uint8_t EXPLR_RDF_FWMS5_ADDRESS_LEN                               = 11  ;
static const uint8_t EXPLR_RDF_FWMS5_EXIT_1                                    = 23  ;

static const uint8_t EXPLR_RDF_FWMS6_MARK                                      = 0   ;
static const uint8_t EXPLR_RDF_FWMS6_MARK_LEN                                  = 8   ;
static const uint8_t EXPLR_RDF_FWMS6_TYPE                                      = 8   ;
static const uint8_t EXPLR_RDF_FWMS6_REGION                                    = 9   ;
static const uint8_t EXPLR_RDF_FWMS6_REGION_LEN                                = 3   ;
static const uint8_t EXPLR_RDF_FWMS6_ADDRESS                                   = 12  ;
static const uint8_t EXPLR_RDF_FWMS6_ADDRESS_LEN                               = 11  ;
static const uint8_t EXPLR_RDF_FWMS6_EXIT_1                                    = 23  ;

static const uint8_t EXPLR_RDF_FWMS7_MARK                                      = 0   ;
static const uint8_t EXPLR_RDF_FWMS7_MARK_LEN                                  = 8   ;
static const uint8_t EXPLR_RDF_FWMS7_TYPE                                      = 8   ;
static const uint8_t EXPLR_RDF_FWMS7_REGION                                    = 9   ;
static const uint8_t EXPLR_RDF_FWMS7_REGION_LEN                                = 3   ;
static const uint8_t EXPLR_RDF_FWMS7_ADDRESS                                   = 12  ;
static const uint8_t EXPLR_RDF_FWMS7_ADDRESS_LEN                               = 11  ;
static const uint8_t EXPLR_RDF_FWMS7_EXIT_1                                    = 23  ;

static const uint8_t EXPLR_RDF_HWMS0_CHIPMARK                                  = 0   ;
static const uint8_t EXPLR_RDF_HWMS0_CHIPMARK_LEN                              = 8   ;
static const uint8_t EXPLR_RDF_HWMS0_CONFIRMED                                 = 8   ;
static const uint8_t EXPLR_RDF_HWMS0_EXIT_1                                    = 9   ;

static const uint8_t EXPLR_RDF_HWMS1_CHIPMARK                                  = 0   ;
static const uint8_t EXPLR_RDF_HWMS1_CHIPMARK_LEN                              = 8   ;
static const uint8_t EXPLR_RDF_HWMS1_CONFIRMED                                 = 8   ;
static const uint8_t EXPLR_RDF_HWMS1_EXIT_1                                    = 9   ;

static const uint8_t EXPLR_RDF_HWMS2_CHIPMARK                                  = 0   ;
static const uint8_t EXPLR_RDF_HWMS2_CHIPMARK_LEN                              = 8   ;
static const uint8_t EXPLR_RDF_HWMS2_CONFIRMED                                 = 8   ;
static const uint8_t EXPLR_RDF_HWMS2_EXIT_1                                    = 9   ;

static const uint8_t EXPLR_RDF_HWMS3_CHIPMARK                                  = 0   ;
static const uint8_t EXPLR_RDF_HWMS3_CHIPMARK_LEN                              = 8   ;
static const uint8_t EXPLR_RDF_HWMS3_CONFIRMED                                 = 8   ;
static const uint8_t EXPLR_RDF_HWMS3_EXIT_1                                    = 9   ;

static const uint8_t EXPLR_RDF_HWMS4_CHIPMARK                                  = 0   ;
static const uint8_t EXPLR_RDF_HWMS4_CHIPMARK_LEN                              = 8   ;
static const uint8_t EXPLR_RDF_HWMS4_CONFIRMED                                 = 8   ;
static const uint8_t EXPLR_RDF_HWMS4_EXIT_1                                    = 9   ;

static const uint8_t EXPLR_RDF_HWMS5_CHIPMARK                                  = 0   ;
static const uint8_t EXPLR_RDF_HWMS5_CHIPMARK_LEN                              = 8   ;
static const uint8_t EXPLR_RDF_HWMS5_CONFIRMED                                 = 8   ;
static const uint8_t EXPLR_RDF_HWMS5_EXIT_1                                    = 9   ;

static const uint8_t EXPLR_RDF_HWMS6_CHIPMARK                                  = 0   ;
static const uint8_t EXPLR_RDF_HWMS6_CHIPMARK_LEN                              = 8   ;
static const uint8_t EXPLR_RDF_HWMS6_CONFIRMED                                 = 8   ;
static const uint8_t EXPLR_RDF_HWMS6_EXIT_1                                    = 9   ;

static const uint8_t EXPLR_RDF_HWMS7_CHIPMARK                                  = 0   ;
static const uint8_t EXPLR_RDF_HWMS7_CHIPMARK_LEN                              = 8   ;
static const uint8_t EXPLR_RDF_HWMS7_CONFIRMED                                 = 8   ;
static const uint8_t EXPLR_RDF_HWMS7_EXIT_1                                    = 9   ;

static const uint8_t EXPLR_RDF_MASK_FIR                                        = 0   ;
static const uint8_t EXPLR_RDF_MASK_FIR_LEN                                    = 64  ;

static const uint8_t EXPLR_RDF_MASK0_MSR_PE                                    = 12  ;
static const uint8_t EXPLR_RDF_MASK0_EICR_PE                                   = 13  ;
static const uint8_t EXPLR_RDF_MASK0_HWMSX_PE                                  = 16  ;
static const uint8_t EXPLR_RDF_MASK0_HWMSX_PE_LEN                              = 8   ;
static const uint8_t EXPLR_RDF_MASK0_FWMSX_PE                                  = 24  ;
static const uint8_t EXPLR_RDF_MASK0_FWMSX_PE_LEN                              = 8   ;
static const uint8_t EXPLR_RDF_MASK0_RSPAR_PE                                  = 32  ;
static const uint8_t EXPLR_RDF_MASK0_CTCR_PE                                   = 40  ;
static const uint8_t EXPLR_RDF_MASK0_AACR_PE                                   = 41  ;
static const uint8_t EXPLR_RDF_MASK0_MCBCM_PE                                  = 44  ;
static const uint8_t EXPLR_RDF_MASK0_RECR_PE                                   = 45  ;
static const uint8_t EXPLR_RDF_MASK0_DBGR_PE                                   = 46  ;
static const uint8_t EXPLR_RDF_MASK0_MASK0_PE                                  = 48  ;
static const uint8_t EXPLR_RDF_MASK0_MASK1_PE                                  = 49  ;
static const uint8_t EXPLR_RDF_MASK0_CGDR_PE                                   = 50  ;

static const uint8_t EXPLR_RDF_MASK1_ECC_CTL_AF_PERR                           = 0   ;
static const uint8_t EXPLR_RDF_MASK1_ECC_CTL_TCHN_PERR                         = 1   ;
static const uint8_t EXPLR_RDF_MASK1_ECC_CTL_CMPMODE_ERR                       = 2   ;
static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_PCX_PERR                         = 3   ;
static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_SYND_PERR                        = 4   ;
static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_2SYM_PERR                        = 5   ;
static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_CPLX_PERR                        = 6   ;
static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_EP2_PERR                         = 7   ;
static const uint8_t EXPLR_RDF_MASK1_READ_ECC_DATAPATH_PARITY_ERROR            = 8   ;
static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_CMX_PERR                         = 9   ;
static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_VP1_PERR                         = 10  ;
static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_VP2_PERR                         = 11  ;
static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_SYG_PERR                         = 12  ;
static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_EF1_PERR                         = 13  ;
static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_MK3_PERR                         = 14  ;
static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_E1A_PERR                         = 15  ;
static const uint8_t EXPLR_RDF_MASK1_UNEXPECTED_RDDATA_VALID                   = 16  ;
static const uint8_t EXPLR_RDF_MASK1_MISSING_RDDATA_VALID                      = 17  ;

static const uint8_t EXPLR_RDF_MCBCM_MCBIST_HALF_COMPARE_MASK                  = 0   ;
static const uint8_t EXPLR_RDF_MCBCM_MCBIST_HALF_COMPARE_MASK_LEN              = 40  ;
static const uint8_t EXPLR_RDF_MCBCM_MCBIST_MASK_COVERAGE_SELECTOR             = 40  ;
static const uint8_t EXPLR_RDF_MCBCM_MCBIST_TRAP_NONSTOP                       = 41  ;
static const uint8_t EXPLR_RDF_MCBCM_MCBIST_TRAP_CE_ENABLE                     = 42  ;
static const uint8_t EXPLR_RDF_MCBCM_MCBIST_TRAP_MPE_ENABLE                    = 43  ;
static const uint8_t EXPLR_RDF_MCBCM_MCBIST_TRAP_UE_ENABLE                     = 44  ;

static const uint8_t EXPLR_RDF_MSR_CHIPMARK                                    = 8   ;
static const uint8_t EXPLR_RDF_MSR_CHIPMARK_LEN                                = 8   ;
static const uint8_t EXPLR_RDF_MSR_RANK                                        = 16  ;
static const uint8_t EXPLR_RDF_MSR_RANK_LEN                                    = 3   ;

static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT   = 0   ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT         = 1   ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_MARK_STORE_WRITE           = 2   ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_UE_RETRY                   = 3   ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ITAG_METADATA_ENABLE               = 4   ;
static const uint8_t EXPLR_RDF_RECR_DISABLE_RCD_CHECK                          = 5   ;
static const uint8_t EXPLR_RDF_RECR_DISABLE_RDDATA_VALID_CHECK                 = 6   ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_UTC_EXIT_INCREASE          = 8   ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_EXIT_OVERRIDE                      = 9   ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_EXIT_OVERRIDE_LEN                  = 2   ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_HWMARK_EXIT1                       = 11  ;
static const uint8_t EXPLR_RDF_RECR_CAPPTAG_BYPASS_BIT_ENABLE                  = 14  ;
static const uint8_t EXPLR_RDF_RECR_CAPPTAG_RETRY_BIT_ENABLE                   = 15  ;
static const uint8_t EXPLR_RDF_RECR_CAPPTAG_BYPASS_BIT_SELECT                  = 16  ;
static const uint8_t EXPLR_RDF_RECR_CAPPTAG_BYPASS_BIT_SELECT_LEN              = 4   ;
static const uint8_t EXPLR_RDF_RECR_CAPPTAG_RETRY_BIT_SELECT                   = 20  ;
static const uint8_t EXPLR_RDF_RECR_CAPPTAG_RETRY_BIT_SELECT_LEN               = 4   ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_MPE_CONFIRM                = 25  ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW             = 26  ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ENABLE_TCE_CORRECTION              = 27  ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ENABLE_CHIPMARKED_SCE_NCE          = 28  ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_USE_ADDRESS_HASH                   = 29  ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION                     = 30  ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION_LEN                 = 2   ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING    = 32  ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_MAINT_NO_RETRY_UE                  = 33  ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_MAINT_NO_RETRY_MPE                 = 34  ;
static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ENABLE_BYPASS_MARK_PLACE           = 39  ;
static const uint8_t EXPLR_RDF_RECR_CFG_MAINT_USE_TIMERS                       = 40  ;
static const uint8_t EXPLR_RDF_RECR_HWMS_RANK_SELECT                           = 41  ;
static const uint8_t EXPLR_RDF_RECR_HWMS_RANK_SELECT_LEN                       = 6   ;

static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R0_LEFT                      = 0   ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R0_LEFT_LEN                  = 5   ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R0_RIGHT                     = 5   ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R0_RIGHT_LEN                 = 5   ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R1_LEFT                      = 10  ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R1_LEFT_LEN                  = 5   ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R1_RIGHT                     = 15  ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R1_RIGHT_LEN                 = 5   ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R2_LEFT                      = 20  ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R2_LEFT_LEN                  = 5   ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R2_RIGHT                     = 25  ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R2_RIGHT_LEN                 = 5   ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R3_LEFT                      = 30  ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R3_LEFT_LEN                  = 5   ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R3_RIGHT                     = 35  ;
static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R3_RIGHT_LEN                 = 5   ;

static const uint8_t EXPLR_RDF_WOF_FIR                                         = 0   ;
static const uint8_t EXPLR_RDF_WOF_FIR_LEN                                     = 64  ;

static const uint8_t EXPLR_SRQ_ERR_HOLD_LAT_FIR_MASK_PAR                       = 0   ;
static const uint8_t EXPLR_SRQ_ERR_HOLD_LAT_FIR_ACTION0_PAR                    = 1   ;
static const uint8_t EXPLR_SRQ_ERR_HOLD_LAT_FIR_ACTION1_PAR                    = 2   ;

static const uint8_t EXPLR_SRQ_ERR_MASK_LAT_FIR_PAR                            = 0   ;
static const uint8_t EXPLR_SRQ_ERR_MASK_LAT_FIR_ACTION0_PAR                    = 1   ;
static const uint8_t EXPLR_SRQ_ERR_MASK_LAT_FIR_ACTION1_PAR                    = 2   ;

static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_ENABLE                     = 0   ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT   = 1   ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN = 2   ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_PER_BANK_REFRESH                   = 3   ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_RESERVED_4                             = 4   ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD         = 5   ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD_LEN     = 3   ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_INTERVAL                   = 8   ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_INTERVAL_LEN               = 11  ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL             = 19  ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL_LEN         = 11  ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_TRFC                               = 30  ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_TRFC_LEN                           = 10  ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFR_TSV_STACK                     = 40  ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFR_TSV_STACK_LEN                 = 10  ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFR_CHECK_INTERVAL                = 50  ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFR_CHECK_INTERVAL_LEN            = 11  ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_TRFC_STACK_GATE_ALL_REF            = 61  ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_RESERVED_62_63                         = 62  ;
static const uint8_t EXPLR_SRQ_MBAREF0Q_RESERVED_62_63_LEN                     = 2   ;

static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_STATIC_IDLE_DLY                    = 0   ;
static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_STATIC_IDLE_DLY_LEN                = 4   ;
static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_LP_SUB_CNT                         = 4   ;
static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_LP_SUB_CNT_LEN                     = 2   ;
static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_REFRESH_HP_RANK_BLOCK_ENABLE       = 6   ;
static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_HP_WR_GATE_LP_REF_DIS              = 7   ;
static const uint8_t EXPLR_SRQ_MBAREFAQ_RESERVED_8_9                           = 8   ;
static const uint8_t EXPLR_SRQ_MBAREFAQ_RESERVED_8_9_LEN                       = 2   ;
static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY                 = 10  ;
static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY_LEN             = 6   ;
static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_TSTAB                              = 16  ;
static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_TSTAB_LEN                          = 13  ;
static const uint8_t EXPLR_SRQ_MBAREFAQ_RESERVED_29_31                         = 29  ;
static const uint8_t EXPLR_SRQ_MBAREFAQ_RESERVED_29_31_LEN                     = 3   ;

static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_LP_CTRL_ENABLE                     = 0   ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_LP_DATA_ENABLE                     = 1   ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE             = 2   ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_MAX_DOMAINS                    = 3   ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN                = 3   ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AVAIL                          = 6   ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AVAIL_LEN                      = 5   ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PDN_PUP                            = 11  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PDN_PUP_LEN                        = 5   ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_PDN                            = 16  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_PDN_LEN                        = 5   ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_QUAD_RANK_ENC                      = 21  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE        = 22  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME          = 23  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN      = 10  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE     = 33  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME       = 34  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN   = 8   ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_CONC_LP_DATA_DISABLE               = 42  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT  = 43  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN                = 44  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN_LEN            = 3   ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_ALL_WRITES_PENDING             = 47  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_ALWAYS_WAIT_ACT_TIME               = 48  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_TLP_RESP                           = 49  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_TLP_RESP_LEN                       = 5   ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_TLP_WAKEUP                         = 54  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_TLP_WAKEUP_LEN                     = 5   ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_CONC_CCS_STR_EN                    = 59  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_RESERVED_60_63                         = 60  ;
static const uint8_t EXPLR_SRQ_MBARPC0Q_RESERVED_60_63_LEN                     = 4   ;

static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_STR_ENABLE                         = 0   ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_DIS_CLK_IN_STR                     = 1   ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_ENTER_STR_TIME                     = 2   ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_ENTER_STR_TIME_LEN                 = 10  ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKESR                             = 12  ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKESR_LEN                         = 5   ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKSRE                             = 17  ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKSRE_LEN                         = 5   ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKSRX                             = 22  ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKSRX_LEN                         = 5   ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TXSDLL                             = 27  ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TXSDLL_LEN                         = 11  ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TRFC_COUNTER_DIS                   = 38  ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TRFC_COUNTER_DIS_LEN               = 8   ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL              = 46  ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL_LEN          = 11  ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL              = 57  ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL_LEN          = 4   ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_OCC_DEADMAN_TB_SEL                 = 61  ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_FORCE_STR                          = 62  ;
static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_EPOW_DISABLE                       = 63  ;

static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_ENABLE                    = 0   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL0                      = 1   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL0_LEN                  = 3   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL1                      = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL1_LEN                  = 3   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL2                      = 7   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL2_LEN                  = 3   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL3                      = 10  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL3_LEN                  = 3   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL4                      = 13  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL4_LEN                  = 3   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL5                      = 16  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL5_LEN                  = 3   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL6                      = 19  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL6_LEN                  = 3   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL7                      = 22  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL7_LEN                  = 3   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP0_FLIP               = 25  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP1_FLIP               = 26  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP2_FLIP               = 27  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP3_FLIP               = 28  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP4_FLIP               = 29  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP5_FLIP               = 30  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP6_FLIP               = 31  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP7_FLIP               = 32  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_RESERVED_33_47                        = 33  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_RESERVED_33_47_LEN                    = 15  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT                   = 48  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT_LEN               = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT                   = 52  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT_LEN               = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_REF_GT                   = 56  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_REF_GT_LEN               = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_RESERVED_60_63                        = 60  ;
static const uint8_t EXPLR_SRQ_MBA_DBG0Q_RESERVED_60_63_LEN                    = 4   ;

static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP            = 0   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP_LEN        = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP            = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP_LEN        = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FP_DIS                        = 8   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FP_DIS_LEN                    = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_DIS_RD_PG                     = 12  ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_DIS_RD_PG_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_DIS_WR_PG                     = 16  ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_DIS_WR_PG_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_PUP_ALL                       = 20  ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_PUP_ALL_LEN                   = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_EXIT_STR                      = 24  ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_EXIT_STR_LEN                  = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_HP                        = 28  ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_HP_LEN                    = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_SYNC                      = 32  ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_SYNC_LEN                  = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_SAFE                      = 36  ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_SAFE_LEN                  = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_RESERVED_40_43                        = 40  ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_RESERVED_40_43_LEN                    = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_MCBIST_GT                     = 44  ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_MCBIST_GT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_NCF_RM_INVALID_CMD            = 48  ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_NCF_RM_INVALID_CMD_LEN        = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_SET_FIR                       = 52  ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_SET_FIR_LEN                   = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_EMER_TH                       = 56  ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_EMER_TH_LEN                   = 4   ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_START_RECOVERY                = 60  ;
static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_START_RECOVERY_LEN            = 4   ;

static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RODT_START_DLY                    = 0   ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RODT_START_DLY_LEN                = 6   ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RODT_END_DLY                      = 6   ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RODT_END_DLY_LEN                  = 6   ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WODT_START_DLY                    = 12  ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WODT_START_DLY_LEN                = 6   ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WODT_END_DLY                      = 18  ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WODT_END_DLY_LEN                  = 6   ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY                        = 24  ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY_LEN                    = 6   ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDATA_DLY                        = 30  ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDATA_DLY_LEN                    = 6   ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY                         = 36  ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY_LEN                     = 6   ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDCSLAT_DLY                       = 42  ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDCSLAT_DLY_LEN                   = 5   ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDDATA_EN_DLY                     = 47  ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDDATA_EN_DLY_LEN                 = 5   ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRCSLAT_DLY                       = 52  ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRCSLAT_DLY_LEN                   = 5   ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDATA_EN_DLY                     = 57  ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDATA_EN_DLY_LEN                 = 5   ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_RESERVED_62_63                        = 62  ;
static const uint8_t EXPLR_SRQ_MBA_DSM0Q_RESERVED_62_63_LEN                    = 2   ;

static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_PC_PCFSM_1HOT                   = 0   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_STRFSM_1HOT                     = 1   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_FARB_RECVFSM_1HOT               = 2   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_PC_PE                           = 3   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_RRQ_PE                          = 4   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_WRQ_PE                          = 5   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_DSM_PE                          = 6   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_TMR_PE                          = 7   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_FARB_PE                         = 8   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_WRQ_HANG                        = 9   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_RRQ_HANG                        = 10  ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_FARB_CMD_PE_HOLD_OUT            = 11  ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_DSM_CMD_PE_HOLD_OUT             = 12  ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_UE                          = 13  ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_UE_LEN                      = 2   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_TBD                         = 15  ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_TBD_LEN                     = 2   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_MCB_LOGIC_ERROR             = 17  ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_MCB_LOGIC_ERROR_LEN         = 5   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_LOGIC_ERROR                 = 22  ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_LOGIC_ERROR_LEN             = 15  ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_MCB_PARITY_ERROR            = 37  ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_MCB_PARITY_ERROR_LEN        = 5   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_PARITY_ERROR                = 42  ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_PARITY_ERROR_LEN            = 11  ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_CE                          = 53  ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_CE_LEN                      = 4   ;

static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_MASK_ERRMASK                    = 0   ;
static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_MASK_ERRMASK_LEN                = 57  ;

static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MISR_BLOCK                       = 0   ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MISR_BLOCK_LEN                   = 16  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MISR_FEEDBACK_ENABLE             = 16  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_2N_ADDR                          = 17  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_DDP_ADDR_MODE                    = 18  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_PLANAR_ADDR_MODE                 = 19  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_ACT_SAME_RANK_HOLD_TIME          = 20  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_ACT_SAME_RANK_HOLD_TIME_LEN      = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW               = 24  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW_LEN           = 7   ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW              = 31  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW_LEN          = 7   ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_PARITY_AFTER_CMD                 = 38  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_WEN            = 39  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_ADDR5          = 40  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_BW_WINDOW_SIZE                   = 41  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_BW_WINDOW_SIZE_LEN               = 2   ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_PARITY_DETECT_TIME               = 43  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_PARITY_DETECT_TIME_LEN           = 5   ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME              = 48  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME_LEN          = 6   ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY             = 54  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_WAIT_FOR_INIT_COMPLETE           = 55  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_FARB_CLOSE_ALL_PAGES             = 56  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_PORT_FAIL_DISABLE                = 57  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_RESERVED_58                          = 58  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_CONSTANT       = 59  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_FINISH_WR_BEFORE_RD              = 60  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_OPT_RD_SIZE                      = 61  ;
static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_OPT_RD_SIZE_LEN                  = 3   ;

static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S0_CID                     = 0   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S0_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S1_CID                     = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S1_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S2_CID                     = 6   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S2_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S3_CID                     = 9   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S3_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S4_CID                     = 12  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S4_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S5_CID                     = 15  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S5_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S6_CID                     = 18  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S6_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S7_CID                     = 21  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S7_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S0_CID                     = 24  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S0_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S1_CID                     = 27  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S1_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S2_CID                     = 30  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S2_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S3_CID                     = 33  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S3_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S4_CID                     = 36  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S4_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S5_CID                     = 39  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S5_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S6_CID                     = 42  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S6_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S7_CID                     = 45  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S7_CID_LEN                 = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_DIS_SMDR                         = 48  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_DDR4_PARITY_ON_CID_DIS           = 49  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_READ_2CYC_PREAMBLE_EN            = 50  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_WRITE_2CYC_PREAMBLE_EN           = 51  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RDCSGAP_DLY                      = 52  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RDCSGAP_DLY_LEN                  = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_WRCSGAP_DLY                      = 55  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_WRCSGAP_DLY_LEN                  = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RSV0                             = 58  ;
static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RSV0_LEN                         = 6   ;

static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK0_RD_ODT                     = 0   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK0_RD_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK1_RD_ODT                     = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK1_RD_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK2_RD_ODT                     = 8   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK2_RD_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK3_RD_ODT                     = 12  ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK3_RD_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK4_RD_ODT                     = 16  ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK4_RD_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK5_RD_ODT                     = 20  ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK5_RD_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK6_RD_ODT                     = 24  ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK6_RD_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK7_RD_ODT                     = 28  ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK7_RD_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK0_WR_ODT                     = 32  ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK0_WR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK1_WR_ODT                     = 36  ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK1_WR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK2_WR_ODT                     = 40  ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK2_WR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK3_WR_ODT                     = 44  ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK3_WR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK4_WR_ODT                     = 48  ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK4_WR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK5_WR_ODT                     = 52  ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK5_WR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK6_WR_ODT                     = 56  ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK6_WR_ODT_LEN                 = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK7_WR_ODT                     = 60  ;
static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK7_WR_ODT_LEN                 = 4   ;

static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_SLOT                    = 0   ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_SLOT_LEN                = 15  ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_PORT                    = 15  ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_PORT_LEN                = 16  ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_M                             = 31  ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_M_LEN                         = 14  ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_RAS_WEIGHT                    = 45  ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_RAS_WEIGHT_LEN                = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_CAS_WEIGHT                    = 48  ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_CAS_WEIGHT_LEN                = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_RESERVED_51                          = 51  ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_RESERVED_52                          = 52  ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_CHANGE_AFTER_SYNC             = 53  ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_RESERVED_54_63                       = 54  ;
static const uint8_t EXPLR_SRQ_MBA_FARB3Q_RESERVED_54_63_LEN                   = 10  ;

static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_NOISE_WAIT_TIME                  = 0   ;
static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_NOISE_WAIT_TIME_LEN              = 16  ;
static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME              = 16  ;
static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME_LEN          = 6   ;
static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_SIM_FAST_NOISE_WINDOW            = 22  ;
static const uint8_t EXPLR_SRQ_MBA_FARB4Q_RESERVED_23_26                       = 23  ;
static const uint8_t EXPLR_SRQ_MBA_FARB4Q_RESERVED_23_26_LEN                   = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB4Q_EMERGENCY_N                          = 27  ;
static const uint8_t EXPLR_SRQ_MBA_FARB4Q_EMERGENCY_N_LEN                      = 15  ;
static const uint8_t EXPLR_SRQ_MBA_FARB4Q_EMERGENCY_M                          = 42  ;
static const uint8_t EXPLR_SRQ_MBA_FARB4Q_EMERGENCY_M_LEN                      = 14  ;
static const uint8_t EXPLR_SRQ_MBA_FARB4Q_RESERVED_56_63                       = 56  ;
static const uint8_t EXPLR_SRQ_MBA_FARB4Q_RESERVED_56_63_LEN                   = 8   ;

static const uint8_t EXPLR_SRQ_MBA_FARB5Q_RESERVED_0_3                         = 0   ;
static const uint8_t EXPLR_SRQ_MBA_FARB5Q_RESERVED_0_3_LEN                     = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB5Q_CFG_DDR_RESETN                       = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL                 = 5   ;
static const uint8_t EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_INST_RESET_ENABLE            = 6   ;
static const uint8_t EXPLR_SRQ_MBA_FARB5Q_RESERVED_7_15                        = 7   ;
static const uint8_t EXPLR_SRQ_MBA_FARB5Q_RESERVED_7_15_LEN                    = 9   ;

static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_BW_SNAPSHOT                      = 0   ;
static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN                  = 11  ;
static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_CKE_PUP_STATE                    = 11  ;
static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_CKE_PUP_STATE_LEN                = 4   ;
static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_STR_STATE                        = 15  ;
static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_RRQ_DEPTH                        = 16  ;
static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_RRQ_DEPTH_LEN                    = 5   ;
static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_WRQ_DEPTH                        = 21  ;
static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_WRQ_DEPTH_LEN                    = 5   ;
static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_RCD_PARITY_DLY                   = 26  ;
static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_RCD_PARITY_DLY_LEN               = 5   ;
static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_EVENT                            = 31  ;

static const uint8_t EXPLR_SRQ_MBA_FARB7Q_EMER_THROTTLE_IP                     = 0   ;

static const uint8_t EXPLR_SRQ_MBA_FARB8Q_SAFE_REFRESH_MODE                    = 0   ;

static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_ENABLE                = 0   ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_INTERVAL_TB           = 1   ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_INTERVAL_TB_LEN       = 2   ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_INTERVAL              = 3   ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_INTERVAL_LEN          = 9   ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_RESERVED_12                          = 12  ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_RUN_LENGTH            = 13  ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_RUN_LENGTH_LEN        = 8   ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_RUN_LENGTH_TB         = 21  ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_RUN_LENGTH_TB_LEN     = 2   ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_RESERVED_23_31                       = 23  ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_RESERVED_23_31_LEN                   = 9   ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_ENABLE                = 32  ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_INTERVAL_TB           = 33  ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_INTERVAL_TB_LEN       = 2   ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_INTERVAL              = 35  ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_INTERVAL_LEN          = 9   ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_FIXED_RUN_LENGTH_EN   = 44  ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_RUN_LENGTH            = 45  ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_RUN_LENGTH_LEN        = 10  ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_CTRLUPD_MIN           = 55  ;
static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_CTRLUPD_MIN_LEN       = 9   ;

static const uint8_t EXPLR_SRQ_MBA_PMU0Q_READ_COUNT                            = 0   ;
static const uint8_t EXPLR_SRQ_MBA_PMU0Q_READ_COUNT_LEN                        = 32  ;
static const uint8_t EXPLR_SRQ_MBA_PMU0Q_WRITE_COUNT                           = 32  ;
static const uint8_t EXPLR_SRQ_MBA_PMU0Q_WRITE_COUNT_LEN                       = 32  ;

static const uint8_t EXPLR_SRQ_MBA_PMU1Q_ACTIVATE_COUNT                        = 0   ;
static const uint8_t EXPLR_SRQ_MBA_PMU1Q_ACTIVATE_COUNT_LEN                    = 32  ;
static const uint8_t EXPLR_SRQ_MBA_PMU1Q_PU_COUNTS                             = 32  ;
static const uint8_t EXPLR_SRQ_MBA_PMU1Q_PU_COUNTS_LEN                         = 32  ;

static const uint8_t EXPLR_SRQ_MBA_PMU2Q_FRAME_COUNT                           = 0   ;
static const uint8_t EXPLR_SRQ_MBA_PMU2Q_FRAME_COUNT_LEN                       = 32  ;
static const uint8_t EXPLR_SRQ_MBA_PMU2Q_STR_EXIT_COUNT                        = 32  ;
static const uint8_t EXPLR_SRQ_MBA_PMU2Q_STR_EXIT_COUNT_LEN                    = 8   ;

static const uint8_t EXPLR_SRQ_MBA_PMU3Q_LOW_IDLE_THRESHOLD                    = 0   ;
static const uint8_t EXPLR_SRQ_MBA_PMU3Q_LOW_IDLE_THRESHOLD_LEN                = 16  ;
static const uint8_t EXPLR_SRQ_MBA_PMU3Q_MED_IDLE_THRESHOLD                    = 16  ;
static const uint8_t EXPLR_SRQ_MBA_PMU3Q_MED_IDLE_THRESHOLD_LEN                = 16  ;
static const uint8_t EXPLR_SRQ_MBA_PMU3Q_HIGH_IDLE_THRESHOLD                   = 32  ;
static const uint8_t EXPLR_SRQ_MBA_PMU3Q_HIGH_IDLE_THRESHOLD_LEN               = 32  ;

static const uint8_t EXPLR_SRQ_MBA_PMU4Q_BASE_IDLE_COUNT                       = 0   ;
static const uint8_t EXPLR_SRQ_MBA_PMU4Q_BASE_IDLE_COUNT_LEN                   = 32  ;
static const uint8_t EXPLR_SRQ_MBA_PMU4Q_LOW_IDLE_COUNT                        = 32  ;
static const uint8_t EXPLR_SRQ_MBA_PMU4Q_LOW_IDLE_COUNT_LEN                    = 32  ;

static const uint8_t EXPLR_SRQ_MBA_PMU5Q_MED_IDLE_COUNT                        = 0   ;
static const uint8_t EXPLR_SRQ_MBA_PMU5Q_MED_IDLE_COUNT_LEN                    = 32  ;
static const uint8_t EXPLR_SRQ_MBA_PMU5Q_HIGH_IDLE_COUNT                       = 32  ;
static const uint8_t EXPLR_SRQ_MBA_PMU5Q_HIGH_IDLE_COUNT_LEN                   = 32  ;

static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT0_COUNTER                        = 0   ;
static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT0_COUNTER_LEN                    = 16  ;
static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT1_COUNTER                        = 16  ;
static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT1_COUNTER_LEN                    = 16  ;
static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT2_COUNTER                        = 32  ;
static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT2_COUNTER_LEN                    = 16  ;
static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT3_COUNTER                        = 48  ;
static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT3_COUNTER_LEN                    = 16  ;

static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT0_SELECT                     = 0   ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT0_SELECT_LEN                 = 6   ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT1_SELECT                     = 6   ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT1_SELECT_LEN                 = 6   ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT2_SELECT                     = 12  ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT2_SELECT_LEN                 = 6   ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT3_SELECT                     = 18  ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT3_SELECT_LEN                 = 6   ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C0                      = 24  ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C0_LEN                  = 2   ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C1                      = 26  ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C1_LEN                  = 2   ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C2                      = 28  ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C2_LEN                  = 2   ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C3                      = 30  ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C3_LEN                  = 2   ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CASCADE                               = 32  ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CASCADE_LEN                           = 3   ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_FREEZE                                = 35  ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PMU_START_RESET                   = 36  ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PMU_START_NO_RESET                = 37  ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PMU_STOP                          = 38  ;
static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_RESET_PMU6_WHEN_READ              = 39  ;

static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_TYPE                         = 0   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_TYPE_LEN                     = 2   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_MRANK_MATCH_EN               = 2   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_SRANK_MATCH_EN               = 3   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BG_MATCH_EN                  = 4   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BANK_MATCH_EN                = 5   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_MRANK                        = 6   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_MRANK_LEN                    = 3   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_SRANK                        = 9   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_SRANK_LEN                    = 3   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BG                           = 12  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BG_LEN                       = 2   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BANK                         = 14  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BANK_LEN                     = 3   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_TYPE                         = 17  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_TYPE_LEN                     = 2   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_MRANK_MATCH_EN               = 19  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_SRANK_MATCH_EN               = 20  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BG_MATCH_EN                  = 21  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BANK_MATCH_EN                = 22  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_MRANK                        = 23  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_MRANK_LEN                    = 3   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_SRANK                        = 26  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_SRANK_LEN                    = 3   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BG                           = 29  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BG_LEN                       = 2   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BANK                         = 31  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BANK_LEN                     = 3   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_TYPE                         = 34  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_TYPE_LEN                     = 2   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_MRANK_MATCH_EN               = 36  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_SRANK_MATCH_EN               = 37  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BG_MATCH_EN                  = 38  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BANK_MATCH_EN                = 39  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_MRANK                        = 40  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_MRANK_LEN                    = 3   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_SRANK                        = 43  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_SRANK_LEN                    = 3   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BG                           = 46  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BG_LEN                       = 2   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BANK                         = 48  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BANK_LEN                     = 3   ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_RESERVED_51_63                        = 51  ;
static const uint8_t EXPLR_SRQ_MBA_PMU8Q_RESERVED_51_63_LEN                    = 13  ;

static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT                    = 0   ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT_LEN                = 6   ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_FIFO_MODE                     = 6   ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_SINGLE_THREAD_MODE            = 7   ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_RESERVED_8_10                         = 8   ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_RESERVED_8_10_LEN                     = 3   ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_DISABLE_RD_PG_MODE                = 11  ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_DISABLE_FAST_ACT                  = 12  ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR                  = 13  ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR_LEN              = 11  ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT             = 24  ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT_LEN         = 6   ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_SRQ_RRQ_DBG_SEL                   = 30  ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_SRQ_RRQ_DBG_SEL_LEN               = 4   ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_RESERVED_34_56                        = 34  ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_RESERVED_34_56_LEN                    = 23  ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING         = 57  ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING_LEN     = 4   ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_DISABLE_FAST_ACT_FIFO             = 61  ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_ENTRY0_ENABLE                 = 62  ;
static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_CRIT_OW_FIRST_EN                  = 63  ;

static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_SYNC_REF_EN                       = 0   ;
static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_SYNC_PC_EN                        = 1   ;
static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_SYNC_TIMEBASE_EN                  = 2   ;
static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_RESERVED_3_7                      = 3   ;
static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_RESERVED_3_7_LEN                  = 5   ;

static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRDM_DLY                              = 0   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRDM_DLY_LEN                          = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRSMSR_DLY                            = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRSMSR_DLY_LEN                        = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRSMDR_DLY                            = 8   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRSMDR_DLY_LEN                        = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RROP_DLY                              = 12  ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RROP_DLY_LEN                          = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWDM_DLY                              = 16  ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWDM_DLY_LEN                          = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWSMSR_DLY                            = 20  ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWSMSR_DLY_LEN                        = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWSMDR_DLY                            = 24  ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWSMDR_DLY_LEN                        = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWOP_DLY                              = 28  ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWOP_DLY_LEN                          = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWDM_DLY                              = 32  ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWDM_DLY_LEN                          = 5   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWSMSR_DLY                            = 37  ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWSMSR_DLY_LEN                        = 5   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWSMDR_DLY                            = 42  ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWSMDR_DLY_LEN                        = 5   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRDM_DLY                              = 47  ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRDM_DLY_LEN                          = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRSMSR_DLY                            = 51  ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRSMSR_DLY_LEN                        = 6   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRSMDR_DLY                            = 57  ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRSMDR_DLY_LEN                        = 6   ;
static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RESERVED_63                           = 63  ;

static const uint8_t EXPLR_SRQ_MBA_TMR1Q_RRSBG_DLY                             = 0   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_RRSBG_DLY_LEN                         = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_WRSBG_DLY                             = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_WRSBG_DLY_LEN                         = 6   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TFAW                              = 10  ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TFAW_LEN                          = 6   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRCD                              = 16  ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRCD_LEN                          = 5   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRP                               = 21  ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRP_LEN                           = 5   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRAS                              = 26  ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRAS_LEN                          = 6   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_SRQ_TMR_DBG_SEL                   = 32  ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_SRQ_TMR_DBG_SEL_LEN               = 5   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_RESERVED_37_40                        = 37  ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_RESERVED_37_40_LEN                    = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_WR2PRE                            = 41  ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_WR2PRE_LEN                        = 7   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_RD2PRE                            = 48  ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_RD2PRE_LEN                        = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_TRRD                                  = 52  ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_TRRD_LEN                              = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_TRRD_SBG                              = 56  ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_TRRD_SBG_LEN                          = 4   ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY              = 60  ;
static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY_LEN          = 4   ;

static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS                 = 0   ;
static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS_LEN             = 20  ;
static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS           = 20  ;
static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN       = 12  ;
static const uint8_t EXPLR_SRQ_MBA_TMR2Q_RESERVED_32_63                        = 32  ;
static const uint8_t EXPLR_SRQ_MBA_TMR2Q_RESERVED_32_63_LEN                    = 32  ;

static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRITE_HW_MARK                     = 0   ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRITE_HW_MARK_LEN                 = 5   ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_FIFO_MODE                     = 5   ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_DISABLE_WR_PG_MODE                = 6   ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY                 = 7   ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY_LEN             = 12  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_FLUSH_WR_RANK                 = 19  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ENABLE_NON_HP_WR              = 20  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR        = 21  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN    = 12  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRITE_LW_MARK                     = 33  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRITE_LW_MARK_LEN                 = 5   ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT                    = 38  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT_LEN                = 6   ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_SINGLE_THREAD_MODE            = 44  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD                 = 45  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD_LEN             = 8   ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_SKIP_RRQ_ENTRIES_DIS          = 53  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_RESERVED_54                           = 54  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING        = 55  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN    = 4   ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ALLOW_NEW_PAGE_COMMIT         = 59  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_SRQ_WRQ_DBG_SEL                   = 60  ;
static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_SRQ_WRQ_DBG_SEL_LEN               = 4   ;

static const uint8_t EXPLR_SRQ_SRQCFG0_MODE_ECC_CHK_DIS                        = 0   ;
static const uint8_t EXPLR_SRQ_SRQCFG0_MODE_ECC_COR_DIS                        = 1   ;
static const uint8_t EXPLR_SRQ_SRQCFG0_RMW_RBUF_PTR_MASK                       = 2   ;
static const uint8_t EXPLR_SRQ_SRQCFG0_RMW_RBUF_PTR_MASK_LEN                   = 14  ;
static const uint8_t EXPLR_SRQ_SRQCFG0_MCB_PAUSE                               = 16  ;
static const uint8_t EXPLR_SRQ_SRQCFG0_MCB_CREDIT_UPDATE                       = 17  ;
static const uint8_t EXPLR_SRQ_SRQCFG0_MCB_CRD_INIT                            = 18  ;
static const uint8_t EXPLR_SRQ_SRQCFG0_MCB_CRD_INIT_LEN                        = 4   ;
static const uint8_t EXPLR_SRQ_SRQCFG0_TRACE_UPDATE                            = 22  ;
static const uint8_t EXPLR_SRQ_SRQCFG0_CLEAR                                   = 23  ;
static const uint8_t EXPLR_SRQ_SRQCFG0_HOLD_ACUM                               = 24  ;
static const uint8_t EXPLR_SRQ_SRQCFG0_ERR_INJ0                                = 25  ;
static const uint8_t EXPLR_SRQ_SRQCFG0_ERR_INJ1                                = 26  ;
static const uint8_t EXPLR_SRQ_SRQCFG0_TBD0                                    = 27  ;
static const uint8_t EXPLR_SRQ_SRQCFG0_NCF_CGT_DIS                             = 28  ;
static const uint8_t EXPLR_SRQ_SRQCFG0_NCF_CGT_DIS_LEN                         = 3   ;
static const uint8_t EXPLR_SRQ_SRQCFG0_NCF_DRAM_CMD_FLUSH_EN                   = 31  ;

static const uint8_t EXPLR_SRQ_SRQFIRQ_MBA_RECOVERABLE_ERROR                   = 0   ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_MBA_NONRECOVERABLE_ERROR                = 1   ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_REFRESH_OVERRUN                         = 2   ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_WAT_ERROR                               = 3   ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_RCD_PARITY_ERROR                        = 4   ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_MCB_LOGIC_ERROR                     = 5   ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_EMERGENCY_THROTTLE                      = 6   ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_MCB_PARITY_ERROR                    = 7   ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_DDR_MBA_EVENT_N                         = 8   ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_WRQ_RRQ_HANG_ERR                        = 9   ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_SM_1HOT_ERR                             = 10  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_REG_PARITY_ERROR                        = 11  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_CMD_PARITY_ERROR                        = 12  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_PORT_FAIL                               = 13  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_INFO_REG_PARITY_ERROR                   = 14  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_DEBUG_PARITY_ERROR                      = 15  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR0                              = 16  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR1                              = 17  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR2                              = 18  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR3                              = 19  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR4                              = 20  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR5                              = 21  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR6                              = 22  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR7                              = 23  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_UE                                  = 24  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_TBD_FREE                                = 25  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_LOGIC_ERROR                         = 26  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_PARITY_ERROR                        = 27  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_CORR_ERROR                          = 28  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_INTERNAL_SCOM_ERROR                     = 29  ;
static const uint8_t EXPLR_SRQ_SRQFIRQ_INTERNAL_SCOM_ERROR_COPY                = 30  ;

static const uint8_t EXPLR_SRQ_SRQFIRWOF_FIR_WOF                               = 0   ;
static const uint8_t EXPLR_SRQ_SRQFIRWOF_FIR_WOF_LEN                           = 31  ;

static const uint8_t EXPLR_SRQ_SRQFIR_ACTION0_FIR                              = 0   ;
static const uint8_t EXPLR_SRQ_SRQFIR_ACTION0_FIR_LEN                          = 31  ;

static const uint8_t EXPLR_SRQ_SRQFIR_ACTION1_FIR                              = 0   ;
static const uint8_t EXPLR_SRQ_SRQFIR_ACTION1_FIR_LEN                          = 31  ;

static const uint8_t EXPLR_SRQ_SRQFIR_MASK_MBA                                 = 0   ;
static const uint8_t EXPLR_SRQ_SRQFIR_MASK_MBA_LEN                             = 31  ;

static const uint8_t EXPLR_SRQ_SRQTRAP0_DEBUG_BUS                              = 0   ;
static const uint8_t EXPLR_SRQ_SRQTRAP0_DEBUG_BUS_LEN                          = 64  ;

static const uint8_t EXPLR_SRQ_SRQTRAP1_DEBUG_BUS                              = 0   ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_DEBUG_BUS_LEN                          = 24  ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_SYNDROME                           = 24  ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_SYNDROME_LEN                       = 8   ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_SYNDROME                        = 32  ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_SYNDROME_LEN                    = 8   ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_INVALID_CMD_CODE                   = 40  ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_INVALID_CMD_CODE_LEN               = 4   ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_INVALID_CMD_CODE                = 44  ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_INVALID_CMD_CODE_LEN            = 4   ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_MCB_CREDITS                            = 48  ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_MCB_CREDITS_LEN                        = 4   ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_FSM_ENCODE                         = 52  ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_FSM_ENCODE_LEN                     = 4   ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_FSM_ENCODE                      = 56  ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_FSM_ENCODE_LEN                  = 3   ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_MCB_STATUS                             = 59  ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_MCB_STATUS_LEN                         = 2   ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_TBD                                    = 61  ;
static const uint8_t EXPLR_SRQ_SRQTRAP1_TBD_LEN                                = 3   ;

static const uint8_t EXPLR_TLXT_ERR_HOLD_LAT_FIR_MASK_PAR                      = 0   ;
static const uint8_t EXPLR_TLXT_ERR_HOLD_LAT_FIR_ACTION0_PAR                   = 1   ;
static const uint8_t EXPLR_TLXT_ERR_HOLD_LAT_FIR_ACTION1_PAR                   = 2   ;

static const uint8_t EXPLR_TLXT_ERR_MASK_LAT_FIR_PAR                           = 0   ;
static const uint8_t EXPLR_TLXT_ERR_MASK_LAT_FIR_ACTION0_PAR                   = 1   ;
static const uint8_t EXPLR_TLXT_ERR_MASK_LAT_FIR_ACTION1_PAR                   = 2   ;

static const uint8_t EXPLR_TLXT_TLXCFG0_TRAP_CLEAR                             = 0   ;
static const uint8_t EXPLR_TLXT_TLXCFG0_EARLY_WDONE_DISABLE                    = 1   ;
static const uint8_t EXPLR_TLXT_TLXCFG0_EARLY_WDONE_DISABLE_LEN                = 2   ;
static const uint8_t EXPLR_TLXT_TLXCFG0_TRAP_UPDATE                            = 3   ;
static const uint8_t EXPLR_TLXT_TLXCFG0_HOLD_ACUM                              = 4   ;
static const uint8_t EXPLR_TLXT_TLXCFG0_TBD                                    = 5   ;
static const uint8_t EXPLR_TLXT_TLXCFG0_TBD_LEN                                = 5   ;
static const uint8_t EXPLR_TLXT_TLXCFG0_DCP1_RETURN_PAUSE                      = 10  ;
static const uint8_t EXPLR_TLXT_TLXCFG0_DCP1_CREDIT_UPDATE                     = 11  ;
static const uint8_t EXPLR_TLXT_TLXCFG0_VC0_RETURN_PAUSE                       = 12  ;
static const uint8_t EXPLR_TLXT_TLXCFG0_VC0_CREDIT_UPDATE                      = 13  ;
static const uint8_t EXPLR_TLXT_TLXCFG0_VC1_RETURN_PAUSE                       = 14  ;
static const uint8_t EXPLR_TLXT_TLXCFG0_VC1_CREDIT_UPDATE                      = 15  ;
static const uint8_t EXPLR_TLXT_TLXCFG0_DCP1_INIT                              = 16  ;
static const uint8_t EXPLR_TLXT_TLXCFG0_DCP1_INIT_LEN                          = 16  ;
static const uint8_t EXPLR_TLXT_TLXCFG0_VC0_INIT                               = 32  ;
static const uint8_t EXPLR_TLXT_TLXCFG0_VC0_INIT_LEN                           = 16  ;
static const uint8_t EXPLR_TLXT_TLXCFG0_VC1_INIT                               = 48  ;
static const uint8_t EXPLR_TLXT_TLXCFG0_VC1_INIT_LEN                           = 16  ;

static const uint8_t EXPLR_TLXT_TLXCFG1_SLOW_CLOCK                             = 0   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_MODE                          = 1   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_MODE_LEN                      = 2   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_ON_OPT_ERR                    = 3   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_ON_MMIO_BAD                   = 4   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_ON_DFLOW_ERR                  = 5   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_ON_BAR0_BAD                   = 6   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_RESERVED                               = 7   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXR_DEBSEL_LO                         = 8   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXR_DEBSEL_LO_LEN                     = 4   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXR_DEBSEL_HI                         = 12  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXR_DEBSEL_HI_LEN                     = 4   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_DBG_DIAL                          = 16  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_DBG_DIAL_LEN                      = 16  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_HI_BW_THRESHOLD                        = 32  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_HI_BW_THRESHOLD_LEN                    = 3   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_MID_BW_THRESHOLD                       = 35  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_MID_BW_THRESHOLD_LEN                   = 3   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_HI_BW_DIS                              = 38  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_MID_BW_ENAB                            = 39  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_HI_BW_ENAB_RD_THRESH                   = 40  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_LOW_LAT_RD_DIS                         = 41  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_CLK_GATE_DIS                           = 42  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_CFEI_ENAB                              = 43  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_CFEI_PERSIST                           = 44  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_CFEI_BIT0                              = 45  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_CFEI_BIT1                              = 46  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TBD                                    = 47  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_0                   = 48  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_0_LEN               = 4   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_1                   = 52  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_1_LEN               = 4   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_2                   = 56  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_2_LEN               = 4   ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_3                   = 60  ;
static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_3_LEN               = 4   ;

static const uint8_t EXPLR_TLXT_TLXCFG2_TLXC_WAT_EN_REG                        = 0   ;
static const uint8_t EXPLR_TLXT_TLXCFG2_TLXC_WAT_EN_REG_LEN                    = 24  ;
static const uint8_t EXPLR_TLXT_TLXCFG2_TBD                                    = 24  ;
static const uint8_t EXPLR_TLXT_TLXCFG2_TBD_LEN                                = 40  ;

static const uint8_t EXPLR_TLXT_TLXFIRACT0_FIR_ACTION0                         = 0   ;
static const uint8_t EXPLR_TLXT_TLXFIRACT0_FIR_ACTION0_LEN                     = 30  ;

static const uint8_t EXPLR_TLXT_TLXFIRACT1_FIR_ACTION1                         = 0   ;
static const uint8_t EXPLR_TLXT_TLXFIRACT1_FIR_ACTION1_LEN                     = 30  ;

static const uint8_t EXPLR_TLXT_TLXFIRMASK_FIR_MASK                            = 0   ;
static const uint8_t EXPLR_TLXT_TLXFIRMASK_FIR_MASK_LEN                        = 30  ;

static const uint8_t EXPLR_TLXT_TLXFIRQ_INFO_REG_PARITY_ERROR                  = 0   ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_CTRL_REG_PARITY_ERROR                  = 1   ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLX_VC0_MAX_CRD_ERROR                  = 2   ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLX_VC1_MAX_CRD_ERROR                  = 3   ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLX_DCP0_MAX_CRD_ERROR                 = 4   ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLX_DCP1_MAX_CRD_ERROR                 = 5   ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_CREDIT_MGMT_ERROR                      = 6   ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_CREDIT_MGMT_PERROR                     = 7   ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_PARITY_ERROR                      = 8   ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_RECOVERABLE_ERROR                 = 9   ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_CONFIG_ERROR                      = 10  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_INFORMATIONAL_PERROR              = 11  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_HARD_ERROR                        = 12  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_RESERVED_10                            = 13  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_RESERVED_10_LEN                        = 3   ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_SHUTDOWN                          = 16  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_BAR0_OR_MMIO_NF                   = 17  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_OC_MALFORMED                      = 18  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_OC_PROTOCOL_ERROR                 = 19  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_ADDR_XLAT                         = 20  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_METADATA_UNC_DPERR                = 21  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_OC_UNSUPPORTED                    = 22  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_OC_FATAL                          = 23  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_CONTROL_ERROR                     = 24  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_INTERNAL_ERROR                    = 25  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_INFORMATIONAL                     = 26  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_TRACE_STOP                        = 27  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_INTERNAL_SCOM_ERROR                    = 28  ;
static const uint8_t EXPLR_TLXT_TLXFIRQ_INTERNAL_SCOM_ERROR_CLONE              = 29  ;

static const uint8_t EXPLR_TLXT_TLXFIRWOF_FIR_WOF                              = 0   ;
static const uint8_t EXPLR_TLXT_TLXFIRWOF_FIR_WOF_LEN                          = 30  ;

static const uint8_t EXPLR_TLXT_TLXTINTHLD0_TLXT_INTHLD_0_REG                  = 0   ;
static const uint8_t EXPLR_TLXT_TLXTINTHLD0_TLXT_INTHLD_0_REG_LEN              = 64  ;

static const uint8_t EXPLR_TLXT_TLXTINTHLD1_TLXT_INTHLD_1_REG                  = 0   ;
static const uint8_t EXPLR_TLXT_TLXTINTHLD1_TLXT_INTHLD_1_REG_LEN              = 64  ;

static const uint8_t EXPLR_TLXT_TLXTINTHLD2_TLXT_INTHLD_2_REG                  = 0   ;
static const uint8_t EXPLR_TLXT_TLXTINTHLD2_TLXT_INTHLD_2_REG_LEN              = 64  ;

static const uint8_t EXPLR_TLXT_TLXTINTHLD3_TLXT_INTHLD_3_REG                  = 0   ;
static const uint8_t EXPLR_TLXT_TLXTINTHLD3_TLXT_INTHLD_3_REG_LEN              = 64  ;

static const uint8_t EXPLR_TLXT_TLXTRAP0_DEBUG_BUS                             = 0   ;
static const uint8_t EXPLR_TLXT_TLXTRAP0_DEBUG_BUS_LEN                         = 64  ;

static const uint8_t EXPLR_TLXT_TLXTRAP1_DEBUG_BUS                             = 0   ;
static const uint8_t EXPLR_TLXT_TLXTRAP1_DEBUG_BUS_LEN                         = 64  ;

static const uint8_t EXPLR_TLXT_TLXTTRAP2_DEBUG_BUS                            = 0   ;
static const uint8_t EXPLR_TLXT_TLXTTRAP2_DEBUG_BUS_LEN                        = 64  ;

static const uint8_t EXPLR_TLXT_TLXTTRAP3_DEBUG_BUS                            = 0   ;
static const uint8_t EXPLR_TLXT_TLXTTRAP3_DEBUG_BUS_LEN                        = 64  ;

static const uint8_t EXPLR_TLXT_TLXTTRAP4_DEBUG_BUS                            = 0   ;
static const uint8_t EXPLR_TLXT_TLXTTRAP4_DEBUG_BUS_LEN                        = 64  ;

static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TLXR_UNUSED                   = 0   ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TLXR_UNUSED_LEN               = 5   ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_7                       = 5   ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TLXR_SHUTDOWN                 = 6   ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MMIO_BAD_WR_RESP_NF           = 7   ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAR0_PERR_NF                  = 8   ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_TEMPLATE_OPCODE_COMBO     = 9   ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_6                       = 10  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_CREDIT_RETURN_SLOT        = 11  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_TEMPLATE_0_FORMAT         = 12  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_RESERVED_FIELD_VALUE          = 13  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_DATA_SEQ_ERR                  = 14  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_RD_BDY_ERR                    = 15  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_WR_BDY_ERR                    = 16  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_5                       = 17  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_INTRP_RESP_TAG            = 18  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_MEMCTL                    = 19  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_4                       = 20  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_3                       = 21  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_2                       = 22  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_ADDRESS_DROPPED               = 23  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_ADDR_XLAT_ERROR_RD            = 24  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_ADDR_XLAT_ERROR_WR            = 25  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_PATTERN_CORRUPT               = 26  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_DATAFLOW_PERR_NF              = 27  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_METADATA_UNC                  = 28  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_PR_RD_DDR         = 29  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_RD_MEM            = 30  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_WRITE             = 31  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_PR_LENGTH         = 32  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_PAD_MEM           = 33  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_PAD_MEM_LEN_ERR               = 34  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_WRITE_LENGTH      = 35  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_READ_LENGTH       = 36  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_OPCODE            = 37  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_TEMPLATE          = 38  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_DATA_CARRIER      = 39  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BUFF_CNTL_PERR                = 40  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_D_LIST_UNC                    = 41  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TAGSTORE_UNC                  = 42  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_B_MGMT_3                      = 43  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_1                       = 44  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_FLIT_PERR                     = 45  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MMIO_WD_PERR                  = 46  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MMIO_WD_INV                   = 47  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SRQ_WD_PERR                   = 48  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SRQ_WD_INV                    = 49  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_D_LIST_UNDERFLOW              = 50  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_DATAFLOW_PERR_F               = 51  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_D_LIST_OVERFLOW               = 52  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MMIO_BAD_WR_RESP_F            = 53  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAR0_PERR_F                   = 54  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_B_MGMT_1                      = 55  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_B_MGMT_2                      = 56  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_ADDR_XLATE_HOLE               = 57  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_DATA_RXD                  = 58  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_METADATA_CORR                 = 59  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TAG_BUFFER_CORR               = 60  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_D_LIST_CORR                   = 61  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_EPOW_SIGNALLED                = 62  ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TRACE_STOP                    = 63  ;

static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MASK_ERRMASK                  = 0   ;
static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MASK_ERRMASK_LEN              = 64  ;

static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_TLXT_PERRORS                  = 0   ;
static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_TLXT_PERRORS_LEN              = 37  ;
static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_TLXT_ERRORS                   = 37  ;
static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_TLXT_ERRORS_LEN               = 27  ;

static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_MASK_ERRMASK                  = 0   ;
static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_MASK_ERRMASK_LEN              = 64  ;

static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_PERRORS                  = 0   ;
static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_PERRORS_LEN              = 8   ;
static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_ERRORS                   = 8   ;
static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_ERRORS_LEN               = 6   ;
static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_INTHLD_PERROR                 = 14  ;
static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_INTHLD_PERROR_LEN             = 4   ;
static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_SPARE                    = 18  ;
static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_SPARE_LEN                = 14  ;

static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_MASK_ERRMASK                  = 0   ;
static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_MASK_ERRMASK_LEN              = 32  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_RESERVED_LAST_LT       = 17  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_ATOMIC_LOCK_MASK_LATCH_REG_MASK      = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN  = 32  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND1_SEL_A     = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND1_SEL_B     = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND2_SEL_A     = 16  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND2_SEL_B     = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C1_INAROW_MODE  = 32  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_UNUSED          = 36  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_UNUSED_LEN      = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C2_INAROW_MODE  = 39  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_UNUSED_2        = 43  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_UNUSED_2_LEN    = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_EXACT_TO_MODE   = 47  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_RESET_C3_ON_C0  = 49  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_SLOW_TO_MODE    = 50  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C1_COUNT_LT     = 52  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C2_COUNT_LT     = 56  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_TO_CMP_LT       = 20  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN   = 24  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND1_SEL_A     = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND1_SEL_B     = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND2_SEL_A     = 16  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND2_SEL_B     = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C1_INAROW_MODE  = 32  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_UNUSED          = 36  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_UNUSED_LEN      = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C2_INAROW_MODE  = 39  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_UNUSED_2        = 43  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_UNUSED_2_LEN    = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_EXACT_TO_MODE   = 47  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_RESET_C3_ON_C0  = 49  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_SLOW_TO_MODE    = 50  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C1_COUNT_LT     = 52  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C2_COUNT_LT     = 56  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_TO_CMP_LT       = 20  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN   = 24  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_GLB_BRCST               = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_GLB_BRCST_LEN           = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRACE_SEL               = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRACE_SEL_LEN           = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRIG_SEL                = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRIG_SEL_LEN            = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_FREEZE_SEL              = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_SYNC_BRCST              = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_SYNC_BRCST_LEN          = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRACE_RUN_STATUS        = 17  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRACE_RUN_STATUS_LEN    = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_IS_FROZEN_STATUS        = 19  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_INST1_CONDITION_HISTORY_STATUS = 20  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_INST1_CONDITION_HISTORY_STATUS_LEN = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_INST2_CONDITION_HISTORY_STATUS = 23  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_INST2_CONDITION_HISTORY_STATUS_LEN = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_INST3_CONDITION_HISTORY_STATUS = 26  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_INST3_CONDITION_HISTORY_STATUS_LEN = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_INST4_CONDITION_HISTORY_STATUS = 29  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_INST4_CONDITION_HISTORY_STATUS_LEN = 3   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_IMM_FREEZE      = 16  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_STOP_ON_ERR     = 17  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_FORCE_TEST      = 19  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_ACCUM_HIST      = 20  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST1_COND3_ENABLE   = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_COND3_ENABLE   = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST3_COND3_ENABLE   = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST4_COND3_ENABLE   = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL = 14  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL = 16  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP     = 32  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE   = 33  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL   = 34  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL   = 39  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_PC_TP_TRIG_SEL       = 44  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN   = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_ARM_SEL              = 46  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_ARM_SEL_LEN          = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL      = 50  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN  = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL      = 54  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN  = 4   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN = 25  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN = 26  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN = 27  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN = 28  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN = 29  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK = 36  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK = 37  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK = 38  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK = 39  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK = 40  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK = 41  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT = 48  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR = 51  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT = 52  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_DEBUG_TRACE_CONTROL_SCOM_TRACE_START = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP  = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET = 2   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_HOLD_LAT_FIR_MASK_PAR            = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_HOLD_LAT_FIR_ACTION0_PAR         = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_HOLD_LAT_FIR_ACTION1_PAR         = 2   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_MASK_FIR_PAR                     = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_MASK_FIR_ACTION0_PAR             = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_MASK_FIR_ACTION1_PAR             = 2   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PCB_WDATA_PARITY_ERROR  = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PCB_ADDRESS_PARITY_ERROR = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_DL_RETURN_WDATA_PARITY_ERROR = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_DL_RETURN_P0_ERROR      = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_UL_RDATA_PARITY_ERROR   = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_UL_P0_ERROR             = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PARITY_ERROR_ON_INTERFACE_MACHINE = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PARITY_ERROR_ON_P2S_MACHINE = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PSCOM_PARALLEL_WRITE_NVLD = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PSCOM_PARALLEL_READ_NVLD = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PSCOM_PARALLEL_ADDR_INVALID = 13  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PCB_COMMAND_PARITY_ERROR = 14  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_GENERAL_TIMEOUT         = 15  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN0                         = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN1                         = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN2                         = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN3                         = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN4                         = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN5                         = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN6                         = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN7                         = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN8                         = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN9                         = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN10                        = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN11                        = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN12                        = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN14                        = 13  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN14_LEN                    = 13  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN26                        = 26  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ABORT_ON_ERROR_REG_MASK_READ_ADDR_P = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ABORT_ON_ERROR_REG_MASK_WRITE_ADDR_P = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ABORT_ON_ERROR_REG_MASK_WRITE_DATA_P = 2   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_READ_ADDRESS_ERR = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_WRITE_ADDRESS_ERR = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_WRITE_DATA_ERR = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_COMMAND_MASTER = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_PCB_PAR_ERR_RSP_INFO = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_PCB_PAR_ERR_RSP_DATA_0_15 = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_PCB_PAR_ERR_RSP_DATA_16_31 = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_PCB_PAR_ERR_RSP_DATA_32_47 = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_PCB_PAR_ERR_RSP_DATA_48_63 = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_IN_PIB2GIF = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_FIRST_PR_WR_ADDRESS_ERR = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_FIRST_PR_WR_DATA_ERR = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_SECOND_PR_WR_ADDRESS_ERR = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_SECOND_PR_WR_DATA_ERR = 13  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_RESERVED = 14  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_RESERVED_LEN = 18  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_SLAVE_ADDR = 32  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_SLAVE_ADDR_LEN = 32  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_RSP_INFO = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_RSP_DATA_0 = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_RSP_DATA_1 = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_RSP_DATA_2 = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_RSP_DATA_3 = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_TIMEOUT       = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_INT_ADDR_ACCESS = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PIB2GIF       = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PCB_ERR_CODE  = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PCB_ERR_CODE_LEN = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_AXI_READ_ADDR_PARITY = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_AXI_WRITE_ADDR_PARITY = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_AXI_WRITE_DATA_PARITY_31_24 = 13  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_AXI_WRITE_DATA_PARITY_23_16 = 14  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_AXI_WRITE_DATA_PARITY_15_8 = 15  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_AXI_WRITE_DATA_PARITY_7_0 = 16  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PIB2GIF_PARITY = 17  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_INFO    = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_DATA_0  = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_DATA_1  = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_DATA_2  = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_DATA_3  = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_TIMEOUT            = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_INT_ADDR_ACCESS    = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_INVALID_ACCESS     = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PCB_ERR_CODE       = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PCB_ERR_CODE_LEN   = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_AXI_READ_ADDR_PARITY = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_AXI_WRITE_ADDR_PARITY = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_AXI_WRITE_DATA_PARITY_31_24 = 13  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_AXI_WRITE_DATA_PARITY_23_16 = 14  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_AXI_WRITE_DATA_PARITY_15_8 = 15  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_AXI_WRITE_DATA_PARITY_7_0 = 16  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PIB2GIF_PARITY     = 17  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_RESET_REG_RESET_STATEMACHINE = 63  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_TIMER_REG_COUNT              = 48  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_TIMER_REG_COUNT_LEN          = 16  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_HOLD_OUT_REG_SPARE_LATCH_UNUSED      = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_HOLD_OUT_REG_OUT                     = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_HOLD_OUT_REG_OUT_LEN                 = 18  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN0                        = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN1                        = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN2                        = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN3                        = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN4                        = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN5                        = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN6                        = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN7                        = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN8                        = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN9                        = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN10                       = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN10_LEN                   = 53  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION0_IN                 = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION0_IN_LEN             = 63  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION1_IN                 = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION1_IN_LEN             = 63  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_MASK_LFIR_IN               = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_MASK_LFIR_IN_LEN           = 63  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN0                  = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN1                  = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN2                  = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN3                  = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN4                  = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN5                  = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN6                  = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN7                  = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN8                  = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN9                  = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN10                 = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN11                 = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN12                 = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN13                 = 13  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN14                 = 14  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN15                 = 15  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN16                 = 16  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN17                 = 17  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN18                 = 18  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN19                 = 19  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN20                 = 20  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN21                 = 21  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN22                 = 22  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_MASK_IN                  = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_MASK_IN_LEN              = 22  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN0                         = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN1                         = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN2                         = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN3                         = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN4                         = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN5                         = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN6                         = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN7                         = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN8                         = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN9                         = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN10                        = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN11                        = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN                          = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN_LEN                      = 4   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_0                     = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_1                     = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_2                     = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_3                     = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_4                     = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_5                     = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_6                     = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_7                     = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_8                     = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_9                     = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PCS_GPBC_IRQ_106             = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_MOORTEC_PVT                  = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PCS_GPBC_IRQ_111             = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PCS_GPBC_IRQ_112             = 13  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_TOP_DIGITAL_IO__FAIL_N       = 14  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PROC_SS__TOP_FATAL           = 15  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PROC_SS__TOP_NON_FATAL       = 16  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_7          = 17  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_6          = 18  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_5          = 19  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_4          = 20  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_3          = 21  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_2          = 22  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_1          = 23  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_0          = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_TOP_DIGITAL_IO__DDR_EVENTB   = 25  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_DDR4_PHY__FATAL              = 26  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_DDR4_PHY__NON_FATAL          = 27  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_DDR4_PHY__DDR_PHY_IRQ0       = 28  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_7__FATAL       = 29  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_6__FATAL       = 30  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_5__FATAL       = 31  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_4__FATAL       = 32  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_3__FATAL       = 33  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_2__FATAL       = 34  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_1__FATAL       = 35  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_0__FATAL       = 36  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_7__NON_FATAL   = 37  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_6__NON_FATAL   = 38  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_5__NON_FATAL   = 39  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_4__NON_FATAL   = 40  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_3__NON_FATAL   = 41  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_2__NON_FATAL   = 42  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_1__NON_FATAL   = 43  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_0__NON_FATAL   = 44  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_7__SERDES_INT  = 45  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_6__SERDES_INT  = 46  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_5__SERDES_INT  = 47  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_4__SERDES_INT  = 48  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_3__SERDES_INT  = 49  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_2__SERDES_INT  = 50  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_1__SERDES_INT  = 51  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_0__SERDES_INT  = 52  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ABORT_ON_ERROR_REG_MASK_READ_ADDR_P = 61  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ABORT_ON_ERROR_REG_MASK_WRITE_ADDR_P = 62  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ABORT_ON_ERROR_REG_MASK_WRITE_DATA_P = 63  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK2_REG_ERROR_MASK2_REG = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK2_REG_ERROR_MASK2_REG_LEN = 64  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_REQ_DATA_0 = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_REQ_DATA_1 = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_REQ_DATA_2 = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_REQ_DATA_3 = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_REQ_ADDR_0 = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_REQ_ADDR_1 = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_REQ_CTRL = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_TIMEOUT       = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_INT_ADDR_ACCESS = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_GIF2PCB       = 32  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_GIF2PCB_LEN   = 7   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_DATA_0  = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_DATA_1  = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_DATA_2  = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_DATA_3  = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_ADDR_0  = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_ADDR_1  = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_CTRL    = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_TIMEOUT            = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_INT_ADDR_ACCESS    = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_ERROR_REG_UNUSED1  = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_ERROR_REG_UNUSED1_LEN = 23  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_GIF2PCB            = 32  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_GIF2PCB_LEN        = 14  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_GIF2PCB_ERROR_REG  = 46  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_GIF2PCB_ERROR_REG_LEN = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_ERROR_REG_UNUSED2  = 50  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_ERROR_REG_UNUSED2_LEN = 14  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG2_TP_MSG_REG        = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG2_TP_MSG_REG_LEN    = 64  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_TIMER_REG_COUNT              = 48  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_TIMER_REG_COUNT_LEN          = 16  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PCB_WDATA_PARITY    = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY  = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_DL_RETURN_P0        = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_UL_RDATA_PARITY     = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_UL_P0               = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD  = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY  = 14  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_GENERAL_TIMEOUT     = 15  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_UNUSED_BIT_2          = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_WATCHDOG_ENABLE       = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_SCOM_HANG_LIMIT       = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN   = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_FORCE_ALL_RINGS       = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_RESERVED_LT           = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_RESERVED_LT_LEN       = 3   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9
        ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16
        ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17
        ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN0                             = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_LFIR_RECOV_ERR                  = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN4                             = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN5                             = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN6                             = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN7                             = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN8                             = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN9                             = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN10                            = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN11                            = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN12                            = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN13                            = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN14                            = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN14_LEN                        = 12  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_RING_FENCE_MASK_LATCH_REG_ENABLE     = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 31  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN0                           = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN1                           = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN2                           = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN3                           = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN4                           = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN5                           = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN6                           = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN7                           = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN8                           = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN9                           = 9   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPA_MASK_IN                          = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPA_MASK_IN_LEN                      = 10  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_SUM_MASK_REG_SMASK_IN                = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_SUM_MASK_REG_SMASK_IN_LEN            = 5   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_HI_DATA_REG_DATA               = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_HI_DATA_REG_DATA_LEN           = 64  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_DATA               = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_DATA_LEN           = 32  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_ADDRESS            = 32  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_ADDRESS_LEN        = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_LAST_BANK          = 42  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_LAST_BANK_LEN      = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_LAST_BANK_VALID    = 51  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_WRITE_ON_RUN       = 52  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_RUNNING            = 53  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_HOLD_ADDRESS       = 54  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN   = 10  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_BANK_MODE        = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_ENH_MODE         = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_SELECT_CONTROL   = 14  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF     = 18  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_RUN_STATUS       = 19  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_RUN_STICKY       = 20  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_TRA_MASTER_CLOCK_ENABLE = 22  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_DISABLE_RD_ACT   = 23  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_TRA_MUX_SEL      = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED   = 25  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 3   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2_PATTERNA       = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN   = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2_PATTERNB       = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN   = 24  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3_PATTERNC       = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN   = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3_PATTERND       = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3_PATTERND_LEN   = 24  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4_MASKA          = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4_MASKA_LEN      = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4_MASKB          = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4_MASKB_LEN      = 24  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5_MASKC          = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5_MASKC_LEN      = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5_MASKD          = 24  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5_MASKD_LEN      = 24  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL  = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL  = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL  = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL  = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK  = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK  = 18  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP  = 34  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP  = 35  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_UNIT_TC_TRA_FIR_ERR = 37  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_SPARE_LT       = 38  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_SPARE_LT_LEN   = 2   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1   ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_RINGS_REG_RINGS        = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_RINGS_REG_RINGS_LEN    = 32  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN0                             = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN1                             = 1   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN2                             = 2   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN3                             = 3   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN4                             = 4   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN5                             = 5   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN6                             = 6   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN7                             = 7   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN8                             = 8   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN9                             = 9   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN10                            = 10  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN11                            = 11  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN12                            = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN13                            = 13  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN14                            = 14  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN14_LEN                        = 12  ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN26                            = 26  ;

static const uint8_t EXPLR_TP_MB_UNIT_TOP_XTRA_TRACE_MODE_DATA                 = 0   ;
static const uint8_t EXPLR_TP_MB_UNIT_TOP_XTRA_TRACE_MODE_DATA_LEN             = 64  ;

static const uint8_t EXPLR_WDF_AACR_BUFFER                                     = 0   ;
static const uint8_t EXPLR_WDF_AACR_ADDRESS                                    = 1   ;
static const uint8_t EXPLR_WDF_AACR_ADDRESS_LEN                                = 9   ;
static const uint8_t EXPLR_WDF_AACR_AUTOINC                                    = 10  ;
static const uint8_t EXPLR_WDF_AACR_ECCGEN                                     = 11  ;
static const uint8_t EXPLR_WDF_AACR_PASSTHRU                                   = 12  ;

static const uint8_t EXPLR_WDF_AADR_DATA                                       = 0   ;
static const uint8_t EXPLR_WDF_AADR_DATA_LEN                                   = 64  ;

static const uint8_t EXPLR_WDF_AAER_META_ECC_SPARE                             = 0   ;
static const uint8_t EXPLR_WDF_AAER_META_ECC_SPARE_LEN                         = 16  ;

static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE0_SWIZZLE                         = 0   ;
static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE0_SWIZZLE_LEN                     = 11  ;
static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE1_SWIZZLE                         = 11  ;
static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE1_SWIZZLE_LEN                     = 11  ;
static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE2_SWIZZLE                         = 22  ;
static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE2_SWIZZLE_LEN                     = 11  ;
static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE3_SWIZZLE                         = 33  ;
static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE3_SWIZZLE_LEN                     = 11  ;
static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE4_SWIZZLE                         = 44  ;
static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE4_SWIZZLE_LEN                     = 11  ;

static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE5_SWIZZLE                         = 0   ;
static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE5_SWIZZLE_LEN                     = 11  ;
static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE6_SWIZZLE                         = 11  ;
static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE6_SWIZZLE_LEN                     = 11  ;
static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE7_SWIZZLE                         = 22  ;
static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE7_SWIZZLE_LEN                     = 11  ;
static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE8_SWIZZLE                         = 33  ;
static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE8_SWIZZLE_LEN                     = 11  ;
static const uint8_t EXPLR_WDF_DQS1R_CFG_ODD_RANK_SWIZZLE_EN                   = 44  ;
static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE9_SWIZZLE                         = 45  ;
static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE9_SWIZZLE_LEN                     = 11  ;

static const uint8_t EXPLR_WDF_WECR_CFG_WDF_ECC_CHK_DISABLE                    = 0   ;
static const uint8_t EXPLR_WDF_WECR_CFG_WDF_ECC_COR_DISABLE                    = 1   ;
static const uint8_t EXPLR_WDF_WECR_CFG_CRC_MODE_EN                            = 2   ;
static const uint8_t EXPLR_WDF_WECR_CFG_CRC_MODE_X8                            = 3   ;
static const uint8_t EXPLR_WDF_WECR_CFG_FORCE_DFI_CG_ALWAYS_ON                 = 4   ;
static const uint8_t EXPLR_WDF_WECR_CFG_WDF_INTEGRITY_CHECK_DISABLE            = 5   ;
static const uint8_t EXPLR_WDF_WECR_CFG_WDF_CG_FORCE                           = 6   ;
static const uint8_t EXPLR_WDF_WECR_CFG_WDF_SPARE7_11                          = 7   ;
static const uint8_t EXPLR_WDF_WECR_CFG_WDF_SPARE7_11_LEN                      = 5   ;
static const uint8_t EXPLR_WDF_WECR_CFG_WDF_TRACE_SEL                          = 12  ;
static const uint8_t EXPLR_WDF_WECR_CFG_WDF_TRACE_SEL_LEN                      = 4   ;
static const uint8_t EXPLR_WDF_WECR_CFG_WDF_WAT_EN                             = 16  ;
static const uint8_t EXPLR_WDF_WECR_CFG_WDF_WAT_EN_LEN                         = 4   ;

static const uint8_t EXPLR_WDF_WERR_DQS0R_PE                                   = 0   ;
static const uint8_t EXPLR_WDF_WERR_DQS1R_PE                                   = 1   ;
static const uint8_t EXPLR_WDF_WERR_AACR_PE                                    = 2   ;
static const uint8_t EXPLR_WDF_WERR_AADR_PE                                    = 3   ;
static const uint8_t EXPLR_WDF_WERR_AAER_PE                                    = 4   ;
static const uint8_t EXPLR_WDF_WERR_WECR_PE                                    = 5   ;
static const uint8_t EXPLR_WDF_WERR_WSPAR_PE                                   = 8   ;
static const uint8_t EXPLR_WDF_WERR_WMSK_PE                                    = 9   ;
static const uint8_t EXPLR_WDF_WERR_RDF_BE_PE                                  = 15  ;
static const uint8_t EXPLR_WDF_WERR_TLXR_WR_PE                                 = 16  ;
static const uint8_t EXPLR_WDF_WERR_TLXR_BAD_PE                                = 17  ;
static const uint8_t EXPLR_WDF_WERR_TLXR_BE_PE                                 = 18  ;
static const uint8_t EXPLR_WDF_WERR_SRQ_IF_PE                                  = 19  ;
static const uint8_t EXPLR_WDF_WERR_RDF_IF_PE                                  = 20  ;
static const uint8_t EXPLR_WDF_WERR_MMIO_IF_PE                                 = 21  ;
static const uint8_t EXPLR_WDF_WERR_CONTROL_PE                                 = 22  ;
static const uint8_t EXPLR_WDF_WERR_ECCGEN_ERR                                 = 23  ;
static const uint8_t EXPLR_WDF_WERR_WBUF_FUNC_UE                               = 24  ;
static const uint8_t EXPLR_WDF_WERR_RMWBUF_FUNC_UE                             = 25  ;
static const uint8_t EXPLR_WDF_WERR_BEBUF_FUNC_UE                              = 26  ;
static const uint8_t EXPLR_WDF_WERR_BE_PE                                      = 27  ;
static const uint8_t EXPLR_WDF_WERR_INTEGRITY_ERR                              = 28  ;
static const uint8_t EXPLR_WDF_WERR_WBUF_MMIO_UE                               = 29  ;
static const uint8_t EXPLR_WDF_WERR_SCOM_FSM_PE                                = 32  ;
static const uint8_t EXPLR_WDF_WERR_RMWBUF_SCOM_UE                             = 33  ;
static const uint8_t EXPLR_WDF_WERR_BEBUF_SCOM_UE                              = 34  ;
static const uint8_t EXPLR_WDF_WERR_WBUF_CE                                    = 48  ;
static const uint8_t EXPLR_WDF_WERR_RMWBUF_CE                                  = 49  ;
static const uint8_t EXPLR_WDF_WERR_BEBUF_CE                                   = 50  ;

static const uint8_t EXPLR_WDF_WESR_SYNDROME                                   = 0   ;
static const uint8_t EXPLR_WDF_WESR_SYNDROME_LEN                               = 8   ;
static const uint8_t EXPLR_WDF_WESR_SEVERITY                                   = 8   ;
static const uint8_t EXPLR_WDF_WESR_PART                                       = 9   ;
static const uint8_t EXPLR_WDF_WESR_SOURCE                                     = 10  ;
static const uint8_t EXPLR_WDF_WESR_SOURCE_LEN                                 = 3   ;

static const uint8_t EXPLR_WDF_WMSK_DQS0R_PE                                   = 0   ;
static const uint8_t EXPLR_WDF_WMSK_DQS1R_PE                                   = 1   ;
static const uint8_t EXPLR_WDF_WMSK_AACR_PE                                    = 2   ;
static const uint8_t EXPLR_WDF_WMSK_AADR_PE                                    = 3   ;
static const uint8_t EXPLR_WDF_WMSK_AAER_PE                                    = 4   ;
static const uint8_t EXPLR_WDF_WMSK_WECR_PE                                    = 5   ;
static const uint8_t EXPLR_WDF_WMSK_WSPAR_PE                                   = 8   ;
static const uint8_t EXPLR_WDF_WMSK_WMSK_PE                                    = 9   ;
static const uint8_t EXPLR_WDF_WMSK_RDF_BE_PE                                  = 15  ;
static const uint8_t EXPLR_WDF_WMSK_TLXR_WR_PE                                 = 16  ;
static const uint8_t EXPLR_WDF_WMSK_TLXR_BAD_PE                                = 17  ;
static const uint8_t EXPLR_WDF_WMSK_TLXR_BE_PE                                 = 18  ;
static const uint8_t EXPLR_WDF_WMSK_SRQ_IF_PE                                  = 19  ;
static const uint8_t EXPLR_WDF_WMSK_RDF_IF_PE                                  = 20  ;
static const uint8_t EXPLR_WDF_WMSK_MMIO_IF_PE                                 = 21  ;
static const uint8_t EXPLR_WDF_WMSK_CONTROL_PE                                 = 22  ;
static const uint8_t EXPLR_WDF_WMSK_ECCGEN_ERR                                 = 23  ;
static const uint8_t EXPLR_WDF_WMSK_WBUF_FUNC_UE                               = 24  ;
static const uint8_t EXPLR_WDF_WMSK_RMWBUF_FUNC_UE                             = 25  ;
static const uint8_t EXPLR_WDF_WMSK_BEBUF_FUNC_UE                              = 26  ;
static const uint8_t EXPLR_WDF_WMSK_BE_PE                                      = 27  ;
static const uint8_t EXPLR_WDF_WMSK_INTEGRITY_ERR                              = 28  ;
static const uint8_t EXPLR_WDF_WMSK_WBUF_MMIO_UE                               = 29  ;
static const uint8_t EXPLR_WDF_WMSK_SCOM_FSM_PE                                = 32  ;
static const uint8_t EXPLR_WDF_WMSK_RMWBUF_SCOM_UE                             = 33  ;
static const uint8_t EXPLR_WDF_WMSK_BEBUF_SCOM_UE                              = 34  ;
static const uint8_t EXPLR_WDF_WMSK_WBUF_CE                                    = 48  ;
static const uint8_t EXPLR_WDF_WMSK_RMWBUF_CE                                  = 49  ;
static const uint8_t EXPLR_WDF_WMSK_BEBUF_CE                                   = 50  ;

static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R0_LEFT                      = 0   ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R0_LEFT_LEN                  = 5   ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R0_RIGHT                     = 5   ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R0_RIGHT_LEN                 = 5   ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R1_LEFT                      = 10  ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R1_LEFT_LEN                  = 5   ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R1_RIGHT                     = 15  ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R1_RIGHT_LEN                 = 5   ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R2_LEFT                      = 20  ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R2_LEFT_LEN                  = 5   ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R2_RIGHT                     = 25  ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R2_RIGHT_LEN                 = 5   ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R3_LEFT                      = 30  ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R3_LEFT_LEN                  = 5   ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R3_RIGHT                     = 35  ;
static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R3_RIGHT_LEN                 = 5   ;

static const uint8_t EXPLR_EFUSE_IMAGE_OUT_0_ENTERPRISE_MODE_DIS               = 10  ;

#endif
OpenPOWER on IntegriCloud