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# Note : Assumes these vars were setup in startup.simics
# $hb_masterproc : name of master proc chip object
# $hb_pnor : name of pnor object associated with master proc
#($hb_masterproc).proc_fsi2host_mbox->responder_enable=1
# Default value is to preload VPD into PNOR image
if not defined hb_skip_vpd_preload {$hb_skip_vpd_preload = 0}
if ($hb_mode == 0) { # Axone and beyond
# There is no VPD cache on Axone
$hb_skip_vpd_preload = 1;
}
# Preload VPD in PNOR unless told not to
if ($hb_skip_vpd_preload == 0) {
# Pass processor chip type. All proc chip types should be the same.
if (get-object-list proc_hb_standalone) {
$procChipType=(get-object-list proc_hb_standalone)[0]->chip_type
python "os.environ['HB_PROC_CHIP_TYPE'] = \""+$procChipType+"\""
} else if (get-object-list p9_proc) {
$procChipType=(get-object-list p9_proc)[0]->chip_type
python "os.environ['HB_PROC_CHIP_TYPE'] = \""+$procChipType+"\""
} else {
python "os.environ['HB_PROC_CHIP_TYPE'] = \""+$proc_chip_type+"\""
}
try {
run-python-file (lookup-file hbfw/hb-pnor-vpd-preload.py)
# Must match pnor layout used (see eyecatch in layout)
echo "PNOR layout offset for VPD:"
if ($hb_mode == 1) { # Nimbus/Cumulus
# PNOR eyecatch MVPD
echo " - MVPD at 0x79000"
($hb_pnor).load-file ./sysmvpd.dat.ecc 0x79000
# PNOR eyecatch DJVPD
echo " - DJVPD at 0x31000"
($hb_pnor).load-file ./sysspd.dat.ecc 0x31000
# PNOR eyecatch CVPD
echo " - CVPD at 0x109000"
($hb_pnor).load-file ./sysmemvpd.dat.ecc 0x109000
} else { # Axone and beyond
# PNOR eyecatch MVPD
echo " - MVPD at 0x31000"
($hb_pnor).load-file ./sysmvpd.dat.ecc 0x31000
}
} except { echo "ERROR: Failed to preload VPD into PNOR." }
}
if ($hb_mode == 0) {
$eccPreload = (lookup-file "%simics%/eecache_prebuilt.bin.ecc")
# NOTE must change offset if PNOR layout changes EECACHE offsets
echo " - Loading prebuilt EECACHE "+$eccPreload+" at 0x3D80000 in PNOR"
($hb_pnor).load-file $eccPreload 0x2C000
}
# Turn on all processor cec-chips
if ($hb_mode == 1) {
# Nimbus/Cumulus
foreach $cc in (get-object-list p9_proc) {
echo $cc
#Trigger a power on to cec-chip
echo "-Trigger power on"
@mp="%s.proc_chip"%simenv.cc
@SIM_get_interface(SIM_get_object(mp),"signal").signal_raise()
}
} else {
# Axone and Beyond:
foreach $proc in (get-component-list -all proc_pib){
foreach $cc in (get-object-list component=$proc type=cec-chip -recursive) {
@SIM_get_interface(SIM_get_object(simenv.cc), "signal").signal_raise()
}
}
}
#Power on cec-chip on memory controllers if present
foreach $cp in (get-object-list p9_centaur_cfam -recursive){
echo $cp
@cc="%s.membuf_chip"%simenv.cp
@ignore=SIM_get_interface(SIM_get_object(cc),"signal").signal_raise()
}
###################################
#Enable the IPMI Responder
###################################
echo "Enable IPMI Responder"
try {
run-python-file (lookup-file hbfw/ipmi_bt_responder.py)
} except { echo "ERROR: Failed to load IPMIresponder." }
#Cumulus/Nimbus
if ($hb_mode == 1) {
# Setup fabric ID for master proc
($hb_masterproc_cecchip).invoke parallel_store SCOM 0x1000008 "00000000_00000000" 64 #group=0, chip=0
###################################
#Enable SBE
###################################
echo "Enable the SBE"
# Set mailbox scratch registers so that the SBE starts in plck mode
# Set Boot Freq valid bit (bit 3) and valid data bit (bit 7)
($hb_masterproc_cecchip).invoke parallel_store SCOM 0x5003F "31000000_00000000" 64
($hb_masterproc_cecchip).invoke parallel_store SCOM 0x5003A "00000000_00000000" 64
# Set the Nest PLL Bucket ID to 5 in the 4th byte of Mbox Scratch Reg 4
($hb_masterproc_cecchip).invoke parallel_store SCOM 0x5003B "00000005_00000000" 64
($hb_masterproc_cecchip).invoke parallel_store FSIMBOX 0x01 "80000000" 32
($hb_masterproc_cecchip).invoke parallel_store FSIMBOX 0x08 "00080000" 32
}
###############################
#Initialize Explorer Registers
###############################
if ($hb_mode == 0) { #Only do this on Axone and later models that have Explorer chip
# IDEC register consumed by Hostboot
# UCHIP(0x2134)=0x110600D2
# TODO RTC: 215621 Remove workarounds after simics gets updated
set-class-attr ocmb mscc_regs_xcbi_chip_info 0x110600D2
# Loop over all explorer chips
foreach $obj in (get-object-list ocmb -all){
# RAM1 image ID consumed by Hostboot
# UCHIP(0x2200)=0x00000000
$obj->mscc_regs_xcbi_ram1[0] = 0x00000000
# RAM1 hash value registers consumed by Hostboot
# This matches the hash of zero-filled 4k file.
$obj->mscc_regs_xcbi_ram1[1] = 0x2D23913D
$obj->mscc_regs_xcbi_ram1[2] = 0x3759EF01
$obj->mscc_regs_xcbi_ram1[3] = 0x704A86B4
$obj->mscc_regs_xcbi_ram1[4] = 0xBEE3AC8A
$obj->mscc_regs_xcbi_ram1[5] = 0x29002313
$obj->mscc_regs_xcbi_ram1[6] = 0xECC98A74
$obj->mscc_regs_xcbi_ram1[7] = 0x24425A78
$obj->mscc_regs_xcbi_ram1[8] = 0x170F2195
$obj->mscc_regs_xcbi_ram1[9] = 0x77822FD7
$obj->mscc_regs_xcbi_ram1[10] = 0x7E4AE963
$obj->mscc_regs_xcbi_ram1[11] = 0x13547696
$obj->mscc_regs_xcbi_ram1[12] = 0xAD7D5949
$obj->mscc_regs_xcbi_ram1[13] = 0xB58E12D5
$obj->mscc_regs_xcbi_ram1[14] = 0x063EF2EE
$obj->mscc_regs_xcbi_ram1[15] = 0x063B5957
$obj->mscc_regs_xcbi_ram1[16] = 0x40A3A12D
# Allow for testing MMIO HW failures
# Forces write access to TRACE_TRDATA_CONFIG_0 to fail
# in src/usr/mmio/test/mmiotest.H
# NOTE: address is left shifted 3 and has MMIO
# offset (0x100000000) added.
$obj->mmio_regs_mmioerr = 0x0000000140082018
}
}
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