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# Note : Assumes these vars were setup in startup.simics
# $hb_masterproc : name of master proc chip object
# $hb_pnor : name of pnor object associated with master proc
($hb_masterproc).proc_fsi2host_mbox->responder_enable=1
# Default value is to preload VPD into PNOR image
if not defined hb_skip_vpd_preload {$hb_skip_vpd_preload = 0}
# Preload VPD in PNOR unless told not to
if ($hb_skip_vpd_preload == 0) {
# Pass processor chip type. All proc chip types should be the same.
if (get-object-list p9_proc) {
$procChipType=(get-object-list p9_proc)[0]->chip_type
python "os.environ['HB_PROC_CHIP_TYPE'] = \""+$procChipType+"\""
}
try {
echo "Preload VPD into PNOR"
run-python-file (lookup-file hbfw/hb-pnor-vpd-preload.py)
# Must match pnor layout used (see eyecatch in layout)
echo "PNOR layout offset for VPD:"
# PNOR eyecatch MVPD
echo " - MVPD at 0x79000"
($hb_pnor).sfc_master_mem.load-file ./sysmvpd.dat.ecc 0x79000
# PNOR eyecatch DJVPD
echo " - DJVPD at 0x31000"
($hb_pnor).sfc_master_mem.load-file ./sysspd.dat.ecc 0x31000
# PNOR eyecatch CVPD
echo " - CVPD at 0x109000"
($hb_pnor).sfc_master_mem.load-file ./sysmemvpd.dat.ecc 0x109000
} except { echo "ERROR: Failed to preload VPD into PNOR." }
}
# Loop through every processor chip
foreach $cc in (get-object-list p9_proc) {
echo $cc
#Trigger a power on to cec-chip
#echo "-Trigger power on"
@mp="%s.proc_chip"%simenv.cc
@SIM_get_interface(SIM_get_object(mp),"signal").signal_raise()
}
#Power on cec-chip on centaurs if present
foreach $cp in (get-object-list p9_centaur_cfam -recursive){
echo $cp
@cc="%s.membuf_chip"%simenv.cp
@ignore=SIM_get_interface(SIM_get_object(cc),"signal").signal_raise()
}
system_cmp0.cpu0_0_00_0.enable
###################################
#Enable the IPMI Responder
###################################
echo "Enable IPMI Responder"
try {
run-python-file (lookup-file hbfw/ipmi_bt_responder.py)
} except { echo "ERROR: Failed to load IPMIresponder." }
###################################
#Enable SBE
###################################
echo "Enable the SBE"
# Set mailbox scratch registers so that the SBE starts in plck mode
# Set Boot Freq valid bit (bit 3) and valid data bit (bit 7)
($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003F "31000000_00000000" 64
($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "00000000_00000000" 64
# Set the Nest PLL Bucket ID to 3 in the 4th byte of Mbox Scratch Reg 4
($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003B "00000003_00000000" 64
($hb_masterproc).proc_chip.invoke parallel_store FSIMBOX 0x01 "80000000" 32
($hb_masterproc).proc_chip.invoke parallel_store FSIMBOX 0x08 "00080000" 32
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