base
CLASS
TYPE
MODEL
HUID
PHYS_PATH
AFFINITY_PATH
PRIMARY_CAPABILITIES
HWAS_STATE
HWAS_STATE_CHANGED_FLAG
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
DECONFIG_GARDABLE0
RESOURCE_IS_CRITICAL0
ORDINAL_ID
FAPI_POS
FAPI_NAME
PNOR_FLASH_WORKAROUNDS
chip
base
CLASS
CHIP
POSITION
FSI_MASTER_CHIP
ALTFSI_MASTER_CHIP
FSI_MASTER_TYPE
NO_MASTER
MRU_ID
FSI_MASTER_PORT
ALTFSI_MASTER_PORT
FSI_SLAVE_CASCADE
FSI_OPTION_FLAGS
EC
CHIP_ID
FRU_ID
HDAT_EC
MINI_EC
chip-processor
chip
TYPE
PROC
PROC_MASTER_TYPE
PRIMARY_CAPABILITIES
supportsFsiScom1
supportsXscom1
supportsInbandScom0
reserved0
SCOM_SWITCHES
FSI_GP_REG_SCOM_ACCESS
1
FABRIC_NODE_ID
FABRIC_GROUP_ID
PROC_EFF_FABRIC_GROUP_ID
FABRIC_CHIP_ID
PROC_EFF_FABRIC_CHIP_ID
CHIP_HAS_SBE
1
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
VPD_REC_NUM
MSS_MEM_MC_IN_GROUP
PROC_MEM_BASES
PROC_MEM_SIZES
PROC_MIRROR_BASES
PROC_MIRROR_SIZES
PROC_L3_BAR1_REG
PROC_L3_BAR2_REG
PROC_L3_BAR_GROUP_MASK_REG
PROC_PCIE_NOT_F_LINK
MSS_MCS_GROUP_32
MSS_MEM_IPL_COMPLETE
PM_UNDERVOLTING_FRQ_MINIMUM
PM_UNDERVOLTING_FREQ_MAXIMUM
PM_SPIVID_PORT_ENABLE
PM_APSS_CHIP_SELECT
PM_PBAX_NODEID
PBAX_GROUPID
PBAX_CHIPID
PBAX_BRDCST_ID_VECTOR
PM_SLEEP_ENTRY
PM_SLEEP_EXIT
PM_SLEEP_TYPE
PM_WINKLE_ENTRY
PM_WINKLE_EXIT
PM_WINKLE_TYPE
PM_AISS_TIMEOUT
PM_EXTERNAL_VRM_STEPDELAY_RANGE
PM_EXTERNAL_VRM_STEPDELAY_VALUE
PM_IVRMS_ENABLED
PM_OCC_HEARTBEAT_TIME
PM_PBAX_RCV_RESERV_TIMEOUT
PM_PBAX_SND_RESERV_TIMEOUT
PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE
PM_PBAX_SND_RETRY_THRESHOLD
PM_PFET_POWERDOWN_CORE_DELAY0
PM_PFET_POWERDOWN_CORE_DELAY0_VALUE
PM_PFET_POWERDOWN_CORE_DELAY1
PM_PFET_POWERDOWN_CORE_DELAY1_VALUE
PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT
PM_PFET_POWERDOWN_ECO_DELAY0
PM_PFET_POWERDOWN_ECO_DELAY0_VALUE
PM_PFET_POWERDOWN_ECO_DELAY1
PM_PFET_POWERDOWN_ECO_DELAY1_VALUE
PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT
PM_PFET_POWERUP_CORE_DELAY0
PM_PFET_POWERUP_CORE_DELAY0_VALUE
PM_PFET_POWERUP_CORE_DELAY1
PM_PFET_POWERUP_CORE_DELAY1_VALUE
PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT
PM_PFET_POWERUP_ECO_DELAY0
PM_PFET_POWERUP_ECO_DELAY0_VALUE
PM_PFET_POWERUP_ECO_DELAY1
PM_PFET_POWERUP_ECO_DELAY1_VALUE
PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT
PM_PMC_HANGPULSE_DIVIDER
PM_POWER_PROXY_TRACE_TIMER
PM_PPT_TIMER_MATCH_VALUE
PM_PPT_TIMER_TICK
PM_PSTATE0_FREQUENCY
PM_PSTATE_STEPSIZE
PM_PVSAFE_PSTATE
PM_RESONANT_CLOCK_ENABLE
PM_RESONANT_CLOCK_FULL_CSB_PSTATE
PM_RESONANT_CLOCK_HFRHIGH_PSTATE
PM_RESONANT_CLOCK_HFRLOW_PSTATE
PM_RESONANT_CLOCK_LFRLOW_PSTATE
PM_RESONANT_CLOCK_LFRUPPER_PSTATE
PM_SAFE_PSTATE
PM_SLEEP_WINKLE_REQUEST_TIMEOUT
PM_SPIPSS_CLOCK_DIVIDER
PM_SPIPSS_CLOCK_PHASE
PM_SPIPSS_CLOCK_POLARITY
PM_SPIPSS_FRAME_SIZE
PM_SPIPSS_INTER_FRAME_DELAY
PM_SPIPSS_INTER_FRAME_DELAY_SETTING
PM_SPIPSS_IN_COUNT
PM_SPIPSS_IN_DELAY
PM_SPIPSS_OUT_COUNT
PM_SPIVID_CLOCK_DIVIDER
PM_SPIVID_CLOCK_PHASE
PM_SPIVID_CLOCK_POLARITY
PM_SPIVID_CRC_CHECK_ENABLE
PM_SPIVID_CRC_GEN_ENABLE
PM_SPIVID_CRC_POLYNOMIAL_ENABLES
PM_SPIVID_FRAME_SIZE
PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS
PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE
PM_SPIVID_INTER_RETRY_DELAY
PM_SPIVID_INTER_RETRY_DELAY_VALUE
PM_SPIVID_IN_DELAY_FRAME1
PM_SPIVID_IN_DELAY_FRAME2
PM_SPIVID_MAJORITY_VOTE_ENABLE
PM_SPIVID_MAX_RETRIES
PROC_DPLL_DIVIDER
SKIP_HW_VREF_CAL
SKIP_RD_VREF_VREFSENSE_OVERRIDE
SBE_SEEPROM_I2C_ADDRESS_BYTES
SBE_SEEPROM_I2C_DEVICE_ADDRESS
SBE_SEEPROM_I2C_PORT
PNOR_I2C_ADDRESS_BYTES
PROC_SECURITY_SETUP_VECTOR
PROC_MIRROR_BASES_ACK
PROC_MIRROR_SIZES_ACK
PROC_MEM_BASES_ACK
PROC_MEM_SIZES_ACK
CPM_INFLECTION_POINTS
PROC_SBE_MASTER_CHIP
BACKUP_SEEPROM_SELECT
PROC_SELECT_BOOT_SEEPROM_IMAGE
TOD_ROLE
PM_OCC_LFIR_MASK
PM_PBA_FIR_MASK
PM_PMC_LFIR_MASK
PM_FIRINIT_DONE_ONCE_FLAG
I2C_SWITCHES
useFsiI2C1
useHostI2C0
reserved0
CDM_DOMAINFABRIC
HOT_PLUG_POWER_CONTROLLER_INFO
PROC_R_LOADLINE_VDD_UOHM
PROC_R_DISTLOSS_VDD_UOHM
PROC_VRM_VOFFSET_VDD_UV
PROC_R_LOADLINE_VDN_UOHM
PROC_R_DISTLOSS_VDN_UOHM
PROC_VRM_VOFFSET_VDN_UV
PROC_R_LOADLINE_VCS_UOHM
PROC_R_DISTLOSS_VCS_UOHM
PROC_VRM_VOFFSET_VCS_UV
TOD_CPU_DATA
ICACHE_ASSOC_SETS
ICACHE_SIZE
ICACHE_LINE_SIZE
ICACHE_BLOCK_SIZE
DCACHE_LINE_SIZE
DCACHE_ASSOC_SETS
DATA_CACHE_SIZE
DATA_CACHE_LINE_SIZE
L2_CACHE_LINE_SIZE
L2_CACHE_SIZE
L2_CACHE_ASSOC_SETS
L3_CACHE_LINE_SIZE
L3_CACHE_SIZE
TLB_DATA_ENTRIES
TLB_INSTR_ENTRIES
TLB_DATA_ASSOC_SETS
TLB_INSTR_ASSOC_SETS
TLB_RESERVE_SIZE
TIME_BASE
CPU_ATTR
ADU_XSCOM_BAR_BASE_ADDR
PROC_OCC_SANDBOX_SIZE
PROC_FABRIC_SYSTEM_MASTER_CHIP
PROC_FABRIC_GROUP_MASTER_CHIP
PROC_FABRIC_A_ATTACHED_CHIP_CNFG
PROC_FABRIC_X_ATTACHED_CHIP_CNFG
PROC_FABRIC_A_ATTACHED_CHIP_ID
PROC_FABRIC_X_ATTACHED_CHIP_ID
PROC_FABRIC_A_ADDR_DIS
PROC_FABRIC_X_ADDR_DIS
UNIT_TEST_MCA_MEMORY_SIZES
PROC_FABRIC_OPTICS_CONFIG_MODE
PROC_FABRIC_A_AGGREGATE
PROC_FABRIC_X_AGGREGATE
XIVE_HW_RESET
DISABLE_I2C_ENGINE2_PORT0_DIAG_MODE
NDL_MESHCTRL_SETUP
unit
base
CLASS
UNIT
MRU_ID
PRIMARY_CAPABILITIES
supportsFsiScom1
supportsXscom1
supportsInbandScom0
reserved0
CHIP_UNIT
0
CHIPLET_ID
REL_POS
chip-membuf-centaur
chip
TYPE
MEMBUF
MODEL
CENTAUR
PRIMARY_CAPABILITIES
supportsFsiScom1
supportsXscom0
supportsInbandScom1
reserved0
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000003
SCOM_SWITCHES
useSbeScom1
useFsiScom0
useXscom0
useInbandScom0
reserved0
EEPROM_VPD_PRIMARY_INFO
I2C_BUS_SPEED_ARRAY
0,0,0,0,0,400,0,400,400,0,0,0,0,0,0,0
MSS_FREQ
MSS_LAB_OVERRIDE_FOR_MEM_PLL
ECID
CENTAUR_ECID_FRU_ID
0xFF
MRW_MEM_SENSOR_CACHE_ADDR_MAP
FSI_GP_REG_SCOM_ACCESS
0
CHIP_HAS_SBE
0
MSS_CACHE_ENABLE
EI_BUS_TX_LANE_INVERT
SBE_SEEPROM_I2C_ADDRESS_BYTES
SBE_SEEPROM_I2C_DEVICE_ADDRESS
SBE_SEEPROM_I2C_PORT
PNOR_I2C_ADDRESS_BYTES
VPD_REC_NUM
MSS_PSRO
MSS_NWELL_MISPLACEMENT
EI_BUS_TX_MSBSWAP
MSS_FREQ_OVERRIDE
MEMB_TP_BNDY_PLL_SCAN_SELECT
MSS_FREQ_BIAS_PERCENTAGE
CDIMM_SENSOR_MAP_PRIMARY
CDIMM_SENSOR_MAP_SECONDARY
MSS_BLUEWATERFALL_BROKEN
DMI_DFE_OVERRIDE
MSS_INIT_STATE
MSS_NEST_CAPABLE_FREQUENCIES
MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT
MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE
MSS_VOLT_OVERRIDE
I2C_SWITCHES
useFsiI2C1
useHostI2C0
reserved0
CDM_DOMAINMEM
FRU_ID
MSS_VREF_CAL_CNTL
card
base
CLASS
CARD
lcard-dimm
card
TYPE
DIMM
CLASS
LOGICAL_CARD
POSITION
MBA_PORT
MBA_DIMM
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000003
EEPROM_VPD_PRIMARY_INFO
TEMP_SENSOR_I2C_CONFIG
VPD_REC_NUM
MSS_EFF_VPD_VERSION
CDM_DOMAINDIMM
FRU_ID
SPD_OVERRIDE_ENABLE
SPD_OVERRIDE
REL_POS
lcard-dimm-jedec
lcard-dimm
MODELJEDEC
CEN_DQ_TO_DIMM_CONN_DQ
lcard-dimm-cdimm
lcard-dimm
MODELCDIMM
lcard-dimm-ddr4
lcard-dimm
occ
unit
TYPE
OCC
MODEL
POWER9
OCC_MASTER_CAPABLE
FRU_ID
sys-sys-power9
base
CLASSSYS
TYPESYS
MODELPOWER9
HUID0x00010000
EXECUTION_PLATFORM
PHYS_PATH
physical:sys-0
SCRATCH_UINT8_1
SCRATCH_UINT8_2
SCRATCH_UINT32_1
SCRATCH_UINT32_2
SCRATCH_UINT64_1
SCRATCH_UINT64_2
SCRATCH_UINT8_ARRAY_1
SCRATCH_UINT8_ARRAY_2
SCRATCH_UINT32_ARRAY_1
SCRATCH_UINT32_ARRAY_2
SCRATCH_UINT64_ARRAY_1
SCRATCH_UINT64_ARRAY_2
SCRATCH_INT8_1
SCRATCH_INT8_2
SCRATCH_INT32_1
SCRATCH_INT32_2
SCRATCH_INT64_1
SCRATCH_INT64_2
SCRATCH_INT8_ARRAY_1
SCRATCH_INT8_ARRAY_2
SCRATCH_INT32_ARRAY_1
SCRATCH_INT32_ARRAY_2
SCRATCH_INT64_ARRAY_1
SCRATCH_INT64_ARRAY_2
AFFINITY_PATH
affinity:sys-0
XSCOM_BASE_ADDRESS
IS_SIMULATION
0
HB_HRMOR_NODAL_BASE
TPM_REQUIRED
MSS_MRW_SUPPORTED_FREQ
MAX_PROC_CHIPS_PER_NODE
MAX_EXS_PER_PROC_CHIP
MAX_CHIPLETS_PER_PROC
43
MAX_MCS_PER_SYSTEM
TEST_NEGATIVE_FCN
RECONFIGURE_LOOP
RECONFIG_LOOP_TESTS
MULTI_SCOM_BUFFER_MAX_SIZE
ISTEP_PAUSE_ENABLE
ISTEP_PAUSE_CONFIG
FRU_ID
BMC_FRU_ID
PROC_REFCLOCK_RCVR_TERM
PCI_REFCLOCK_RCVR_TERM
DD1_SLOW_PCI_REF_CLOCK
MIN_FREQ_MHZ
DPO_MIN_FREQ_PERCENT
FREQ_PROC_REFCLOCK
FREQ_PROC_REFCLOCK_KHZ
FREQ_MEM_REFCLOCK
MAX_ALLOWED_DIMM_FREQ
REQUIRED_SYNCH_MODE
BOOT_FREQ_MHZ
FREQ_A_MHZ
FREQ_PB_MHZ
ASYNC_NEST_FREQ_MHZ
FREQ_PCIE_MHZ
FREQ_X_MHZ
MSS_MBA_ADDR_INTERLEAVE_BIT
MSS_MBA_CACHELINE_INTERLEAVE_MODE
PROC_EPS_TABLE_TYPE
PROC_FABRIC_PUMP_MODE
X_EREPAIR_THRESHOLD_FIELD
A_EREPAIR_THRESHOLD_FIELD
DMI_EREPAIR_THRESHOLD_FIELD
X_EREPAIR_THRESHOLD_MNFG
A_EREPAIR_THRESHOLD_MNFG
DMI_EREPAIR_THRESHOLD_MNFG
MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA
MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP
MSS_MRW_THERMAL_MEMORY_POWER_LIMIT
EXTERNAL_VRM_TRANSITION_START_NS
EXTERNAL_VRM_TRANSITION_RATE_INC_UV_PER_US
EXTERNAL_VRM_TRANSITION_RATE_DEC_UV_PER_US
EXTERNAL_VRM_TRANSITION_STABILIZATION_TIME_NS
EXTERNAL_VRM_STEPSIZE
EXTERNAL_VRM_STEPDELAY
PM_SPIVID_FREQUENCY
PM_SAFE_FREQUENCY
PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY
PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY
PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY
PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY
PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY
SPIPSS_FREQUENCY
MEM_MIRROR_PLACEMENT_POLICY
MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT
MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE
MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS
MRW_MEM_THROTTLE_DENOMINATOR
MSS_MRW_MAX_DRAM_DATABUS_UTIL
MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE
MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE
MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE
MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR
MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS
SYSTEM_IVRMS_ENABLED
PM_SYSTEM_IVRM_VPD_MIN_LEVEL
MRW_STRICT_MBA_PLUG_RULE_CHECKING
MNFG_DMI_MIN_EYE_WIDTH
MNFG_DMI_MIN_EYE_HEIGHT
MNFG_ABUS_MIN_EYE_WIDTH
MNFG_ABUS_MIN_EYE_HEIGHT
MNFG_XBUS_MIN_EYE_WIDTH
REDUNDANT_CLOCKS
MSS_DRAMINIT_RESET_DISABLE
MSS_MRW_POWER_CONTROL_REQUESTED
MNFG_TH_P8EX_L2_CACHE_CES
MNFG_TH_P8EX_L2_DIR_CES
MNFG_TH_P8EX_L3_CACHE_CES
MNFG_TH_P8EX_L3_DIR_CES
FIELD_TH_P8EX_L2_LINE_DELETES
FIELD_TH_P8EX_L3_LINE_DELETES
FIELD_TH_P8EX_L2_COL_REPAIRS
FIELD_TH_P8EX_L3_COL_REPAIRS
MNFG_TH_P8EX_L2_LINE_DELETES
MNFG_TH_P8EX_L3_LINE_DELETES
MNFG_TH_P8EX_L2_COL_REPAIRS
MNFG_TH_P8EX_L3_COL_REPAIRS
MNFG_TH_CEN_MBA_RT_SOFT_CE_TH_ALGO
MNFG_TH_CEN_MBA_IPL_SOFT_CE_TH_ALGO
MNFG_TH_CEN_MBA_RT_RCE_PER_RANK
MNFG_TH_CEN_L4_CACHE_CES
MNFG_TH_RCD_PARITY_ERRORS
MNFG_TH_MEMORY_IUES
MNFG_TH_MEMORY_IMPES
RCD_PARITY_RECONFIG_LOOPS_ALLOWED
RCD_PARITY_RECONFIG_LOOP_COUNT
OPT_MEMMAP_GROUP_POLICY
BRAZOS_RX_FIFO_OVERRIDE
MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL
MAX_PROC_CHIPS_PER_NODE
MAX_EXS_PER_PROC_CHIP
MAX_MBAS_PER_MEMBUF_CHIP
MAX_MBA_PORTS_PER_MBA
MAX_DIMMS_PER_MBA_PORT
MAX_CHIPLETS_PER_PROC
MAX_MCS_PER_SYSTEM
FABRIC_TO_PHYSICAL_NODE_MAP
RUN_MAX_MEM_PATTERNS
HIDDEN_ERRLOGS_ENABLE
SP_FUNCTIONS
HB_SETTINGS
CEC_IPL_TYPE
PAYLOAD_KIND
PAYLOAD_BASE
PAYLOAD_ENTRY
MFG_TRACE_ENABLE
ENABLED_THREADS
ISTEP_MODE
RECONFIG_LOOP_TESTS_ENABLE
ISTEP_PAUSE_ENABLE
ISTEP_PAUSE_CONFIG
CDM_POLICIES
HOSTSVC_PLID
NOMINAL_FREQ_MHZ
MNFG_FLAGS
FABRIC_TO_PHYSICAL_NODE_MAP
MFG_TRACE_ENABLE
NUMERIC_POD_TYPE_TEST
DUMMY_RW
TEST_NULL_STRING
TEST_MIN_STRINGZ
TEST_MAX_STRING
TEST_NO_DEFAULT_STRING
SYNC_BETWEEN_STEPS
DO_ABUS_DECONFIG
PLCK_IPL_ATTR_OVERRIDES_EXIST
PAYLOAD_IN_MIRROR_MEM
FUSED_CORE_OPTION
FUSED_CORE_MODE
MIRROR_BASE_ADDRESS
EFFECTIVE_EC
HB_RSV_MEM_SIZE_MB
FREQ_CORE_MAX
THREAD_COUNT
PFET_POWERUP_DELAY_NS
PFET_POWERDOWN_DELAY_NS
PFET_VDD_VOFF_SEL
PFET_VCS_VOFF_SEL
SYSTEM_IPL_PHASE
FREQ_CORE_CEILING_MHZ
ULTRA_TURBO_FREQ_MHZ
SOCKET_POWER_NOMINAL
SOCKET_POWER_TURBO
PROC_FABRIC_A_BUS_WIDTH
PROC_FABRIC_X_BUS_WIDTH
PROC_FABRIC_CCSM_MODE
PROC_FABRIC_SMP_OPTICS_MODE
PROC_FABRIC_CAPI_MODE
HDAT_RSV_MEM_NUM_SECTIONS
HDAT_HBRT_NUM_SECTIONS
HDAT_HBRT_SECTION_SIZE
PIB_I2C_REFCLOCK
PIB_I2C_NEST_PLL
MSS_MRW_PREFETCH_ENABLE
MSS_MRW_CLEANER_ENABLE
MRW_DRAMINIT_RESET_DISABLE
MSS_VDDR_OVERIDE_SPD
MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT
MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_SLOT
MSS_MRW_THERMAL_MEMORY_POWER_LIMIT
MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT
MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE
MSS_MRW_MEM_M_DRAM_CLOCKS
MSS_MRW_MAX_DRAM_DATABUS_UTIL
MSS_MRW_MCS_PREFETCH_RETRY_THRESHOLD
MSS_MRW_POWER_CONTROL_REQUESTED
MSS_MRW_IDLE_POWER_CONTROL_REQUESTED
MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE
MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR
MSS_MRW_AVDD_OFFSET_DISABLE
MSS_MRW_VDD_OFFSET_DISABLE
MSS_MRW_VCS_OFFSET_DISABLE
MSS_MRW_VPP_OFFSET_DISABLE
MSS_MRW_VDDR_OFFSET_DISABLE
MSS_MRW_FINE_REFRESH_MODE
MSS_MRW_TEMP_REFRESH_RANGE
MSS_MRW_RESET_DELAY_BEFORE_CAL
MSS_MRW_DRAM_2N_MODE
MRW_HW_MIRRORING_ENABLE
SBE_UPDATE_DISABLE
BOOT_FLAGS
NEST_PLL_BUCKET
NEST_PLL_FREQ_BUCKETS
NEST_PLL_FREQ_LIST
NEST_PLL_FREQ_I2CDIV_LIST
RISK_LEVEL
SYS_FORCE_ALL_CORES
DISABLE_HBBL_VECTORS
SECURITY_ENABLE
PIBMEM_REPAIR0
PIBMEM_REPAIR1
PIBMEM_REPAIR2
PROC_FABRIC_CORE_FLOOR_RATIO
PROC_FABRIC_CORE_CEILING_RATIO
PROC_EPS_GB_PERCENTAGE
PROC_EPS_READ_CYCLES_T0
PROC_EPS_READ_CYCLES_T1
PROC_EPS_READ_CYCLES_T2
PROC_EPS_WRITE_CYCLES_T1
PROC_EPS_WRITE_CYCLES_T2
MSS_VOLT_DDR3_VDDR_SLOPE
MSS_VOLT_DDR3_VDDR_INTERCEPT
MSS_VOLT_DDR4_VDDR_SLOPE
MSS_VOLT_DDR4_VDDR_INTERCEPT
MRW_DDR3_VDDR_MAX_LIMIT
MRW_DDR4_VDDR_MAX_LIMIT
MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT
MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT
MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT
MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT
MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT
MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT
MSS_VOLT_VPP_SLOPE
MSS_VOLT_VPP_INTERCEPT
MSS_INTERLEAVE_ENABLE
MSS_INTERLEAVE_GRANULARITY
SUPPORTS_DYNAMIC_MEM_VOLT
MSS_VDD_PROGRAM
MSS_AVDD_PROGRAM
MSS_VCS_PROGRAM
MSS_VPP_PROGRAM
MSS_VDDR_PROGRAM
PROC_PCIE_MMIO_BAR0_BASE_ADDR_OFFSET
PROC_PCIE_MMIO_BAR1_BASE_ADDR_OFFSET
PROC_PCIE_REGISTER_BAR_BASE_ADDR_OFFSET
PROC_XSCOM_BAR_BASE_ADDR_OFFSET
PROC_LPC_BAR_BASE_ADDR_OFFSET
PROC_PCIE_BAR_SIZE
PROC_FSP_BAR_BASE_ADDR_OFFSET
PROC_FSP_BAR_SIZE
PROC_PSI_BRIDGE_BAR_BASE_ADDR_OFFSET
PROC_NPU_PHY0_BAR_BASE_ADDR_OFFSET
PROC_NPU_PHY1_BAR_BASE_ADDR_OFFSET
PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET
PROC_NX_RNG_BAR_BASE_ADDR_OFFSET
PROC_FSP_MMIO_MASK_SIZE
PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET
PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET_MASK
PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET
PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET_MASK
PROC_INT_CQ_TM1_BAR_BASE_ADDR_OFFSET
PROC_INT_CQ_TM1_BAR_PAGE_SIZE
PROC_INT_CQ_IC_BAR_BASE_ADDR_OFFSET
PROC_INT_CQ_IC_BAR_PAGE_SIZE
VDM_DROOP_SMALL_OVERRIDE
VDM_DROOP_LARGE_OVERRIDE
VDM_DROOP_EXTREME_OVERRIDE
VDM_OVERVOLT_OVERRIDE
VDM_FMAX_OVERRIDE_KHZ
VDM_FMIN_OVERRIDE_KHZ
VDM_VID_COMPARE_OVERRIDE_MV
IVRM_DEADZONE_MV
PM_SAFE_FREQUENCY_MHZ
PM_SAFE_VOLTAGE_MV
MSS_MRW_OFFSET_WLO
MSS_MRW_OFFSET_GPO
MSS_MRW_OFFSET_RLO
MSS_MRW_TSYS_DATA
MSS_MRW_TSYS_ADR
FSP_BAR_SIZE
MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4
MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR3
STOP11_DISABLE
SYSTEM_RESCLK_STEP_DELAY
DPLL_DROOP_PROTECT_ENABLE
DPLL_DYNAMIC_FMIN_ENABLE
DPLL_DYNAMIC_FMAX_ENABLE
DPLL_VDM_RESPONSE
MSS_VMEM_REGULATOR_MAX_DIMM_COUNT
SYSTEM_WOF_ENABLED
WOF_VRATIO_SELECT
WOF_ENABLE_VRATIO
WOF_ENABLE_FRATIO
WOF_POWER_LIMIT
SYS_VFRT_STATIC_DATA_ENABLE
WOF_TABLE_LID_NUMBER
AVSBUS_FREQUENCY
PROC_FABRIC_ASYNC_SAFE_MODE
VDM_ENABLE
STOP8_DISABLE
STOP4_DISABLE
STOP5_DISABLE
SUPPORTED_STOP_STATES
SYSTEM_FAMILY
SYSTEM_TYPE
MSS_CAL_ABORT_ON_ERROR
SBE_IMAGE_MINIMUM_VALID_ECS
MAX_SBE_SEEPROM_SIZE
SBE_SYS_CONFIG
CP_REFCLOCK_RCVR_TERM
IO_REFCLOCK_RCVR_TERM
MSS_MRW_PWR_INTERCEPT
MSS_MRW_PWR_SLOPE
IVRM_STRENGTH_LOOKUP
IVRM_VIN_MULTIPLIER
IVRM_VIN_MAX_MV
IVRM_STEP_DELAY_NS
IVRM_STABILIZATION_DELAY_NS
SYSTEM_RESCLK_ENABLE
MSS_MRW_REFRESH_RATE_REQUEST
MSS_MRW_TEMP_REFRESH_MODE
MSS_VCCD_OVERRIDE
RAW_MTM
MSS_MEM_PORT_POS_OF_FAIL_THROTTLE
SYSTEM_RING_DBG_MODE
NEST_LEAKAGE_PERCENT
MSS_MRW_DRAM_WRITE_CRC
POUND_W_STATIC_DATA_ENABLE
PGPE_HCODE_FUNCTION_ENABLE
SYSTEM_DISABLE_QUEUED_SCAN
PERF_24x7_INVOCATION_TIME_MS
AUX_FUNC_INVOCATION_TIME_MS
enc-node-power9
base
CLASS
ENC
TYPE
NODE
MODEL
POWER9
FIELD_CORE_OVERRIDE
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000009
CDM_DOMAINNODE
FRU_ID
EEPROM_VPD_PRIMARY_INFO
MSS_VOLT_VPP_SLOPE_EFF_CONFIG
MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG
MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG
MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG
MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG
MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG
MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG
MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG
HDAT_RSV_MEM_NUM_SECTIONS
HDAT_HBRT_NUM_SECTIONS
HDAT_HBRT_SECTION_SIZE
VPD_REC_NUM
chip-tpm-cectpm
chip
TYPE
TPM
MODEL
CECTPM
TPM_INFO
chip-processor-power9
chip-processor
DUMMY_RW
DUMMY_HEAP_ZERO_DEFAULT
MSS_MEM_MC_IN_GROUP
EEPROM_VPD_PRIMARY_INFO
EEPROM_VPD_BACKUP_INFO
EEPROM_SBE_PRIMARY_INFO
EEPROM_SBE_BACKUP_INFO
I2C_BUS_SPEED_ARRAY
0,0,0,0,0,0,0,0,0,0,0,0
NPU_MMIO_BAR_BASE_ADDR
NPU_MMIO_BAR_SIZE
FSP_BASE_ADDR
FSP_BAR_SIZE
PSI_BRIDGE_BASE_ADDR
INTP_BASE_ADDR
PHB_BASE_ADDRS
PCI_BASE_ADDRS_64
PCI_BASE_ADDRS_32
MEM_BASE
MIRROR_BASE
RNG_BAR_SIZE
IMT_BASE_ADDR
IMT_BAR_SIZE
VAS_HYPERVISOR_WINDOW_CONTEXT_ADDR
VAS_USER_WINDOW_CONTEXT_ADDR
LPC_BUS_ADDR
NVIDIA_NPU_PRIVILEGED_ADDR
NVIDIA_NPU_USER_REG_ADDR
NVIDIA_PHY0_REG_ADDR
NVIDIA_PHY1_REG_ADDR
XIVE_CONTROLLER_BAR_ADDR
PSI_HB_ESB_ADDR
XIVE_THREAD_MGMT1_BAR_ADDR
NX_RNG_ADDR
ECID
I2C_SLAVE_ADDRESS
PROC_PCIE_NUM_PHB
6
PROC_PCIE_NUM_IOP
3
PROC_PCIE_NUM_PEC
3
PROC_PCIE_NUM_LANES
48
PROC_PCIE_PHB_ACTIVE
PROC_DCM_INSTALLED
XSCOM_BASE_ADDRESS
PSTATEGPE_BOOT_COPIER_IVPR_OFFSET
STOPGPE_BOOT_COPIER_IVPR_OFFSET
EQ_GARD
EC_GARD
I2C_BUS_DIV_REF
I2C_BUS_DIV_REF_VALID
NODE_POS
BOOT_FREQ
VCS_BOOT_VOLTAGE
VDN_BOOT_VOLTAGE
VDD_BOOT_VOLTAGE
VDD_AVSBUS_RAIL
VDD_AVSBUS_BUSNUM
VDN_AVSBUS_RAIL
VDN_AVSBUS_BUSNUM
VCS_AVSBUS_RAIL
VCS_AVSBUS_BUSNUM
CHIP_POS
CLOCK_PLL_MUX
CLOCK_PLL_MUX0
BOOT_FREQ_MULT
PFET_OFF_CONTROLS
MC_SYNC_MODE
CDM_DOMAINFABRIC
OBUS_RATIO_VALUE
FUNCTIONAL_EQ_EC_VALID
FW_MODE_FLAGS_VALID
ISTEP_MODE
SBE_RUNTIME_MODE
IS_SP_MODE
SBE_FFDC_ENABLE
SBE_INTERNAL_FFDC_ENABLE
BOOT_FREQUENCY_VALID
HWP_CONTROL_FLAGS_VALID
CHIP_SELECTION_VALID
CHIP_SELECTION
SCRATCH6_VALID
SCRATCH7_VALID
OCC_LFIR
PBA_LFIR
EXTERNAL_VRM_STEPSIZE
EXTERNAL_VRM_STEPDELAY
AVSBUS_FREQUENCY
PROC_FABRIC_X_ATTACHED_LINK_ID
PROC_FABRIC_X_ATTACHED_CHIP_ID
PROC_FABRIC_A_ATTACHED_LINK_ID
PROC_FABRIC_A_ATTACHED_CHIP_ID
PROC_FABRIC_X_LINK_DELAY
PROC_FABRIC_X_ADDR_DIS
PROC_FABRIC_X_AGGREGATE
PROC_FABRIC_A_LINK_DELAY
PROC_FABRIC_A_ADDR_DIS
PROC_FABRIC_A_AGGREGATE
SCRATCH_UINT8_15
PROC_NHTM_BAR_BASE_ADDR
PROC_NHTM_BAR_SIZE
PROC_CHTM_BAR_BASE_ADDR
PROC_CHTM_BAR_SIZES
NHTM_TRACE_TYPE
CHTM_TRACE_TYPE
HTMSC_TTYPEFILT_PAT
HTMSC_TSIZEFILT_PAT
HTMSC_TTYPEFILT_MASK
HTMSC_TSIZEFILT_MASK
HTMSC_TTYPEFILT_INVERT
HTMSC_CRESPFILT_INVERT
HTMSC_FILT_PAT
HTMSC_FILT_CRESP_PAT
HTMSC_FILT_MASK
HTMSC_FILT_CRESP_MASK
NHTM_HTMSC_MODE_CONTENT_SEL
NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES
NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL
NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE
NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION
NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD
NHTM_HTMSC_MODE_SYNC_STAMP_FORCE
NHTM_HTMSC_MODE_WRITETOIO
CHTM_HTMSC_MODE_CONTENT_SEL
CHTM_HTMSC_MODE_CAPTURE
CHTM_HTMSC_MODE_CORE_INSTR_STALL
HTMSC_MODE_WRAP
HTMSC_MODE_DIS_TSTAMP
HTMSC_MODE_SINGLE_TSTAMP
HTMSC_MODE_MARKERS_ONLY
HTMSC_MODE_DIS_FORCE_GROUP_SCOPE
HTMSC_MODE_VGTARGET
HTMSC_MEM_SCOPE
HTMSC_MEM_PRIORITY
NHTM_CTRL_TRIG
NHTM_CTRL_MARK
CHTM_CTRL_TRIG
CHTM_CTRL_MARK
HTMSC_CTRL_DBG0_STOP
HTMSC_CTRL_DBG1_STOP
HTMSC_CTRL_RUN_STOP
HTMSC_CTRL_OTHER_DBG0_STOP
HTMSC_CTRL_XSTOP_STOP
HTMSC_CTRL_CHIP0_STOP
HTMSC_CTRL_CHIP1_STOP
HTMSC_IMA_PDBAR_SPLIT_CORE_MODE
HTMSC_IMA_PDBAR_SCOPE
HTMSC_IMA_PDBAR_ADDR
PROC_FABRIC_SYSTEM_ID
PROC_OCC_SANDBOX_BASE_ADDR
CP_FILTER_BYPASS
SS_FILTER_BYPASS
IO_FILTER_BYPASS
DUMP_STOP_INFO_SUPPRESS_ERROR_TRACE
DUMP_STOP_INFO_ENABLE_ERRORLOG
SBE_IS_STARTED
HTM_QUEUES
DATA_CACHE_SIZE
32
L3_CACHE_SIZE
10240
ICACHE_ASSOC_SETS
8
TLB_DATA_ENTRIES
1024
TLB_INSTR_ENTRIES
0
TLB_DATA_ASSOC_SETS
4
TLB_INSTR_ASSOC_SETS
0
TLB_RESERVE_SIZE
128
DATA_CACHE_LINE_SIZE
128
L3_CACHE_LINE_SIZE
128
DCACHE_LINE_SIZE
128
DCACHE_ASSOC_SETS
8
ICACHE_BLOCK_SIZE
128
ICACHE_SIZE
32
ICACHE_LINE_SIZE
128
CPU_ATTR
0x0000001D
L2_CACHE_LINE_SIZE
128
L2_CACHE_SIZE
512
L2_CACHE_ASSOC_SETS
8
LPC_BASE_ADDR
BOOT_FREQ_MHZ
PROC_NPU_PHY0_BAR_ENABLE
PROC_NPU_PHY1_BAR_ENABLE
PROC_NPU_MMIO_BAR_ENABLE
PROC_NX_RNG_BAR_ENABLE
PROC_FSP_BAR_ENABLE
PROC_PSI_BRIDGE_BAR_ENABLE
PROC_INT_CQ_PC_BAR_ENABLE
PROC_INT_CQ_VC_BAR_ENABLE
PROC_INT_CQ_TM1_BAR_ENABLE
PROC_INT_CQ_IC_BAR_ENABLE
PROC_NX_RNG_FAILED_INT_ENABLE
PROC_NX_RNG_FAILED_INT_ADDR
NEST_MEM_X_O_PCI_BYPASS
DPLL_BYPASS
FREQ_BIAS_ULTRATURBO
FREQ_BIAS_TURBO
FREQ_BIAS_NOMINAL
FREQ_BIAS_POWERSAVE
VOLTAGE_EXT_VDD_BIAS_ULTRATURBO
VOLTAGE_EXT_VDD_BIAS_TURBO
VOLTAGE_EXT_VDD_BIAS_NOMINAL
VOLTAGE_EXT_VDD_BIAS_POWERSAVE
VOLTAGE_EXT_VCS_BIAS
VOLTAGE_EXT_VDN_BIAS
VOLTAGE_INT_VDD_BIAS_ULTRATURBO
VOLTAGE_INT_VDD_BIAS_TURBO
VOLTAGE_INT_VDD_BIAS_NOMINAL
VOLTAGE_INT_VDD_BIAS_POWERSAVE
TDP_RDP_CURRENT_FACTOR
SYSTEM_RESCLK_FREQ_REGIONS
SYSTEM_RESCLK_FREQ_REGION_INDEX
SYSTEM_RESCLK_VALUE
SYSTEM_RESCLK_L3_VALUE
SYSTEM_RESCLK_L3_VOLTAGE_THRESHOLD_MV
NEST_VDD_ID
NEST_VDN_ID
NEST_VCS_ID
NEST_VIO_ID
NEST_VDDR_ID
MSS_FREQ
WAIT_N2
WAIT_N1
WAIT_N0
START_SEEPROM_ADDR
MASTER_CORE
MASTER_EX
CHIP_REGIONS_TO_ENABLE
PROC_PB_BNDY_DMIPLL_DATA
MB_BIT_RATE_DIVISOR_PLL
LEN_OF_SEEPROM_DATA
BRANCH_PIBMEM_ADDR
I2C_BUS_DIV_NEST
VCS_I2C_RAIL
START_PIBMEM_ADDR
VCS_I2C_BUSNUM
PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA
MB_BIT_RATE_DIVISOR_REFCLK
WAIT_N3
PROC_PERV_BNDY_PLL_DATA
DEVICE_ID
TOD_CPU_DATA
PM_SPWUP_IGNORE_XSTOP_FLAG
SECUREBOOT_PROTECT_DECONFIGURED_TPM
CME_INSTRUCTION_TRACE_ENABLE
MSS_RUN_DCD_CALIBRATION
DO_MSS_WR_VREF
DO_MSS_VREF_DAC
DO_MSS_TRAINING_BAD_BITS
CME_CHTM_TRACE_ENABLE
CME_CHTM_TRACE_MEMORY_CONFIG
PRD_HWP_PLID
chip-processor-nimbus
chip-processor-power9
MODEL
NIMBUS
chip-processor-cumulus
chip-processor-power9
MODEL
CUMULUS
unit-eq-power9
unit
TYPE
EQ
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
SCRATCH_UINT8_15
POUNDV_BUCKET_NUM0
POUNDV_BUCKET_NUM_OVERRIDE0
PARENT_PERVASIVE
CDM_DOMAINCPU
QUAD_PPM_ERRMASK
SENSEADJ_STEP
unit-ex-power9
unit
TYPE
EX
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
SCRATCH_UINT8_15
CDM_DOMAINCPU
CME_LOCAL_FIRMASK
L2_HASCLOCKS
L3_HASCLOCKS
C0_EXEC_HASCLOCKS
C1_EXEC_HASCLOCKS
C0_PC_HASCLOCKS
C1_PC_HASCLOCKS
L2_HASPOWER
L3_HASPOWER
C0_HASPOWER
C1_HASPOWER
unit-core-power9
unit
TYPE
CORE
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
SCRATCH_UINT8_15
PARENT_PERVASIVE
CDM_DOMAINCPU
CORE_PPM_ERRMASK
unit-mcs-power9
unit
TYPE
MCS
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000003
EEPROM_VPD_PRIMARY_INFO
IBSCOM_MCS_BASE_ADDR
EI_BUS_TX_MSBSWAP
SCRATCH_UINT8_15
PARENT_PERVASIVE
MSS_DIMM_MFG_ID_CODE
EFF_NUM_RANKS_PER_DIMM
EFF_DRAM_WIDTH
EFF_DRAM_RANK_MIX
EFF_DIMM_SPARE
EFF_DRAM_WR_VREF
EFF_DRAM_WR_VREF_SCHMOO
EFF_DRAM_WRDDR4_VREF_SCHMOO
EFF_DIMM_SIZE
EFF_DRAM_CL
EFF_DRAM_AL
EFF_DRAM_CWL
EFF_DRAM_RBT
EFF_DRAM_TM
EFF_DRAM_DLL_RESET
EFF_DRAM_DLL_PPD
EFF_DRAM_DLL_ENABLE
EFF_DRAM_WR_LVL_ENABLE
EFF_DRAM_OUTPUT_BUFFER
EFF_DRAM_PASR
EFF_DRAM_ASR
EFF_DRAM_SRT
EFF_MPR_LOC
EFF_MPR_MODE
EFF_DIMM_DDR4_RC00
EFF_DIMM_DDR4_RC01
EFF_DIMM_DDR4_RC02
EFF_DIMM_DDR4_RC03
EFF_DIMM_DDR4_RC04
EFF_DIMM_DDR4_RC05
EFF_DIMM_DDR4_RC06_07
EFF_DIMM_DDR4_RC08
EFF_DIMM_DDR4_RC09
EFF_DIMM_DDR4_RC10
EFF_DIMM_DDR4_RC11
EFF_DIMM_DDR4_RC12
EFF_DIMM_DDR4_RC13
EFF_DIMM_DDR4_RC14
EFF_DIMM_DDR4_RC15
EFF_DIMM_DDR4_RC0A
EFF_DIMM_DDR4_RC0B
EFF_DIMM_DDR4_RC0C
EFF_DIMM_DDR4_RC0D
EFF_DIMM_DDR4_RC0E
EFF_DIMM_DDR4_RC0F
EFF_DIMM_DDR4_RC_1x
EFF_DIMM_DDR4_RC_2x
EFF_DIMM_DDR4_RC_3x
EFF_DIMM_DDR4_RC_4x
EFF_DIMM_DDR4_RC_5x
EFF_DIMM_DDR4_RC_6x
EFF_DIMM_DDR4_RC_7x
EFF_DIMM_DDR4_RC_8x
EFF_DIMM_DDR4_RC_9x
EFF_DIMM_DDR4_RC_Ax
EFF_DIMM_DDR4_RC_Bx
EFF_DIMM_RCD_MIRROR_MODE
EFF_SCHMOO_MODE
EFF_SCHMOO_ADDR_MODE
EFF_SCHMOO_TEST_VALID
EFF_SCHMOO_PARAM_VALID
EFF_SCHMOO_WR_EYE_MIN_MARGIN
EFF_SCHMOO_RD_EYE_MIN_MARGIN
EFF_SCHMOO_DQS_CLK_MIN_MARGIN
EFF_SCHMOO_RD_GATE_MIN_MARGIN
EFF_SCHMOO_ADDR_CMD_MIN_MARGIN
EFF_MEMCAL_INTERVAL
EFF_ZQCAL_INTERVAL
EFF_IBM_TYPE
EFF_NUM_DROPS_PER_PORT
EFF_NUM_MASTER_RANKS_PER_DIMM
EFF_NUM_PACKAGES_PER_RANK
EFF_PRIM_DIE_COUNT
MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT
MSS_MEM_M_DRAM_CLOCKS
MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT
MSS_MEM_WATT_TARGET
MSS_MASTER_PWR_SLOPE
MSS_SUPPLIER_PWR_SLOPE
MSS_TOTAL_PWR_SLOPE
MSS_TOTAL_PWR_INTERCEPT
MSS_PORT_MAXPOWER
MSS_SUPPLIER_PWR_INTERCEPT
MSS_DIMM_MAXBANDWIDTH_GBS
MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS
MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS
MSS_DIMM_MAXPOWER
MSS_CHANNEL_PAIR_MAXPOWER
MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT
MSS_RUNTIME_MEM_M_DRAM_CLOCKS
MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT
MSS_EFF_DIMM_FUNCTIONAL_VECTOR
EFF_DRAM_LPASR
EFF_MPR_PAGE
EFF_GEARDOWN_MODE
EFF_PER_DRAM_ACCESS
EFF_TEMP_READOUT
EFF_CRC_WR_LATENCY
EFF_MPR_RD_FORMAT
EFF_MAX_POWERDOWN_MODE
EFF_TEMP_REFRESH_MODE
EFF_INTERNAL_VREF_MONITOR
EFF_CS_CMD_LATENCY
EFF_SELF_REF_ABORT
EFF_RD_PREAMBLE_TRAIN
EFF_RD_PREAMBLE
EFF_WR_PREAMBLE
EFF_CA_PARITY_LATENCY
EFF_CRC_ERROR_CLEAR
EFF_CA_PARITY_ERROR_STATUS
EFF_ODT_INPUT_BUFF
EFF_CA_PARITY
EFF_DATA_MASK
EFF_WRITE_DBI
EFF_READ_DBI
EFF_VREF_DQ_TRAIN_VALUE
EFF_VREF_DQ_TRAIN_RANGE
EFF_VREF_DQ_TRAIN_ENABLE
EFF_WRITE_CRC
MSS_CAL_STEP_ENABLE
MSS_SLEW_RATE_DATA
MSS_SLEW_RATE_ADR
SCHMOO_MULTIPLE_SETUP_CALL
EFF_BUFFER_LATENCY
EFF_LRDIMM_WORD_X
LRDIMM_MR12_REG
LRDIMM_ADDITIONAL_CNTL_WORDS
LRDIMM_RANK_MULT_MODE
MSS_THROTTLE_CONTROL_RAS_WEIGHT
MSS_THROTTLE_CONTROL_CAS_WEIGHT
MSS_EFF_VPD_VERSION
MSS_DATABUS_UTIL
MSS_THROTTLED_N_COMMANDS
EFF_DRAM_MAC
EFF_DRAM_MODULE_BUS_WIDTH
EFF_DIMM_DDR4_BC00
EFF_DIMM_DDR4_BC01
EFF_DIMM_DDR4_BC02
EFF_DIMM_DDR4_BC03
EFF_DIMM_DDR4_BC04
EFF_DIMM_DDR4_BC05
EFF_DIMM_DDR4_BC06
EFF_DIMM_DDR4_BC07
EFF_DIMM_DDR4_BC08
EFF_DIMM_DDR4_BC09
EFF_DIMM_DDR4_BC0A
EFF_DIMM_DDR4_BC0B
EFF_DIMM_DDR4_BC0C
EFF_DIMM_DDR4_BC0D
EFF_DIMM_DDR4_BC0E
EFF_DIMM_DDR4_BC0F
EFF_DIMM_DDR4_F0BC1x
EFF_DIMM_DDR4_F30BC2x
EFF_DIMM_DDR4_F30BC3x
EFF_DIMM_DDR4_F30BC4x
EFF_DIMM_DDR4_F30BC5x
EFF_DIMM_DDR4_F0BC6x
EFF_DIMM_DDR4_F70BC7x
EFF_DIMM_DDR4_F30BC8x
EFF_DIMM_DDR4_F30BC9x
EFF_DIMM_DDR4_F30BCAx
EFF_DIMM_DDR4_F30BCBx
EFF_DIMM_DDR4_F0BCCx
EFF_DIMM_DDR4_F0BCDx
EFF_DIMM_DDR4_F0BCEx
EFF_DIMM_DDR4_F0BCFx
EFF_DIMM_DDR4_F1BCCx
EFF_DIMM_DDR4_F1BCDx
EFF_DIMM_DDR4_F1BCEx
EFF_DIMM_DDR4_F1BCFx
EFF_DIMM_DDR4_F4BC0x
EFF_DIMM_DDR4_F4BC1x
EFF_DIMM_DDR4_F4BC2x
EFF_DIMM_DDR4_F4BC3x
EFF_DIMM_DDR4_F4BC4x
EFF_DIMM_DDR4_F4BC5x
EFF_DIMM_DDR4_F4BC6x
EFF_DIMM_DDR4_F5BC0x
EFF_DIMM_DDR4_F5BC1x
EFF_DIMM_DDR4_F5BC2x
EFF_DIMM_DDR4_F5BC3x
EFF_DIMM_DDR4_F5BC5x
EFF_DIMM_DDR4_F5BC6x
EFF_DIMM_DDR4_F6BC0x
EFF_DIMM_DDR4_F6BC1x
EFF_DIMM_DDR4_F6BC2x
EFF_DIMM_DDR4_F6BC3x
EFF_DIMM_DDR4_F6BC4x
EFF_DIMM_DDR4_F6BC5x
EFF_DIMM_DDR4_F74BC8x
EFF_DIMM_DDR4_F74BC9x
EFF_DIMM_DDR4_F74BCAx
EFF_DIMM_DDR4_F74BCBx
EFF_DIMM_DDR4_F74BCCx
EFF_DIMM_DDR4_F74BCDx
EFF_DIMM_DDR4_F74BCEx
EFF_DIMM_DDR4_F74BCFx
EFF_DRAM_RON
EFF_DRAM_RTT_NOM
EFF_DRAM_RTT_WR
EFF_DRAM_TDQS
EFF_DRAM_TREFI
EFF_DRAM_TRTP
EFF_DRAM_TRFC_DLR
EFF_DRAM_TFAW_DLR
EFF_DRAM_TXS
MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN
MSS_VPD_MR_DRAM_2N_MODE
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13
MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17
MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0
MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1
MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0
MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1
MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0
MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1
MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2
MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP
MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN
MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP
MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN
MSS_VPD_MR_MC_PHASE_ROT_CLK_D0_P0
MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15
MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16
MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14
MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR
MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0
MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1
MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0
MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1
MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0
MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1
MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0
MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1
MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0
MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1
MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0
MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1
VPD_MR_DRAM_2N_MODE
VPD_MR_MC_PHASE_ROT_ADDR_A00
VPD_MR_MC_PHASE_ROT_ADDR_A01
VPD_MR_MC_PHASE_ROT_ADDR_A02
VPD_MR_MC_PHASE_ROT_ADDR_A03
VPD_MR_MC_PHASE_ROT_ADDR_A04
VPD_MR_MC_PHASE_ROT_ADDR_A05
VPD_MR_MC_PHASE_ROT_ADDR_A06
VPD_MR_MC_PHASE_ROT_ADDR_A07
VPD_MR_MC_PHASE_ROT_ADDR_A08
VPD_MR_MC_PHASE_ROT_ADDR_A09
VPD_MR_MC_PHASE_ROT_ADDR_A10
VPD_MR_MC_PHASE_ROT_ADDR_A11
VPD_MR_MC_PHASE_ROT_ADDR_A12
VPD_MR_MC_PHASE_ROT_ADDR_A13
VPD_MR_MC_PHASE_ROT_ADDR_A17
VPD_MR_MC_PHASE_ROT_ADDR_BA0
VPD_MR_MC_PHASE_ROT_ADDR_BA1
VPD_MR_MC_PHASE_ROT_ADDR_BG0
VPD_MR_MC_PHASE_ROT_ADDR_C0
VPD_MR_MC_PHASE_ROT_ADDR_C1
VPD_MR_MC_PHASE_ROT_ADDR_C2
VPD_MR_MC_PHASE_ROT_D0_CLK0
VPD_MR_MC_PHASE_ROT_D0_CLK1
VPD_MR_MC_PHASE_ROT_D1_CLK0
VPD_MR_MC_PHASE_ROT_D1_CLK1
VPD_MR_MC_PHASE_ROT_CLK_D0_P0
VPD_MR_MC_PHASE_ROT_CLK_D0_P1
VPD_MR_MC_PHASE_ROT_CLK_D1_P0
VPD_MR_MC_PHASE_ROT_CLK_D1_P1
VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15
VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16
VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14
VPD_MR_MC_PHASE_ROT_CMD_PAR
VPD_MR_MC_PHASE_ROT_CNTL_CKE0
VPD_MR_MC_PHASE_ROT_CNTL_CKE1
VPD_MR_MC_PHASE_ROT_CNTL_CKE2
VPD_MR_MC_PHASE_ROT_CNTL_CKE3
VPD_MR_MC_PHASE_ROT_CNTL_CSN0
VPD_MR_MC_PHASE_ROT_CNTL_CSN1
VPD_MR_MC_PHASE_ROT_CNTL_CSN2
VPD_MR_MC_PHASE_ROT_CNTL_CSN3
VPD_MR_MC_PHASE_ROT_CNTL_ODT0
VPD_MR_MC_PHASE_ROT_CNTL_ODT1
VPD_MR_MC_PHASE_ROT_CNTL_ODT3
MSS_VPD_MR_MC_2N_MODE_AUTOSET
MSS_VPD_MR_PERIODIC_MEMCAL_MODE_OPTIONS
MSS_VPD_MR_TSYS_ADR
MSS_VPD_MR_TSYS_DATA
VPD_MR_PERIODIC_MEMCAL_MODE_OPTIONS
MSS_VPD_MT_CKE_PRI_MAP
MSS_VPD_MT_CKE_PWR_MAP
MSS_VPD_MT_DIMM_RCD_IBT_CA
MSS_VPD_MT_DIMM_RCD_IBT_CKE
MSS_VPD_MT_DIMM_RCD_IBT_CS
MSS_VPD_MT_DIMM_RCD_IBT_ODT
MSS_VPD_MT_PREAMBLE
MSS_VPD_MT_MC_DRV_IMP_CSCID
MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR
MSS_VPD_MT_DIMM_RCD_OUTPUT_TIMING
MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS
MSS_VPD_MT_DRAM_RTT_NOM
MSS_VPD_MT_DRAM_RTT_PARK
MSS_VPD_MT_DRAM_RTT_WR
MSS_VPD_MT_MC_DRV_IMP_CLK
MSS_VPD_MT_MC_DRV_IMP_CNTL
MSS_VPD_MT_MC_DRV_IMP_DQ_DQS
MSS_VPD_MT_MC_RCV_IMP_DQ_DQS
MSS_VPD_MT_MC_SLEW_RATE_ADDR
MSS_VPD_MT_MC_SLEW_RATE_CLK
MSS_VPD_MT_MC_SLEW_RATE_CNTL
MSS_VPD_MT_MC_SLEW_RATE_DQ_DQS
MSS_VPD_MT_MC_SLEW_RATE_SPCKE
MSS_VPD_MT_ODT_RD
MSS_VPD_MT_ODT_WR
MSS_VPD_MT_OFFSET_GPO
MSS_VPD_MT_OFFSET_RLO
MSS_VPD_MT_OFFSET_WLO
MSS_VPD_MT_VREF_DRAM_WR
MSS_VPD_MT_VREF_MC_RD
MSS_VPD_MT_WINDAGE_RD_CTR
VPD_MT_CKE_PRI_MAP
VPD_MT_CKE_PWR_MAP
VPD_MT_DIMM_RCD_IBT
VPD_MT_DIMM_RCD_OUTPUT_TIMING
VPD_MT_DRAM_DRV_IMP_DQ_DQS
VPD_MT_DRAM_RTT_NOM
VPD_MT_DRAM_RTT_PARK
VPD_MT_DRAM_RTT_WR
VPD_MT_MC_DRV_IMP_ADDR
VPD_MT_MC_DRV_IMP_CLK
VPD_MT_MC_DRV_IMP_CNTL
VPD_MT_MC_DRV_IMP_DQ_DQS
VPD_MT_MC_DRV_IMP_SPCKE
VPD_MT_MC_RCV_IMP_DQ_DQS
VPD_MT_MC_SLEW_RATE_ADDR
VPD_MT_MC_SLEW_RATE_CLK
VPD_MT_MC_SLEW_RATE_CNTL
VPD_MT_MC_SLEW_RATE_DQ_DQS
VPD_MT_MC_SLEW_RATE_SPCKE
VPD_MT_ODT_RD
VPD_MT_ODT_WR
VPD_MT_OFFSET_GPO
VPD_MT_OFFSET_RLO
VPD_MT_OFFSET_WLO
VPD_MT_VREF_DRAM_WR
VPD_MT_VREF_MC_RD
VPD_MT_WINDAGE_RD_CTR
MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP
MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN
MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP
MSS_VPD_MT_MC_DQ_CTLE_CAP
MSS_VPD_MT_MC_DQ_CTLE_RES
VPD_REC_NUM
EFF_DRAM_GEN
EFF_DIMM_TYPE
EFF_HYBRID_MEMORY_TYPE
EFF_HYBRID
EFF_DRAM_DENSITY
EFF_DRAM_BANK_BITS
EFF_DRAM_BANK_GROUP_BITS
EFF_DRAM_COLUMN_BITS
EFF_DRAM_ROW_BITS
EFF_PRIM_STACK_TYPE
EFF_DRAM_PPR
EFF_DRAM_SOFT_PPR
EFF_DRAM_TRCD
EFF_DRAM_TRP
EFF_DRAM_TRAS
EFF_DRAM_TRC
EFF_DRAM_TRFC
EFF_DRAM_TFAW
EFF_DRAM_TRRD_S
EFF_DRAM_TRRD_L
EFF_DRAM_TCCD_L
EFF_DRAM_TWR
EFF_DRAM_TWTR_S
EFF_DRAM_TWTR_L
EFF_DRAM_TMAW
CDM_DOMAINMEM
MEMVPD_POS
VPD_OVERRIDE_MT
VPD_OVERRIDE_MT_ENABLE
VPD_OVERRIDE_MR
VPD_OVERRIDE_MR_ENABLE
VPD_OVERRIDE_DQ
VPD_OVERRIDE_DQ_ENABLE
VPD_OVERRIDE_CK
VPD_OVERRIDE_CK_ENABLE
MSS_VPD_MT_0_VERSION_LAYOUT
MSS_VPD_MT_1_VERSION_DATA
MSS_VPD_MT_2_SIGNATURE_HASH
MSS_VPD_MR_0_VERSION_LAYOUT
MSS_VPD_MR_1_VERSION_DATA
MSS_VPD_MR_2_SIGNATURE_HASH
MSS_VPD_MR_DPHY_GPO
MSS_VPD_MR_DPHY_RLO
MSS_VPD_MR_DPHY_WLO
MSS_OCC_THROTTLED_N_CMDS
MSS_VPD_CKE_MAP
MSS_VPD_DQ_MAP
EFF_DIMM_RANKS_CONFIGED
MSS_DIMM_MAXBANDWIDTH_MRS
DMI_REFCLOCK_SWIZZLE
MSS_MASTER_PWR_INTERCEPT
MSS_IGNORE_PLUG_RULES
EFF_DRAM_MFG_ID
EFF_DRAM_TRRD_DLR
BAD_DQ_BITMAP
MSS_DIMM_THERMAL_LIMIT
MSS_VREF_CAL_ENABLE
MSS_MRW_UNSUPPORTED_RANK_CONFIG
MSS_RTT_NOM_OVERRIDE_DISABLE
EFF_DRAM_RTT_NOM
EFF_DRAM_RTT_WR
EFF_DRAM_RTT_PARK
EFF_RANK_GROUP_OVERRIDE
MSS_RDVREF_CAL_ENABLE
MSS_VREF_DAC_NIBBLE
MSS_MVPD_FWMS
MSS_PHY_SEQ_REFRESH
unit-mcs-nimbus
unit-mcs-power9
MODEL
NIMBUS
unit-mca-power9
unit
TYPE
MCA
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000003
SCRATCH_UINT8_15
PARENT_PERVASIVE
CDM_DOMAINMEM
VPD_OVERRIDE_MW_ENABLE
VPD_OVERRIDE_MW
PRD_HWP_PLID
unit-mca-nimbus
unit-mca-power9
MODEL
NIMBUS
unit-mcbist-power9
unit
TYPE
MCBIST
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000003
SCRATCH_UINT8_15
PARENT_PERVASIVE
MSS_FREQ
MSS_FREQ_OVERRIDE
MSS_VOLT_OVERRIDE
MSS_FREQ_BIAS_PERCENTAGE
MSS_NEST_CAPABLE_FREQUENCIES
CDM_DOMAINMEM
MSS_VOLT_VPP_MILLIVOLTS
MSS_VOLT_VDDR_MILLIVOLTS
MSS_VOLT_VCS_MILLIVOLTS
MSS_VOLT_VDD_MILLIVOLTS
MSS_VOLT_AVDD_MILLIVOLTS
MSS_VOLT_VPP_OFFSET_MILLIVOLTS
MSS_VOLT_VDDR_OFFSET_MILLIVOLTS
MSS_VOLT_VCS_OFFSET_MILLIVOLTS
MSS_VOLT_VDD_OFFSET_MILLIVOLTS
MSS_VOLT_AVDD_OFFSET_MILLIVOLTS
VPP_ID
VDDR_ID
VCS_ID
VDD_ID
AVDD_ID
MSS_REORDER_QUEUE_SETTING
unit-mcbist-nimbus
unit-mcbist-power9
MODEL
NIMBUS
unit-mi-power9
unit
TYPE
MI
DECONFIG_GARDABLE1
PARENT_PERVASIVE
unit-mi-cumulus
unit-mi-power9
MODEL
CUMULUS
unit-dmi-power9
unit
TYPE
DMI
DECONFIG_GARDABLE1
PARENT_PERVASIVE
EI_BUS_TX_MSBSWAP
unit-dmi-cumulus
unit-dmi-power9
MODEL
CUMULUS
unit-pec-power9
unit
TYPE
PEC
DECONFIG_GARDABLE1
SCRATCH_UINT8_15
PARENT_PERVASIVE
PROC_PCIE_IOVALID_ENABLE
PROC_PCIE_PCS_RX_CDR_GAIN
PROC_PCIE_PCS_RX_PK_INIT
PROC_PCIE_PCS_RX_INIT_GAIN
PROC_PCIE_PCS_RX_SIGDET_LVL
PROC_PCIE_PCS_RX_ROT_EXTEL
PROC_PCIE_PCS_RX_ROT_RST_FW
PROC_PCIE_PCS_RX_DFE_FDDC
PROC_PCIE_PCS_RX_LOFF_CONTROL
PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3
PROC_PCIE_PCS_RX_ROT_CDR_LOOKAHEAD
PROC_PCIE_PCS_RX_ROT_CDR_SSC
PROC_PCIE_PCS_PCLCK_CNTL_PLLA
PROC_PCIE_PCS_PCLCK_CNTL_PLLB
PROC_PCIE_PCS_TX_DCLCK_ROT
PROC_PCIE_PCS_TX_FIFO_CONFIG_OFFSET
PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG1
PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG2
PROC_PCIE_PCS_TX_POWER_SEQ_ENABLE
PROC_PCIE_PCS_RX_PHASE_ROTATOR_CNTL
PROC_PCIE_PCS_RX_VGA_CNTL_REG1
PROC_PCIE_PCS_RX_VGA_CNTL_REG2
PROC_PCIE_PCS_RX_SIGDET_CNTL
PROC_PCIE_PCS_SYSTEM_CNTL
PROC_PCIE_PCS_M_CNTL
PROC_PCIE_IOP_SWAP
PROC_PCIE_REFCLOCK_ENABLE
PROC_PCIE_IOP_CONFIG
CDM_DOMAINIO
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
PROC_PCIE_LANE_MASK
PEC_PCIE_LANE_MASK_NON_BIFURCATED
PEC_PCIE_LANE_MASK_BIFURCATED
PEC_PCIE_IOP_SWAP_NON_BIFURCATED
PEC_PCIE_IOP_SWAP_BIFURCATED
PEC_PCIE_IOP_REVERSAL
PEC_PCIE_IOP_REVERSAL_NON_BIFURCATED
PEC_PCIE_IOP_REVERSAL_BIFURCATED
unit-phb-power9
unit
TYPE
PHB
PROC_PCIE_NUM_LANES
48
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
SCRATCH_UINT8_15
PARENT_PERVASIVE
PROC_PCIE_BAR_ENABLE
PROC_PCIE_BAR_BASE_ADDR
PROC_PCIE_BAR_SIZE
CDM_DOMAINIO
PROC_PCIE_LANE_EQUALIZATION_GEN3
PROC_PCIE_LANE_EQUALIZATION_GEN4
unit-phb-nimbus
unit-phb-power9
MODEL
NIMBUS
unit-phb-cumulus
unit-phb-power9
MODEL
CUMULUS
unit-obus-power9
unit
TYPE
OBUS
DECONFIG_GARDABLE1
SCRATCH_UINT8_15
PARENT_PERVASIVE
OPTICS_CONFIG_MODE
PEER_TARGET
CDM_DOMAINFABRIC
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
unit-obus-nimbus
unit-obus-power9
MODEL
NIMBUS
unit-obus-cumulus
unit-obus-power9
MODEL
CUMULUS
unit-nv-power9
unit
TYPE
NV
DECONFIG_GARDABLE1
CDM_DOMAINFABRIC
SCRATCH_UINT8_15
PARENT_PERVASIVE
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
unit-nv-nimbus
unit-nv-power9
MODEL
NIMBUS
unit-nv-cumulus
unit-nv-power9
MODEL
CUMULUS
unit-ppe-power9
unit
TYPE
PPE
DECONFIG_GARDABLE0
SCRATCH_UINT8_15
unit-ppe-nimbus
unit-ppe-power9
MODEL
NIMBUS
unit-ppe-cumulus
unit-ppe-power9
MODEL
CUMULUS
unit-perv-power9
unit
TYPE
PERV
DECONFIG_GARDABLE0
SCRATCH_UINT8_15
PG5
TARGET_HAS_POWER
TARGET_HAS_CLOCK
TARGET_IS_SCOMMABLE
unit-perv-nimbus
unit-perv-power9
MODEL
NIMBUS
unit-perv-cumulus
unit-perv-power9
MODEL
CUMULUS
unit-xbus-power9
unit
TYPE
XBUS
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
CHIP_UNIT
PEER_TARGET
CDM_DOMAINFABRIC
SCRATCH_UINT8_15
PARENT_PERVASIVE
IO_XBUS_DCCAL_FLAGS
IO_X_DEBUG
IO_X_MFG_CHK
IO_X_MFG_MIN_EYE_WIDTH
IO_XBUS_MASTER_MODE
IO_XBUS_TX_MARGIN_RATIO
IO_XBUS_TX_FFE_PRECURSOR
EI_BUS_TX_MSBSWAP
unit-xbus-nimbus
unit-xbus-power9
MODEL
NIMBUS
unit-xbus-cumulus
unit-xbus-power9
MODEL
CUMULUS
unit-capp-power9
unit
TYPE
CAPP
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
PRIMARY_CAPABILITIES
supportsFsiScom0
supportsXscom0
supportsInbandScom0
reserved0
SCRATCH_UINT8_15
PARENT_PERVASIVE
CDM_DOMAINFABRIC
unit-capp-nimbus
unit-capp-power9
MODEL
NIMBUS
SCRATCH_UINT8_15
unit-capp-cumulus
unit-capp-power9
MODEL
CUMULUS
unit-sbe-power9
unit
TYPE
SBE
DECONFIG_GARDABLE0
SCRATCH_UINT8_15
unit-sbe-nimbus
unit-sbe-power9
MODEL
NIMBUS
unit-sbe-cumulus
unit-sbe-power9
MODEL
CUMULUS
unit-occ-power9
unit
TYPE
OCC
MODEL
POWER9
OCC_MASTER_CAPABLE
unit-occ-nimbus
unit-occ-power9
MODEL
NIMBUS
unit-occ-cumulus
unit-occ-power9
MODEL
CUMULUS
unit-l4-power9
unit
TYPE
L4
DECONFIG_GARDABLE1
unit-l4-centaur
unit-l4-power9
MODEL
CENTAUR
unit-nx-power9
unit
TYPE
NX
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
PRIMARY_CAPABILITIES
supportsFsiScom0
supportsXscom0
supportsInbandScom0
reserved0
CDM_DOMAINFABRIC
uart
unit
CLASS
UNIT
TYPE
UART
sp
chip
CLASS
CHIP
TYPE
SP
bmc
sp
TYPE
SP
MODEL
BMC
HWAS_STATE
deconfiguredByEid0
poweredOn1
present1
functional1
dumpfunctional0
specdeconfig0
power-supply
unit
CLASS
UNIT
TYPE
PS
fan
unit
CLASS
UNIT
TYPE
FAN
vrm
unit
CLASS
UNIT
TYPE
VRM
usb
unit
CLASS
UNIT
TYPE
USB
eth
unit
CLASS
UNIT
TYPE
ETH
panel
unit
TYPE
PANEL