base
CLASS
TYPE
MODEL
HUID
PHYS_PATH
AFFINITY_PATH
PRIMARY_CAPABILITIES
HWAS_STATE
HWAS_STATE_CHANGED_FLAG
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
DECONFIG_GARDABLE0
sys-sys-power8
base
CLASSSYS
TYPESYS
MODELPOWER8
HUID0x00010000
EXECUTION_PLATFORM
SCRATCH_UINT8_1
SCRATCH_UINT8_2
SCRATCH_UINT32_1
SCRATCH_UINT32_2
SCRATCH_UINT64_1
SCRATCH_UINT64_2
SCRATCH_UINT8_ARRAY_1
SCRATCH_UINT8_ARRAY_2
SCRATCH_UINT32_ARRAY_1
SCRATCH_UINT32_ARRAY_2
SCRATCH_UINT64_ARRAY_1
SCRATCH_UINT64_ARRAY_2
NUMERIC_POD_TYPE_TEST
DUMMY_RW
XSCOM_BASE_ADDRESS
TEST_NULL_STRING
TEST_MIN_STRINGZ
TEST_MAX_STRING
TEST_NO_DEFAULT_STRING
PHYS_PATH
physical:sys-0
AFFINITY_PATH
affinity:sys-0
IS_SIMULATION
0
ISTEP_MODE
PROC_EPS_TABLE_TYPE
PROC_FABRIC_PUMP_MODE
PROC_X_BUS_WIDTH
ALL_MCS_IN_INTERLEAVING_GROUP
FREQ_PROC_REFCLOCK
FREQ_PROC_REFCLOCK_KHZ
FREQ_MEM_REFCLOCK
FREQ_CORE_FLOOR
FREQ_PB
FREQ_A
FREQ_X
SP_FUNCTIONS
HB_SETTINGS
PAYLOAD_KIND
PAYLOAD_BASE
PAYLOAD_ENTRY
HB_HRMOR_NODAL_BASE
MSS_MBA_ADDR_INTERLEAVE_BIT
MSS_MBA_CACHELINE_INTERLEAVE_MODE
MSS_PREFETCH_ENABLE
MSS_CLEANER_ENABLE
MIRROR_BASE_ADDRESS
FREQ_PCIE
L2_R_T0_EPS
L2_R_T1_EPS
L2_R_T2_EPS
L2_FORCE_R_T2_EPS
L2_W_EPS
L3_R_T0_EPS
L3_R_T1_EPS
L3_R_T2_EPS
L3_FORCE_R_T2_EPS
L3_W_EPS
NOMINAL_FREQ_MHZ
MNFG_FLAGS
FABRIC_TO_PHYSICAL_NODE_MAP
FREQ_CORE_MAX
PM_EXTERNAL_VRM_STEPDELAY
PM_EXTERNAL_VRM_STEPSIZE
PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY
PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY
PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY
PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY
PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY
PM_SAFE_FREQUENCY
PM_SPIPSS_FREQUENCY
PM_SPIVID_FREQUENCY
CPM_TURBO_BOOST_PERCENT
PROC_R_LOADLINE_VDD
PROC_R_LOADLINE_VCS
PROC_R_DISTLOSS_VDD
PROC_R_DISTLOSS_VCS
PROC_VRM_VOFFSET_VDD
PROC_VRM_VOFFSET_VCS
NEST_FREQ_MHZ
BOOT_FREQ_MHZ
EX_GARD_BITS
PIB_I2C_REFCLOCK
PIB_I2C_NEST_PLL
SBE_IMAGE_OFFSET
BOOT_VOLTAGE
SYNC_BETWEEN_STEPS
PROC_SELECT_BOOT_MASTER
PROC_SELECT_SEEPROM_IMAGE
X_EREPAIR_THRESHOLD_FIELD
A_EREPAIR_THRESHOLD_FIELD
DMI_EREPAIR_THRESHOLD_FIELD
X_EREPAIR_THRESHOLD_MNFG
A_EREPAIR_THRESHOLD_MNFG
DMI_EREPAIR_THRESHOLD_MNFG
FREQ_CORE
PROC_EPS_GB_PERCENTAGE
PROC_EPS_GB_DIRECTION
PROC_FABRIC_ASYNC_SAFE_MODE
ENABLED_THREADS
MSS_ZSERIES
MAX_PROC_CHIPS_PER_NODE
MAX_EXS_PER_PROC_CHIP
MAX_DIMMS_PER_MBA_PORT
2
MAX_MBA_PORTS_PER_MBA
2
MAX_MBAS_PER_MEMBUF_CHIP
2
MAX_CHIPLETS_PER_PROC
32
MAX_MCS_PER_SYSTEM
PROC_PBIEX_ASYNC_SEL
MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA
MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR
MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP
MRW_THERMAL_MEMORY_POWER_LIMIT
PLCK_IPL_ATTR_OVERRIDES_EXIST
DUMMY_PERSISTENCY
MEM_MIRROR_PLACEMENT_POLICY
RISK_LEVEL
CDM_POLICIES
HOSTSVC_PLID
RUN_MAX_MEM_PATTERNS
LAB_USE_JTAG_MODE
MSS_CONTROL_SWITCH
DISABLE_I2C_ACCESS
PROC_REFCLOCK_RCVR_TERM
PCI_REFCLOCK_RCVR_TERM
MEM_FILTER_PLL_SOURCE
chip
base
CLASS
CHIP
POSITION
FSI_MASTER_CHIP
physical:na-0
FSI_MASTER_TYPE
NO_MASTER
FSI_MASTER_PORT
FSI_SLAVE_CASCADE
FSI_OPTION_FLAGS
EC
CHIP_ID
FRU_ID
chip-processor
chip
TYPE
PROC
PRIMARY_CAPABILITIES
supportsFsiScom1
supportsXscom1
supportsInbandScom0
reserved0
SCOM_SWITCHES
FSI_GP_REG_SCOM_ACCESS
1
FABRIC_NODE_ID
FABRIC_CHIP_ID
CHIP_HAS_SBE
1
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
MVPD_FREQ_CORE_NOMINAL
VPD_REC_NUM
MSS_MEM_MC_IN_GROUP
PROC_MEM_BASES
PROC_MEM_SIZES
PROC_MIRROR_BASES
PROC_MIRROR_SIZES
PROC_L3_BAR1_REG
PROC_L3_BAR2_REG
PROC_L3_BAR_GROUP_MASK_REG
PROC_PCIE_NOT_F_LINK
MSS_INTERLEAVE_ENABLE
MSS_MCS_GROUP_32
MSS_MEM_IPL_COMPLETE
PM_APSS_CHIP_SELECT
PM_PBAX_BRDCST_ID_VECTOR
PM_PBAX_CHIPID
PM_PBAX_NODEID
PM_SPIVID_PORT_ENABLE
PM_AISS_TIMEOUT
PM_EXTERNAL_VRM_STEPDELAY_RANGE
PM_EXTERNAL_VRM_STEPDELAY_VALUE
PM_IVRMS_ENABLED
PM_OCC_HEARTBEAT_TIME
PM_PBAX_RCV_RESERV_TIMEOUT
PM_PBAX_SND_RESERV_TIMEOUT
PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE
PM_PBAX_SND_RETRY_THRESHOLD
PM_PFET_POWERDOWN_CORE_DELAY0
PM_PFET_POWERDOWN_CORE_DELAY0_VALUE
PM_PFET_POWERDOWN_CORE_DELAY1
PM_PFET_POWERDOWN_CORE_DELAY1_VALUE
PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT
PM_PFET_POWERDOWN_ECO_DELAY0
PM_PFET_POWERDOWN_ECO_DELAY0_VALUE
PM_PFET_POWERDOWN_ECO_DELAY1
PM_PFET_POWERDOWN_ECO_DELAY1_VALUE
PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT
PM_PFET_POWERUP_CORE_DELAY0
PM_PFET_POWERUP_CORE_DELAY0_VALUE
PM_PFET_POWERUP_CORE_DELAY1
PM_PFET_POWERUP_CORE_DELAY1_VALUE
PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT
PM_PFET_POWERUP_ECO_DELAY0
PM_PFET_POWERUP_ECO_DELAY0_VALUE
PM_PFET_POWERUP_ECO_DELAY1
PM_PFET_POWERUP_ECO_DELAY1_VALUE
PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT
PM_PMC_HANGPULSE_DIVIDER
PM_POWER_PROXY_TRACE_TIMER
PM_PPT_TIMER_MATCH_VALUE
PM_PPT_TIMER_TICK
PM_PSTATE0_FREQUENCY
PM_PSTATE_STEPSIZE
PM_PVSAFE_PSTATE
PM_RESONANT_CLOCK_ENABLE
PM_RESONANT_CLOCK_FULL_CSB_PSTATE
PM_RESONANT_CLOCK_HFRHIGH_PSTATE
PM_RESONANT_CLOCK_HFRLOW_PSTATE
PM_RESONANT_CLOCK_LFRLOW_PSTATE
PM_RESONANT_CLOCK_LFRUPPER_PSTATE
PM_SAFE_PSTATE
PM_SLEEP_ENTRY
PM_SLEEP_EXIT
PM_SLEEP_TYPE
PM_SLEEP_WINKLE_REQUEST_TIMEOUT
PM_SPIPSS_CLOCK_DIVIDER
PM_SPIPSS_CLOCK_PHASE
PM_SPIPSS_CLOCK_POLARITY
PM_SPIPSS_FRAME_SIZE
PM_SPIPSS_INTER_FRAME_DELAY
PM_SPIPSS_INTER_FRAME_DELAY_SETTING
PM_SPIPSS_IN_COUNT
PM_SPIPSS_IN_DELAY
PM_SPIPSS_OUT_COUNT
PM_SPIVID_CLOCK_DIVIDER
PM_SPIVID_CLOCK_PHASE
PM_SPIVID_CLOCK_POLARITY
PM_SPIVID_CRC_CHECK_ENABLE
PM_SPIVID_CRC_GEN_ENABLE
PM_SPIVID_CRC_POLYNOMIAL_ENABLES
PM_SPIVID_FRAME_SIZE
PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS
PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE
PM_SPIVID_INTER_RETRY_DELAY
PM_SPIVID_INTER_RETRY_DELAY_VALUE
PM_SPIVID_IN_DELAY_FRAME1
PM_SPIVID_IN_DELAY_FRAME2
PM_SPIVID_MAJORITY_VOTE_ENABLE
PM_SPIVID_MAX_RETRIES
PM_WINKLE_TYPE
PROC_DPLL_DIVIDER
SBE_SEEPROM_I2C_ADDRESS_BYTES
SBE_SEEPROM_I2C_DEVICE_ADDRESS
SBE_SEEPROM_I2C_PORT
PNOR_I2C_ADDRESS_BYTES
PROC_SECURITY_SETUP_VECTOR
PROC_MIRROR_BASES_ACK
PROC_MIRROR_SIZES_ACK
PROC_MEM_BASES_ACK
PROC_MEM_SIZES_ACK
FREQ_EXT_BIAS_UP
FREQ_EXT_BIAS_DOWN
VOLTAGE_EXT_VDD_BIAS_UP
VOLTAGE_EXT_VDD_BIAS_DOWN
VOLTAGE_EXT_VCS_BIAS_UP
VOLTAGE_EXT_VCS_BIAS_DOWN
VOLTAGE_INT_VDD_BIAS_UP
VOLTAGE_INT_VDD_BIAS_DOWN
VOLTAGE_INT_VCS_BIAS_UP
VOLTAGE_INT_VCS_BIAS_DOWN
PM_UNDERVOLTING_FRQ_MINIMUM
PM_UNDERVOLTING_FREQ_MAXIMUM
CPM_INFLECTION_POINTS
PM_WINKLE_ENTRY
PM_WINKLE_EXIT
chip-processor-power8
chip-processor
DUMMY_RW
DUMMY_HEAP_ZERO_DEFAULT
MSS_MEM_MC_IN_GROUP
EEPROM_VPD_PRIMARY_INFO
EEPROM_VPD_BACKUP_INFO
EEPROM_SBE_PRIMARY_INFO
EEPROM_SBE_BACKUP_INFO
FSP_BASE_ADDR
FSP_BAR_SIZE
FSP_MMIO_MASK_SIZE
PSI_BRIDGE_BASE_ADDR
INTP_BASE_ADDR
PHB_BASE_ADDRS
PCI_BASE_ADDRS
MEM_BASE
MIRROR_BASE
RNG_BASE_ADDR
RNG_BAR_SIZE
IMT_BASE_ADDR
IMT_BAR_SIZE
IBSCOM_PROC_BASE_ADDR
PROC_PCIE_IOP_CONFIG
PROC_PCIE_IOP_SWAP
PROC_PCIE_PHB_ACTIVE
PROC_PCIE_IOP_G3_PLL_CONTROL0
PROC_PCIE_IOP_G2_PLL_CONTROL0
PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0
PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1
PROC_PCIE_IOP_PCS_CONTROL0
PROC_PCIE_IOP_PCS_CONTROL1
PROC_PCIE_IOP_TX_FIFO_OFFSET
PROC_PCIE_IOP_TX_RCVRDETCNTL
PROC_PCIE_IOP_TX_BWLOSS1
PROC_PCIE_IOP_RX_VGA_CONTROL2
PROC_PCIE_IOP_RX_PEAK
PROC_PCIE_IOP_RX_SDL
PROC_PCIE_IOP_ZCAL_CONTROL
PROC_DCM_INSTALLED
CHIP_REGIONS_TO_ENABLE
PROC_ADU_UNTRUSTED_BAR_BASE_ADDR
PROC_ADU_UNTRUSTED_BAR_SIZE
PROC_PSI_UNTRUSTED_BAR0_BASE_ADDR
PROC_PSI_UNTRUSTED_BAR0_SIZE
PROC_PSI_UNTRUSTED_BAR1_BASE_ADDR
PROC_PSI_UNTRUSTED_BAR1_SIZE
PROC_PERV_BNDY_PLL_CHIPLET_ID
PROC_PB_BNDY_DMIPLL_CHIPLET_ID
PROC_AB_BNDY_PLL_CHIPLET_ID
PROC_PCI_BNDY_PLL_CHIPLET_ID
PROC_PERV_BNDY_PLL_SCAN_SELECT
PROC_PB_BNDY_DMIPLL_SCAN_SELECT
PROC_AB_BNDY_PLL_SCAN_SELECT
PROC_PCI_BNDY_PLL_SCAN_SELECT
PROC_PCIE_REFCLOCK_ENABLE
PROC_EX_FUNC_L3_DELTA_DATA
PROC_EX_FUNC_L3_LENGTH
ECID
PROC_HTM_BAR_SIZE
PROC_OCC_SANDBOX_SIZE
PROC_HTM_BAR_BASE_ADDR
PROC_OCC_SANDBOX_BASE_ADDR
PROC_AS_MMIO_BAR_BASE_ADDR
PROC_AS_MMIO_BAR_ENABLE
PROC_AS_MMIO_BAR_SIZE
PROC_BOOT_VOLTAGE_VID
chip-processor-venice
chip-processor-power8
MODEL
VENICE
DUMMY_RW
DUMMY_HEAP_ZERO_DEFAULT
chip-processor-murano
chip-processor-power8
MODEL
MURANO
unit
base
CLASS
UNIT
PRIMARY_CAPABILITIES
supportsFsiScom1
supportsXscom1
supportsInbandScom0
reserved0
CHIP_UNIT
0
unit-ex-power8
unit
TYPE
EX
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
PM_SPWUP_FSP
PM_SPWUP_OCC
PM_SPWUP_PHYP
OVERRIDE_MVPD_NOM_FREQ_MHZ
OVERRIDE_MVPD_V_NEST_NOM_VOLTAGE
OVERRIDE_MVPD_I_NEST_NOM_CURRENT
OVERRIDE_MVPD_V_CS_NOM_VOLTAGE
OVERRIDE_MVPD_I_CS_NOM_CURRENT
OVERRIDE_MVPD_PS_FREQ_MHZ
OVERRIDE_MVPD_V_NEST_PS_VOLTAGE
OVERRIDE_MVPD_I_NEST_PS_CURRENT
OVERRIDE_MVPD_V_CS_PS_VOLTAGE
OVERRIDE_MVPD_I_CS_PS_CURRENT
OVERRIDE_MVPD_TURBO_FREQ_MHZ
OVERRIDE_MVPD_V_NEST_TURBO_VOLTAGE
OVERRIDE_MVPD_I_NEST_TURBO_CURRENT
OVERRIDE_MVPD_V_CS_TURBO_VOLTAGE
OVERRIDE_MVPD_I_CS_TURBO_CURRENT
OVERRIDE_MVPD_FVMIN_FREQ_MHZ
OVERRIDE_MVPD_V_NEST_FVMIN_VOLTAGE
OVERRIDE_MVPD_I_NEST_FVMIN_CURRENT
OVERRIDE_MVPD_V_CS_FVMIN_VOLTAGE
OVERRIDE_MVPD_I_CS_FVMIN_CURRENT
OVERRIDE_MVPD_LAB_FREQ_MHZ
OVERRIDE_MVPD_V_NEST_LAB_VOLTAGE
OVERRIDE_MVPD_I_NEST_LAB_CURRENT
OVERRIDE_MVPD_V_CS_LAB_VOLTAGE
OVERRIDE_MVPD_I_CS_LAB_CURRENT
PM_SPWUP_IGNORE_XSTOP_FLAG
unit-ex-venice
unit-ex-power8
MODEL
VENICE
unit-ex-murano
unit-ex-power8
MODEL
MURANO
unit-core-power8
unit
TYPE
CORE
DECONFIG_GARDABLE0
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000000
unit-core-venice
unit-core-power8
MODEL
VENICE
unit-core-murano
unit-core-power8
MODEL
MURANO
unit-pci-power8
unit
TYPE
PCI
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
unit-pci-venice
unit-pci-power8
MODEL
VENICE
unit-pci-murano
unit-pci-power8
MODEL
MURANO
enc-node-power8
base
CLASS
ENC
TYPE
NODE
MODEL
POWER8
FIELD_CORE_OVERRIDE
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
unit-abus-power8
unit
TYPE
ABUS
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
CHIP_UNIT
PEER_TARGET
EI_BUS_TX_LANE_INVERT
EI_BUS_TX_MSBSWAP
IS_INTER_ENCLOSURE_BUS
PEER_PATH
unit-abus-venice
unit-abus-power8
MODEL
VENICE
unit-abus-murano
unit-abus-power8
MODEL
MURANO
unit-xbus-power8
unit
TYPE
XBUS
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
CHIP_UNIT
PEER_TARGET
unit-xbus-venice
unit-xbus-power8
MODEL
VENICE
unit-xbus-murano
unit-xbus-power8
MODEL
MURANO
unit-l4-power8
unit
TYPE
L4
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
unit-mba-power8
unit
TYPE
MBA
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000001
MSS_DIMM_MFG_ID_CODE
EFF_DIMM_RANKS_CONFIGED
EFF_NUM_RANKS_PER_DIMM
EFF_DIMM_TYPE
EFF_CUSTOM_DIMM
EFF_DRAM_WIDTH
EFF_DRAM_GEN
EFF_PRIMARY_RANK_GROUP0
EFF_PRIMARY_RANK_GROUP1
EFF_PRIMARY_RANK_GROUP2
EFF_PRIMARY_RANK_GROUP3
EFF_SECONDARY_RANK_GROUP0
EFF_SECONDARY_RANK_GROUP1
EFF_SECONDARY_RANK_GROUP2
EFF_SECONDARY_RANK_GROUP3
EFF_TERTIARY_RANK_GROUP0
EFF_TERTIARY_RANK_GROUP1
EFF_TERTIARY_RANK_GROUP2
EFF_TERTIARY_RANK_GROUP3
EFF_QUATERNARY_RANK_GROUP0
EFF_QUATERNARY_RANK_GROUP1
EFF_QUATERNARY_RANK_GROUP2
EFF_QUATERNARY_RANK_GROUP3
EFF_CKE_MAP
EFF_SPCKE_MAP
EFF_DIMM_SPARE
EFF_DRAM_RON
EFF_DRAM_RTT_NOM
EFF_DRAM_RTT_WR
EFF_ODT_RD
EFF_ODT_WR
EFF_DRAM_WR_VREF
EFF_DRAM_WRDDR4_VREF
EFF_CEN_RCV_IMP_DQ_DQS
EFF_CEN_DRV_IMP_DQ_DQS
EFF_CEN_DRV_IMP_ADDR
EFF_CEN_DRV_IMP_CNTL
EFF_CEN_DRV_IMP_CLK
EFF_CEN_DRV_IMP_SPCKE
EFF_CEN_SLEW_RATE_DQ_DQS
EFF_CEN_SLEW_RATE_ADDR
EFF_CEN_SLEW_RATE_CLK
EFF_CEN_SLEW_RATE_SPCKE
EFF_CEN_SLEW_RATE_CNTL
EFF_CEN_RD_VREF
EFF_CEN_RD_VREF_SCHMOO
EFF_DRAM_WR_VREF_SCHMOO
EFF_DRAM_WRDDR4_VREF_SCHMOO
EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO
EFF_CEN_DRV_IMP_CLK_SCHMOO
EFF_CEN_DRV_IMP_SPCKE_SCHMOO
EFF_CEN_DRV_IMP_CNTL_SCHMOO
EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO
EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO
EFF_CEN_SLEW_RATE_CLK_SCHMOO
EFF_CEN_SLEW_RATE_SPCKE_SCHMOO
EFF_CEN_SLEW_RATE_ADDR_SCHMOO
EFF_CEN_SLEW_RATE_CNTL_SCHMOO
EFF_DIMM_SIZE
EFF_DRAM_BANKS
EFF_DRAM_ROWS
EFF_DRAM_COLS
EFF_DRAM_DENSITY
EFF_DRAM_TRCD
EFF_DRAM_TRRD
EFF_DRAM_TRP
EFF_DRAM_TRAS
EFF_DRAM_TRC
EFF_DRAM_TRFI
EFF_DRAM_TRFC
EFF_DRAM_TWTR
EFF_DRAM_TRTP
EFF_DRAM_TFAW
EFF_DRAM_BL
EFF_DRAM_CL
EFF_DRAM_AL
EFF_DRAM_CWL
EFF_DRAM_RBT
EFF_DRAM_TM
EFF_DRAM_DLL_RESET
EFF_DRAM_WR
EFF_DRAM_DLL_PPD
EFF_DRAM_DLL_ENABLE
EFF_DRAM_TDQS
EFF_DRAM_WR_LVL_ENABLE
EFF_DRAM_OUTPUT_BUFFER
EFF_DRAM_PASR
EFF_DRAM_ASR
EFF_DRAM_SRT
EFF_MPR_LOC
EFF_MPR_MODE
EFF_DIMM_RCD_CNTL_WORD_0_15
EFF_DIMM_RCD_IBT
EFF_DIMM_RCD_MIRROR_MODE
EFF_SCHMOO_MODE
EFF_SCHMOO_ADDR_MODE
EFF_SCHMOO_TEST_VALID
EFF_SCHMOO_PARAM_VALID
EFF_SCHMOO_WR_EYE_MIN_MARGIN
EFF_SCHMOO_RD_EYE_MIN_MARGIN
EFF_SCHMOO_DQS_CLK_MIN_MARGIN
EFF_SCHMOO_RD_GATE_MIN_MARGIN
EFF_SCHMOO_ADDR_CMD_MIN_MARGIN
EFF_MEMCAL_INTERVAL
EFF_ZQCAL_INTERVAL
EFF_IBM_TYPE
EFF_NUM_DROPS_PER_PORT
EFF_STACK_TYPE
EFF_NUM_MASTER_RANKS_PER_DIMM
EFF_NUM_PACKAGES_PER_RANK
EFF_NUM_DIES_PER_PACKAGE
MSS_MEM_THROTTLE_NUMERATOR_PER_MBA
MSS_MEM_THROTTLE_DENOMINATOR
MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP
MSS_MEM_WATT_TARGET
MSS_POWER_SLOPE
MSS_POWER_SLOPE2
MSS_POWER_INT
MSS_POWER_INT2
MSS_DIMM_MAXBANDWIDTH_GBS
MSS_DIMM_MAXBANDWIDTH_MRS
MSS_CHANNEL_MAXBANDWIDTH_GBS
MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS
MSS_CHANNEL_MAXBANDWIDTH_MRS
MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS
MSS_DIMM_MAXPOWER
MSS_CHANNEL_MAXPOWER
MSS_CHANNEL_PAIR_MAXPOWER
MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA
MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR
MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP
MSS_EFF_DIMM_FUNCTIONAL_VECTOR
MSS_CAL_STEP_ENABLE
MSS_SLEW_RATE_DATA
MSS_SLEW_RATE_ADR
MSS_ALLOW_SINGLE_PORT
EFF_CEN_PHASE_ROT_M0_CLK_P0
EFF_CEN_PHASE_ROT_M0_CLK_P1
EFF_CEN_PHASE_ROT_M1_CLK_P0
EFF_CEN_PHASE_ROT_M1_CLK_P1
EFF_CEN_PHASE_ROT_M_CMD_A0
EFF_CEN_PHASE_ROT_M_CMD_A1
EFF_CEN_PHASE_ROT_M_CMD_A2
EFF_CEN_PHASE_ROT_M_CMD_A3
EFF_CEN_PHASE_ROT_M_CMD_A4
EFF_CEN_PHASE_ROT_M_CMD_A5
EFF_CEN_PHASE_ROT_M_CMD_A6
EFF_CEN_PHASE_ROT_M_CMD_A7
EFF_CEN_PHASE_ROT_M_CMD_A8
EFF_CEN_PHASE_ROT_M_CMD_A9
EFF_CEN_PHASE_ROT_M_CMD_A10
EFF_CEN_PHASE_ROT_M_CMD_A11
EFF_CEN_PHASE_ROT_M_CMD_A12
EFF_CEN_PHASE_ROT_M_CMD_A13
EFF_CEN_PHASE_ROT_M_CMD_A14
EFF_CEN_PHASE_ROT_M_CMD_A15
EFF_CEN_PHASE_ROT_M_CMD_BA0
EFF_CEN_PHASE_ROT_M_CMD_BA1
EFF_CEN_PHASE_ROT_M_CMD_BA2
EFF_CEN_PHASE_ROT_M_CMD_CASN
EFF_CEN_PHASE_ROT_M_CMD_RASN
EFF_CEN_PHASE_ROT_M_CMD_WEN
EFF_CEN_PHASE_ROT_M_PAR
EFF_CEN_PHASE_ROT_M_ACTN
EFF_CEN_PHASE_ROT_M0_CNTL_CKE0
EFF_CEN_PHASE_ROT_M0_CNTL_CKE1
EFF_CEN_PHASE_ROT_M0_CNTL_CKE2
EFF_CEN_PHASE_ROT_M0_CNTL_CKE3
EFF_CEN_PHASE_ROT_M0_CNTL_CSN0
EFF_CEN_PHASE_ROT_M0_CNTL_CSN1
EFF_CEN_PHASE_ROT_M0_CNTL_CSN2
EFF_CEN_PHASE_ROT_M0_CNTL_CSN3
EFF_CEN_PHASE_ROT_M0_CNTL_ODT0
EFF_CEN_PHASE_ROT_M0_CNTL_ODT1
EFF_CEN_PHASE_ROT_M1_CNTL_CKE0
EFF_CEN_PHASE_ROT_M1_CNTL_CKE1
EFF_CEN_PHASE_ROT_M1_CNTL_CKE2
EFF_CEN_PHASE_ROT_M1_CNTL_CKE3
EFF_CEN_PHASE_ROT_M1_CNTL_CSN0
EFF_CEN_PHASE_ROT_M1_CNTL_CSN1
EFF_CEN_PHASE_ROT_M1_CNTL_CSN2
EFF_CEN_PHASE_ROT_M1_CNTL_CSN3
EFF_CEN_PHASE_ROT_M1_CNTL_ODT0
EFF_CEN_PHASE_ROT_M1_CNTL_ODT1
MSS_DQS_SWIZZLE_TYPE
MCBIST_PATTERN
MCBIST_TEST_TYPE
MCBIST_ADDR_MODES
MCBIST_RANK
MCBIST_START_ADDR
MCBIST_END_ADDR
MCBIST_ERROR_CAPTURE
MCBIST_MAX_TIMEOUT
MCBIST_PRINT_PORT
MCBIST_STOP_ON_ERROR
MCBIST_DATA_SEED
MCBIST_ADDR_INTER
MCBIST_ADDR_NUM_ROWS
MCBIST_ADDR_NUM_COLS
MCBIST_ADDR_RANK
MCBIST_ADDR_BANK
MCBIST_ADDR_SLAVE_RANK_ON
MCBIST_ADDR_STR_MAP
MCBIST_ADDR_RAND
MCBIST_PRINTING_DISABLE
MCBIST_DATA_ENABLE
MCBIST_USER_RANK
MCBIST_USER_BANK
SCHMOO_MULTIPLE_SETUP_CALL
EFF_DRAM_LPASR
EFF_MPR_PAGE
EFF_GEARDOWN_MODE
EFF_PER_DRAM_ACCESS
EFF_TEMP_READOUT
EFF_FINE_REFRESH_MODE
EFF_MPR_RD_FORMAT
EFF_MAX_POWERDOWN_MODE
EFF_TEMP_REF_RANGE
EFF_TEMP_REF_MODE
EFF_INT_VREF_MON
EFF_CS_CMD_LATENCY
EFF_SELF_REF_ABORT
EFF_RD_PREAMBLE_TRAIN
EFF_RD_PREAMBLE
EFF_WR_PREAMBLE
EFF_CA_PARITY_LATENCY
EFF_CRC_ERROR_CLEAR
EFF_CA_PARITY_ERROR_STATUS
EFF_ODT_INPUT_BUFF
EFF_RTT_PARK
EFF_CA_PARITY
EFF_DATA_MASK
EFF_WRITE_DBI
EFF_READ_DBI
VREF_DQ_TRAIN_VALUE
VREF_DQ_TRAIN_RANGE
VREF_DQ_TRAIN_ENABLE
TCCD_L
EFF_WRITE_CRC
EFF_DRAM_2N_MODE_ENABLED
EFF_DRAM_ADDRESS_MIRRORING
EFF_RLO
EFF_WLO
EFF_GPO
EFF_CKE_PRI_MAP
EFF_CKE_PWR_MAP
EFF_RDTAG
EFF_TSYS_ADR
EFF_TSYS_DP18
EFF_DQ_WR_OFFSET
EFF_BUFFER_LATENCY
LRDIMM_MR12_REG
LRDIMM_ADDITIONAL_CNTL_WORDS
LRDIMM_RANK_MULT_MODE
EFF_CRC_WR_LATENCY
MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_MBA
MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_CHIP
MSS_DIMM_POWER_TEST_MEM_THROTTLE_DENOMINATOR
MSS_THROTTLE_CONTROL_RAS_WEIGHT
MSS_THROTTLE_CONTROL_CAS_WEIGHT
MCBIST_RANDOM_SEED_VALUE
MCBIST_RANDOM_SEED_TYPE
unit-mcs-power8
unit
TYPE
MCS
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000003
IBSCOM_MCS_BASE_ADDR
EI_BUS_TX_LANE_INVERT
DMI_REFCLOCK_SWIZZLE
EI_BUS_TX_MSBSWAP
DMI_DFE_OVERRIDE
unit-mcs-venice
unit-mcs-power8
MODEL
VENICE
unit-mcs-murano
unit-mcs-power8
MODEL
MURANO
unit-mba-venice
unit-mba-power8
MODEL
VENICE
unit-mba-murano
unit-mba-venice
MODEL
MURANO
chip-membuf-centaur
chip
TYPE
MEMBUF
MODEL
CENTAUR
PRIMARY_CAPABILITIES
supportsFsiScom1
supportsXscom0
supportsInbandScom1
reserved0
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000003
SCOM_SWITCHES
useFsiScom1
useXscom0
useInbandScom0
reserved0
EEPROM_VPD_PRIMARY_INFO
MSS_VOLT
MSS_FREQ
MSS_LAB_OVERRIDE_FOR_MEM_PLL
ECID
FSI_GP_REG_SCOM_ACCESS
0
CHIP_HAS_SBE
0
MSS_CACHE_ENABLE
VMEM_ID
EI_BUS_TX_LANE_INVERT
SBE_SEEPROM_I2C_ADDRESS_BYTES
SBE_SEEPROM_I2C_DEVICE_ADDRESS
SBE_SEEPROM_I2C_PORT
PNOR_I2C_ADDRESS_BYTES
VPD_REC_NUM
MSS_PSRO
MSS_NWELL_MISPLACEMENT
EI_BUS_TX_MSBSWAP
MSS_FREQ_OVERRIDE
MEMB_TP_BNDY_PLL_SCAN_SELECT
MSS_FREQ_BIAS_PERCENTAGE
CDIMM_SENSOR_MAP_PRIMARY
CDIMM_SENSOR_MAP_SECONDARY
MSS_BLUEWATERFALL_BROKEN
L4_BANK_DELETE_VPD
DMI_DFE_OVERRIDE
unit-l4-centaur
unit-l4-power8
MODEL
CENTAUR
unit-mba-centaur
unit-mba-power8
PRIMARY_CAPABILITIES
supportsFsiScom1
supportsXscom0
supportsInbandScom1
reserved0
MODEL
CENTAUR
card
base
CLASS
CARD
lcard-dimm
card
TYPE
DIMM
CLASS
LOGICAL_CARD
POSITION
MBA_PORT
MBA_DIMM
DECONFIG_GARDABLE1
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
0x00000003
EEPROM_VPD_PRIMARY_INFO
VPD_REC_NUM
lcard-dimm-jedec
lcard-dimm
MODELJEDEC
CEN_DQ_TO_DIMM_CONN_DQ
lcard-dimm-cdimm
lcard-dimm
MODELCDIMM