base CLASS TYPE MODEL HUID PHYS_PATH AFFINITY_PATH PRIMARY_CAPABILITIES HWAS_STATE DECONFIG_GARDABLE 0 sys-sys-power8 base CLASSSYS TYPESYS MODELPOWER8 HUID0x00010000 EXECUTION_PLATFORM SCRATCH_UINT8_1 SCRATCH_UINT8_2 SCRATCH_UINT32_1 SCRATCH_UINT32_2 SCRATCH_UINT64_1 SCRATCH_UINT64_2 SCRATCH_UINT8_ARRAY_1 SCRATCH_UINT8_ARRAY_2 SCRATCH_UINT32_ARRAY_1 SCRATCH_UINT32_ARRAY_2 SCRATCH_UINT64_ARRAY_1 SCRATCH_UINT64_ARRAY_2 NUMERIC_POD_TYPE_TEST DUMMY_RW XSCOM_BASE_ADDRESS TEST_NULL_STRING TEST_MIN_STRINGZ TEST_MAX_STRING TEST_NO_DEFAULT_STRING PHYS_PATH physical:sys-0 AFFINITY_PATH affinity:sys-0 IS_SIMULATION 0 ISTEP_MODE PROC_EPS_TABLE_TYPE PROC_FABRIC_PUMP_MODE PROC_X_BUS_WIDTH ALL_MCS_IN_INTERLEAVING_GROUP FREQ_PROC_REFCLOCK FREQ_MEM_REFCLOCK FREQ_CORE_FLOOR FREQ_PB FREQ_A FREQ_X SP_FUNCTIONS HB_SETTINGS PAYLOAD_KIND PAYLOAD_BASE PAYLOAD_ENTRY MSS_MCA_HASH_MODE MSS_MBA_ADDR_INTERLEAVE_BIT MSS_MBA_CACHELINE_INTERLEAVE_MODE MSS_PREFETCH_ENABLE MSS_CLEANER_ENABLE MIRROR_BASE_ADDRESS PROC_EPS_GB_PERCENTAGE PROC_EPS_GB_DIRECTION PROC_FABRIC_ASYNC_SAFE_MODE FREQ_PCIE L2_R_T0_EPS L2_R_T1_EPS L2_R_T2_EPS L2_FORCE_R_T2_EPS L2_W_EPS L3_R_T0_EPS L3_R_T1_EPS L3_R_T2_EPS L3_FORCE_R_T2_EPS L3_W_EPS NOMINAL_FREQ_MHZ MNFG_FLAGS PROC_R_LOADLINE PROC_R_DISTLOSS PROC_VRM_VOFFSET FREQ_CORE_MAX PROC_DPLL_DIVIDER NEST_FREQ_MHZ BOOT_FREQ_MHZ EX_GARD_BITS PIB_I2C_REFCLOCK PIB_I2C_NEST_PLL SBE_IMAGE_OFFSET BOOT_VOLTAGE SYNC_BETWEEN_STEPS PROC_SELECT_BOOT_MASTER PROC_SELECT_SEEPROM_IMAGE ENABLED_THREADS MSS_ZSERIES chip base CLASS CHIP POSITION FSI_MASTER_CHIP physical:na-0 FSI_MASTER_TYPE FSI_MASTER_PORT FSI_SLAVE_CASCADE FSI_OPTION_FLAGS DECONFIG_GARDABLE 1 EC CHIP_ID chip-processor chip TYPE PROC PRIMARY_CAPABILITIES supportsFsiScom1 supportsXscom1 supportsInbandScom0 reserved0 SCOM_SWITCHES FSI_GP_REG_SCOM_ACCESS 1 FABRIC_NODE_ID FABRIC_CHIP_ID CHIP_HAS_SBE 1 MVPD_FREQ_CORE_NOMINAL VPD_REC_NUM MSS_MEM_MC_IN_GROUP PROC_MEM_BASES PROC_MEM_SIZES PROC_MIRROR_BASES PROC_MIRROR_SIZES PROC_L3_BAR1_REG PROC_L3_BAR2_REG PROC_L3_BAR_GROUP_MASK_REG FREQ_CORE PROC_PCIE_NOT_F_LINK MSS_INTERLEAVE_ENABLE MSS_MCS_GROUP_32 MSS_MEM_IPL_COMPLETE PM_EXTERNAL_VRM_STEPSIZE PM_EXTERNAL_VRM_STEPDELAY PM_SAFE_VOLTAGE PM_PSTATE_UNDERVOLTING_MINIMUM PM_PSTATE_UNDERVOLTING_MAXIMUM PM_SPIVID_FREQUENCY PM_SPIVID_PORT_ENABLE PM_SLEEP_ENTRY PM_SLEEP_EXIT PM_SLEEP_TYPE PM_WINKLE_ENTRY PM_WINKLE_EXIT PM_WINKLE_TYPE PM_SAFE_FREQUENCY PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY PM_SPIPSS_FREQUENCY PM_APSS_CHIP_SELECT PM_PBAX_NODEID PM_PBAX_CHIPID PM_PBAX_BRDCST_ID_VECTOR PM_POWER_PROXY_TRACE_TIMER PM_PPT_TIMER_MATCH_VALUE PM_PPT_TIMER_TICK PM_AISS_TIMEOUT PM_PSTATE_STEPSIZE PM_EXTERNAL_VRM_STEPDELAY_RANGE PM_EXTERNAL_VRM_STEPDELAY_VALUE PM_PMC_HANGPULSE_DIVIDER PM_PVSAFE_PSTATE PM_SPIVID_FRAME_SIZE PM_SPIVID_IN_DELAY_FRAME1 PM_SPIVID_IN_DELAY_FRAME2 PM_SPIVID_CLOCK_POLARITY PM_SPIVID_CLOCK_PHASE PM_SPIVID_CLOCK_DIVIDER PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE PM_SPIVID_INTER_RETRY_DELAY_VALUE PM_SPIVID_INTER_RETRY_DELAY PM_SPIVID_CRC_GEN_ENABLE PM_SPIVID_CRC_CHECK_ENABLE PM_SPIVID_MAJORITY_VOTE_ENABLE PM_SPIVID_MAX_RETRIES PM_SPIVID_CRC_POLYNOMIAL_ENABLES PM_OCC_HEARTBEAT_TIME PM_SLEEP_WINKLE_REQUEST_TIMEOUT PM_PFET_POWERUP_CORE_DELAY0 PM_PFET_POWERUP_CORE_DELAY1 PM_PFET_POWERUP_CORE_DELAY0_VALUE PM_PFET_POWERUP_CORE_DELAY1_VALUE PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT PM_PFET_POWERDOWN_CORE_DELAY0 PM_PFET_POWERDOWN_CORE_DELAY1 PM_PFET_POWERDOWN_CORE_DELAY0_VALUE PM_PFET_POWERDOWN_CORE_DELAY1_VALUE PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT PM_PFET_POWERUP_ECO_DELAY0 PM_PFET_POWERUP_ECO_DELAY1 PM_PFET_POWERUP_ECO_DELAY0_VALUE PM_PFET_POWERUP_ECO_DELAY1_VALUE PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT PM_PFET_POWERDOWN_ECO_DELAY0 PM_PFET_POWERDOWN_ECO_DELAY1 PM_PFET_POWERDOWN_ECO_DELAY0_VALUE PM_PFET_POWERDOWN_ECO_DELAY1_VALUE PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT PM_PSTATE0_FREQUENCY PM_IVRMS_ENABLED PM_SAFE_PSTATE PM_RESONANT_CLOCK_ENABLE PM_RESONANT_CLOCK_FULL_CSB_PSTATE PM_RESONANT_CLOCK_LFRLOW_PSTATE PM_RESONANT_CLOCK_LFRUPPER_PSTATE PM_RESONANT_CLOCK_HFRLOW_PSTATE PM_RESONANT_CLOCK_HFRHIGH_PSTATE PM_SPIPSS_FRAME_SIZE PM_SPIPSS_OUT_COUNT PM_SPIPSS_IN_DELAY PM_SPIPSS_IN_COUNT PM_SPIPSS_CLOCK_POLARITY PM_SPIPSS_CLOCK_PHASE PM_SPIPSS_CLOCK_DIVIDER PM_SPIPSS_INTER_FRAME_DELAY_SETTING PM_SPIPSS_INTER_FRAME_DELAY PM_PBAX_RCV_RESERV_TIMEOUT PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE PM_PBAX_SND_RETRY_THRESHOLD PM_PBAX_SND_RESERV_TIMEOUT SBE_SEEPROM_I2C_ADDRESS_BYTES SBE_SEEPROM_I2C_DEVICE_ADDRESS SBE_SEEPROM_I2C_PORT PNOR_I2C_ADDRESS_BYTES PROC_A_ENABLE PROC_X_ENABLE chip-processor-power8 chip-processor DUMMY_RW DUMMY_HEAP_ZERO_DEFAULT MSS_MEM_MC_IN_GROUP FSP_BASE_ADDR FSP_BAR_SIZE FSP_MMIO_MASK_SIZE PSI_BRIDGE_BASE_ADDR INTP_BASE_ADDR PHB_BASE_ADDRS PCI_BASE_ADDRS MEM_BASE MIRROR_BASE RNG_BASE_ADDR RNG_BAR_SIZE IMT_BASE_ADDR IMT_BAR_SIZE PROC_PCIE_IOP_CONFIG PROC_PCIE_IOP_SWAP PROC_PCIE_PHB_ACTIVE PROC_PCIE_IOP_G3_PLL_CONTROL0 PROC_PCIE_IOP_G2_PLL_CONTROL0 PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0 PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1 PROC_PCIE_IOP_PCS_CONTROL0 PROC_PCIE_IOP_PCS_CONTROL1 PROC_PCIE_IOP_TX_FIFO_OFFSET PROC_PCIE_IOP_TX_RCVRDETCNTL PROC_PCIE_IOP_TX_BWLOSS1 PROC_PCIE_IOP_RX_VGA_CONTROL2 PROC_PCIE_IOP_RX_PEAK PROC_PCIE_IOP_RX_SDL PROC_PCIE_IOP_ZCAL_CONTROL PROC_DCM_INSTALLED CHIP_REGIONS_TO_ENABLE PROC_NX_ENABLE PROC_PCIE_ENABLE PROC_ADU_UNTRUSTED_BAR_BASE_ADDR PROC_ADU_UNTRUSTED_BAR_SIZE PROC_PSI_UNTRUSTED_BAR0_BASE_ADDR PROC_PSI_UNTRUSTED_BAR0_SIZE PROC_PSI_UNTRUSTED_BAR1_BASE_ADDR PROC_PSI_UNTRUSTED_BAR1_SIZE PROC_PERV_BNDY_PLL_DATA PROC_PB_BNDY_DMIPLL_DATA PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA PROC_AB_BNDY_PLL_DATA PROC_AB_BNDY_PLL_FOR_DCCAL_DATA PROC_PCI_BNDY_PLL_DATA PROC_PERV_BNDY_PLL_LENGTH PROC_PB_BNDY_DMIPLL_LENGTH PROC_AB_BNDY_PLL_LENGTH PROC_PCI_BNDY_PLL_LENGTH PROC_PERV_BNDY_PLL_FLUSH PROC_PB_BNDY_DMIPLL_FLUSH PROC_AB_BNDY_PLL_FLUSH PROC_PCI_BNDY_PLL_FLUSH PROC_PERV_BNDY_PLL_CHIPLET_ID PROC_PB_BNDY_DMIPLL_CHIPLET_ID PROC_AB_BNDY_PLL_CHIPLET_ID PROC_PCI_BNDY_PLL_CHIPLET_ID PROC_PERV_BNDY_PLL_SCAN_SELECT PROC_PB_BNDY_DMIPLL_SCAN_SELECT PROC_AB_BNDY_PLL_SCAN_SELECT PROC_PCI_BNDY_PLL_SCAN_SELECT chip-processor-venice chip-processor-power8 MODEL VENICE DUMMY_RW DUMMY_HEAP_ZERO_DEFAULT EEPROM_ADDR_INFO0 EEPROM_ADDR_INFO1 chip-processor-murano chip-processor-power8 MODEL MURANO unit base CLASS UNIT PRIMARY_CAPABILITIES supportsFsiScom1 supportsXscom1 supportsInbandScom0 reserved0 DECONFIG_GARDABLE 1 CHIP_UNIT 0 unit-ex-power8 unit TYPE EX PM_SPWUP_FSP PM_SPWUP_OCC PM_SPWUP_PHYP OVERRIDE_MVPD_NOM_FREQ_MHZ OVERRIDE_MVPD_V_NEST_NOM_VOLTAGE OVERRIDE_MVPD_I_NEST_NOM_CURRENT OVERRIDE_MVPD_V_CS_NOM_VOLTAGE OVERRIDE_MVPD_I_CS_NOM_CURRENT OVERRIDE_MVPD_PS_FREQ_MHZ OVERRIDE_MVPD_V_NEST_PS_VOLTAGE OVERRIDE_MVPD_I_NEST_PS_CURRENT OVERRIDE_MVPD_V_CS_PS_VOLTAGE OVERRIDE_MVPD_I_CS_PS_CURRENT OVERRIDE_MVPD_TURBO_FREQ_MHZ OVERRIDE_MVPD_V_NEST_TURBO_VOLTAGE OVERRIDE_MVPD_I_NEST_TURBO_CURRENT OVERRIDE_MVPD_V_CS_TURBO_VOLTAGE OVERRIDE_MVPD_I_CS_TURBO_CURRENT OVERRIDE_MVPD_FVMIN_FREQ_MHZ OVERRIDE_MVPD_V_NEST_FVMIN_VOLTAGE OVERRIDE_MVPD_I_NEST_FVMIN_CURRENT OVERRIDE_MVPD_V_CS_FVMIN_VOLTAGE OVERRIDE_MVPD_I_CS_FVMIN_CURRENT OVERRIDE_MVPD_LAB_FREQ_MHZ OVERRIDE_MVPD_V_NEST_LAB_VOLTAGE OVERRIDE_MVPD_I_NEST_LAB_CURRENT OVERRIDE_MVPD_V_CS_LAB_VOLTAGE OVERRIDE_MVPD_I_CS_LAB_CURRENT PROC_L3_ENABLE unit-ex-venice unit-ex-power8 MODEL VENICE unit-ex-murano unit-ex-power8 MODEL MURANO unit-core-power8 unit TYPE CORE unit-core-venice unit-core-power8 MODEL VENICE unit-core-murano unit-core-power8 MODEL MURANO unit-pci-power8 unit TYPE PCI unit-pci-venice unit-pci-power8 MODEL VENICE unit-pci-murano unit-pci-power8 MODEL MURANO enc-node-power8 base CLASS ENC TYPE NODE MODEL POWER8 unit-abus-power8 unit TYPE ABUS CHIP_UNIT EI_BUS_RX_MSB_LSB_SWAP EI_BUS_TX_MSB_LSB_SWAP PEER_TARGET EI_BUS_TX_LANE_INVERT unit-abus-venice unit-abus-power8 MODEL VENICE unit-abus-murano unit-abus-power8 MODEL MURANO unit-xbus-power8 unit TYPE XBUS CHIP_UNIT PEER_TARGET unit-xbus-venice unit-xbus-power8 MODEL VENICE unit-xbus-murano unit-xbus-power8 MODEL MURANO unit-mbs-power8 unit TYPE MBS unit-mba-power8 unit TYPE MBA MSS_DIMM_MFG_ID_CODE EFF_DIMM_RANKS_CONFIGED EFF_NUM_RANKS_PER_DIMM EFF_DIMM_TYPE EFF_CUSTOM_DIMM EFF_DRAM_WIDTH EFF_DRAM_GEN EFF_PRIMARY_RANK_GROUP0 EFF_PRIMARY_RANK_GROUP1 EFF_PRIMARY_RANK_GROUP2 EFF_PRIMARY_RANK_GROUP3 EFF_SECONDARY_RANK_GROUP0 EFF_SECONDARY_RANK_GROUP1 EFF_SECONDARY_RANK_GROUP2 EFF_SECONDARY_RANK_GROUP3 EFF_TERTIARY_RANK_GROUP0 EFF_TERTIARY_RANK_GROUP1 EFF_TERTIARY_RANK_GROUP2 EFF_TERTIARY_RANK_GROUP3 EFF_QUATERNARY_RANK_GROUP0 EFF_QUATERNARY_RANK_GROUP1 EFF_QUATERNARY_RANK_GROUP2 EFF_QUATERNARY_RANK_GROUP3 EFF_ODT_RD EFF_ODT_WR EFF_CKE_MAP EFF_SPCKE_MAP EFF_DIMM_SPARE EFF_DRAM_RON EFF_DRAM_RTT_NOM EFF_DRAM_RTT_WR EFF_DRAM_WR_VREF EFF_DRAM_WRDDR4_VREF EFF_DRAM_WR_VREF_SCHMOO EFF_DRAM_WRDDR4_VREF_SCHMOO EFF_CEN_DRV_IMP_DQ_DQS EFF_CEN_DRV_IMP_ADDR EFF_CEN_DRV_IMP_CNTL EFF_CEN_DRV_IMP_CLK EFF_CEN_DRV_IMP_SPCKE EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO EFF_CEN_DRV_IMP_CLK_SCHMOO EFF_CEN_DRV_IMP_SPCKE_SCHMOO EFF_CEN_DRV_IMP_CNTL_SCHMOO EFF_CEN_RCV_IMP_DQ_DQS EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO EFF_CEN_SLEW_RATE_DQ_DQS EFF_CEN_SLEW_RATE_ADDR EFF_CEN_SLEW_RATE_CLK EFF_CEN_SLEW_RATE_SPCKE EFF_CEN_SLEW_RATE_CNTL EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO EFF_CEN_SLEW_RATE_CLK_SCHMOO EFF_CEN_SLEW_RATE_SPCKE_SCHMOO EFF_CEN_SLEW_RATE_ADDR_SCHMOO EFF_CEN_SLEW_RATE_CNTL_SCHMOO EFF_CEN_RD_VREF EFF_CEN_RD_VREF_SCHMOO EFF_DIMM_SIZE EFF_DRAM_BANKS EFF_DRAM_ROWS EFF_DRAM_COLS EFF_DRAM_DENSITY EFF_DRAM_TRCD EFF_DRAM_TRRD EFF_DRAM_TRP EFF_DRAM_TRAS EFF_DRAM_TRC EFF_DRAM_TRFI EFF_DRAM_TRFC EFF_DRAM_TWTR EFF_DRAM_TRTP EFF_DRAM_TFAW EFF_DRAM_BL EFF_DRAM_CL EFF_DRAM_AL EFF_DRAM_CWL EFF_DRAM_RBT EFF_DRAM_TM EFF_DRAM_DLL_RESET EFF_DRAM_WR EFF_DRAM_DLL_PPD EFF_DRAM_DLL_ENABLE EFF_DRAM_TDQS EFF_DRAM_WR_LVL_ENABLE EFF_DRAM_OUTPUT_BUFFER EFF_DRAM_PASR EFF_DRAM_ASR EFF_DRAM_SRT EFF_MPR_LOC EFF_MPR_MODE EFF_DIMM_RCD_CNTL_WORD_0_15 EFF_DIMM_RCD_IBT EFF_DIMM_RCD_MIRROR_MODE EFF_SCHMOO_MODE EFF_SCHMOO_ADDR_MODE EFF_SCHMOO_TEST_VALID EFF_SCHMOO_PARAM_VALID EFF_SCHMOO_WR_EYE_MIN_MARGIN EFF_SCHMOO_RD_EYE_MIN_MARGIN EFF_SCHMOO_DQS_CLK_MIN_MARGIN EFF_SCHMOO_RD_GATE_MIN_MARGIN EFF_SCHMOO_ADDR_CMD_MIN_MARGIN EFF_MEMCAL_INTERVAL EFF_ZQCAL_INTERVAL EFF_IBM_TYPE EFF_NUM_DROPS_PER_PORT EFF_STACK_TYPE EFF_NUM_MASTER_RANKS_PER_DIMM EFF_NUM_PACKAGES_PER_RANK EFF_NUM_DIES_PER_PACKAGE MSS_MEM_THROTTLE_NUMERATOR_PER_MBA MSS_MEM_THROTTLE_DENOMINATOR MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP MSS_MEM_WATT_TARGET MSS_POWER_SLOPE MSS_POWER_SLOPE2 MSS_POWER_INT MSS_POWER_INT2 MSS_DIMM_MAXBANDWIDTH_GBS MSS_DIMM_MAXBANDWIDTH_MRS MSS_CHANNEL_MAXBANDWIDTH_GBS MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS MSS_CHANNEL_MAXBANDWIDTH_MRS MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS MSS_DIMM_MAXPOWER MSS_CHANNEL_MAXPOWER MSS_CHANNEL_PAIR_MAXPOWER MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP MSS_EFF_DIMM_FUNCTIONAL_VECTOR MSS_CAL_STEP_ENABLE MSS_SLEW_RATE_DATA MSS_SLEW_RATE_ADR MSS_ALLOW_SINGLE_PORT EFF_CEN_PHASE_ROT_M0_CLK_P0 EFF_CEN_PHASE_ROT_M0_CLK_P1 EFF_CEN_PHASE_ROT_M1_CLK_P0 EFF_CEN_PHASE_ROT_M1_CLK_P1 EFF_CEN_PHASE_ROT_M_CMD_A0 EFF_CEN_PHASE_ROT_M_CMD_A1 EFF_CEN_PHASE_ROT_M_CMD_A2 EFF_CEN_PHASE_ROT_M_CMD_A3 EFF_CEN_PHASE_ROT_M_CMD_A4 EFF_CEN_PHASE_ROT_M_CMD_A5 EFF_CEN_PHASE_ROT_M_CMD_A6 EFF_CEN_PHASE_ROT_M_CMD_A7 EFF_CEN_PHASE_ROT_M_CMD_A8 EFF_CEN_PHASE_ROT_M_CMD_A9 EFF_CEN_PHASE_ROT_M_CMD_A10 EFF_CEN_PHASE_ROT_M_CMD_A11 EFF_CEN_PHASE_ROT_M_CMD_A12 EFF_CEN_PHASE_ROT_M_CMD_A13 EFF_CEN_PHASE_ROT_M_CMD_A14 EFF_CEN_PHASE_ROT_M_CMD_A15 EFF_CEN_PHASE_ROT_M_CMD_BA0 EFF_CEN_PHASE_ROT_M_CMD_BA1 EFF_CEN_PHASE_ROT_M_CMD_BA2 EFF_CEN_PHASE_ROT_M_CMD_CASN EFF_CEN_PHASE_ROT_M_CMD_RASN EFF_CEN_PHASE_ROT_M_CMD_WEN EFF_CEN_PHASE_ROT_M_PAR EFF_CEN_PHASE_ROT_M_ACTN EFF_CEN_PHASE_ROT_M0_CNTL_CKE0 EFF_CEN_PHASE_ROT_M0_CNTL_CKE1 EFF_CEN_PHASE_ROT_M0_CNTL_CKE2 EFF_CEN_PHASE_ROT_M0_CNTL_CKE3 EFF_CEN_PHASE_ROT_M0_CNTL_CSN0 EFF_CEN_PHASE_ROT_M0_CNTL_CSN1 EFF_CEN_PHASE_ROT_M0_CNTL_CSN2 EFF_CEN_PHASE_ROT_M0_CNTL_CSN3 EFF_CEN_PHASE_ROT_M0_CNTL_ODT0 EFF_CEN_PHASE_ROT_M0_CNTL_ODT1 EFF_CEN_PHASE_ROT_M1_CNTL_CKE0 EFF_CEN_PHASE_ROT_M1_CNTL_CKE1 EFF_CEN_PHASE_ROT_M1_CNTL_CKE2 EFF_CEN_PHASE_ROT_M1_CNTL_CKE3 EFF_CEN_PHASE_ROT_M1_CNTL_CSN0 EFF_CEN_PHASE_ROT_M1_CNTL_CSN1 EFF_CEN_PHASE_ROT_M1_CNTL_CSN2 EFF_CEN_PHASE_ROT_M1_CNTL_CSN3 EFF_CEN_PHASE_ROT_M1_CNTL_ODT0 EFF_CEN_PHASE_ROT_M1_CNTL_ODT1 MSS_DQS_SWIZZLE_TYPE unit-mcs-power8 unit TYPE MCS EI_BUS_RX_MSB_LSB_SWAP EI_BUS_TX_MSB_LSB_SWAP IBSCOM_MCS_BASE_ADDR EI_BUS_TX_LANE_INVERT unit-mcs-venice unit-mcs-power8 MODEL VENICE unit-mcs-murano unit-mcs-power8 MODEL MURANO unit-mba-venice unit-mba-power8 MODEL VENICE unit-mba-murano unit-mba-venice MODEL MURANO unit-mbs-venice unit-mbs-power8 MODEL VENICE unit-mbs-murano unit-mbs-venice MODEL MURANO chip-membuf-centaur chip TYPE MEMBUF MODEL CENTAUR PRIMARY_CAPABILITIES supportsFsiScom1 supportsXscom0 supportsInbandScom1 reserved0 SCOM_SWITCHES useFsiScom1 useXscom0 useInbandScom0 reserved0 EEPROM_ADDR_INFO0 EEPROM_ADDR_INFO1 MSS_VOLT MSS_FREQ MSS_LAB_OVERRIDE_FOR_MEM_PLL MSS_ECID EI_BUS_RX_MSB_LSB_SWAP EI_BUS_TX_MSB_LSB_SWAP FSI_GP_REG_SCOM_ACCESS 0 CHIP_HAS_SBE 0 MSS_CACHE_ENABLE VMEM_ID EI_BUS_TX_LANE_INVERT SBE_SEEPROM_I2C_ADDRESS_BYTES SBE_SEEPROM_I2C_DEVICE_ADDRESS SBE_SEEPROM_I2C_PORT PNOR_I2C_ADDRESS_BYTES VPD_REC_NUM MSS_PSRO MSS_NWELL_MISPLACEMENT unit-mbs-centaur unit-mbs-power8 PRIMARY_CAPABILITIES supportsFsiScom1 supportsXscom0 supportsInbandScom1 reserved0 MODEL CENTAUR unit-mba-centaur unit-mba-power8 PRIMARY_CAPABILITIES supportsFsiScom1 supportsXscom0 supportsInbandScom1 reserved0 MODEL CENTAUR card base CLASS CARD lcard-dimm card TYPE DIMM CLASS LOGICAL_CARD POSITION MBA_PORT MBA_DIMM EEPROM_ADDR_INFO0 VPD_REC_NUM lcard-dimm-jedec lcard-dimm MODELJEDEC CEN_DQ_TO_DIMM_CONN_DQ lcard-dimm-cdimm lcard-dimm MODELCDIMM