HIDDEN_ERRLOGS_ENABLE
Used to decide whether or not to prevent INFORMATIONAL/RECOVERED error
logs from being sent to the BMC via SEL/eSEL, saved to the PNOR, and
displayed to the console.
0 = Prevent INFORMATIONAL/RECOVERED error logs from being processed.
1 = Send only INFORMATIONAL error logs.
2 = Send only RECOVERED error logs.
3 = Allow all hidden error logs to be processed.
0
volatile
HIDDEN_ERRLOGS_ENABLE
Enumeration of HIDDEN_ERRLOGS_ENABLE
NO_HIDDEN_LOGS
0
ALLOW_INFORMATIONAL
1
ALLOW_RECOVERED
2
ALLOW_ALL_LOGS
3
IS_MPIPL_HB
1 = in Memory Preserving IPL mode. 0 = in normal IPL mode.
volatile-zeroed
ATTR_IS_MPIPL
DIRECT
XSCOM_VIRTUAL_ADDR
Cached Virtual Address of Xscom memory space for this Chip
volatile-zeroed
FSI_MASTER_MUTEX
Mutex for FSI Master Operations
volatile-zeroed
EEPROM_PAGE_ARRAY
Used to keep track of which EEPROM page the current I2C master bus is set to
0 = PAGE_ZERO
1 = PAGE_ONE
2 = UNKNOWN_PAGE
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2
4,4
volatile
HB_MUTEX_TEST_LOCK
Host boot mutex for testing
volatile-zeroed
I2C_PAGE_MUTEX_0
Mutex to protect page select operations for I2C Master engine 0
volatile-zeroed
I2C_PAGE_MUTEX_1
Mutex to protect page select operations for I2C Master engine 1
volatile-zeroed
I2C_PAGE_MUTEX_2
Mutex to protect page select operations for I2C Master engine 2
volatile-zeroed
I2C_PAGE_MUTEX_3
Mutex to protect page select operations for I2C Master engine 3
volatile-zeroed
I2C_ENGINE_MUTEX_0
Mutex for I2C Master engine 0
volatile-zeroed
I2C_ENGINE_MUTEX_1
Mutex for I2C Master engine 1
volatile-zeroed
I2C_ENGINE_MUTEX_2
Mutex for I2C Master engine 2
volatile-zeroed
I2C_ENGINE_MUTEX_3
Mutex for I2C Master engine 3
volatile-zeroed
FSI_SCOM_MUTEX
Mutex for FSI-based SCOM Operations
volatile-zeroed
SCOM_IND_MUTEX
Mutex for Indirect SCOM read operation
volatile-zeroed
SCAN_MUTEX
Mutex for SCAN operations
0
volatile-zeroed
IBSCOM_VIRTUAL_ADDR
Cached Virtual Address of Inband Scom memory space for this Chip
volatile-zeroed
IBSCOM_MUTEX
Mutex for Inband SCOM Operations
volatile-zeroed
IBSCOM_ENABLE_OVERRIDE
Used to force IBSCOM enabled for lab testing
volatile-zeroed
HB_EXISTING_IMAGE
Indicates which logical nodes have a hostboot image.
volatile-zeroed
HB_TARGET_SCOMABLE
This attribute indicates if the target can be SCOMed.
It's used in FSP only but declared here because the attribute
is defined in chip_attributes.xml, which is a common file
between FSP and HB (without this, HB will get a compilation error).
0x0
volatile-zeroed
ATTR_TARGET_SCOMABLE
DIRECT
OCC_COMMON_AREA_PHYS_ADDR
Physical address where OCC Common Area is placed in mainstore.
volatile-zeroed
HOMER_PHYS_ADDR
Physical address where HOMER image is placed in mainstore.
volatile-zeroed
ATTR_HOMER_PHYS_ADDR
DIRECT
HOMER_VIRT_ADDR
Virtual address where HOMER memory is mapped into. If value is zero,
memory must be mapped into virtual space.
volatile-zeroed
IPMI_SENSOR_ARRAY
Enumeration defining the offsets into the
IPMI_SENSORS array.
NAME_OFFSET
0x00
NUMBER_OFFSET
0x01
SENSOR_NAME
Enumeration indicating the IPMI sensor name, which will
be used by hostboot when determining the sensor number to return.
he sensor name consists of one byte of sensor type plus one byte of
sub-type, to differentiate similar sensors under the same target.
Our implementaion uses the IPMI defined entity ID as the sub-type.
PROC_TEMP
0x0103
DIMM_TEMP
0x0120
CORE_TEMP
0x01D0
STATE
0x0500
MEMBUF_TEMP
0x01D1
PROC_STATE
0x0703
CORE_STATE
0x07D0
DIMM_STATE
0x0C20
MEMBUF_STATE
0x0CD1
FW_BOOT_PROGRESS
0x0F22
SYSTEM_EVENT
0x1201
OS_BOOT
0x1F23
HOST_STATUS
0x2223
OCC_ACTIVE
0x07D2
CORE_FREQ
0xC1D0
APSS_CHANNEL
0xC2D7
PCI_ACTIVE
0xC423
REBOOT_COUNT
0xC322
FAULT
0xC700
BACKPLANE_FAULT
0xC707
REF_CLOCK_FAULT
0xC7D4
PCI_CLOCK_FAULT
0xC7D5
TOD_CLOCK_FAULT
0xC7D6
APSS_FAULT
0xC7D7
DERATING_FACTOR
0xC815
REDUNDANT_PS_POLICY
0xCA22
TPM_REQUIRED
0xFFFF
SBE_FFDC_ADDR
Virtual address where SBE FFDC is placed in mainstore.
volatile-zeroed
SBE_COMM_ADDR
Virtual address where SBE Communications are placed in mainstore.
This area is used for SBE message passing and may contain an SBE
command or the response to it from HBRT.
volatile-zeroed
SERIAL_NUMBER
The serial number for a particular FRU target
18
volatile-zeroed
ATTR_SERIAL_NUMBER
DIRECT
PART_NUMBER
The part number for a particular FRU target
20
volatile-zeroed
ATTR_PART_NUMBER
DIRECT
VPD_SWITCHES
Attribute storing VPD state information
VPD flags
pnorCacheValid
Set when this target's VPD data has been loaded
from EEPROM into the PNOR.
uint8_t
1
0
pnorCacheValidRT
See pnorCacheValid. Allows runtime version to be
set separately from common version.
uint8_t
1
0
disableWriteToPnorRT
Set to disable write-thru to PNOR at runtime
uint8_t
1
0
reserved
Reserved for future expansion
uint8_t
5
0
volatile-zeroed
SPCWKUP_COUNT
Keep track of the calls to Special Wakeup. Increment for each
call to enable, decrement for each call to disable. Not
thread-safe, used at runtime which is single-threaded.
volatile-zeroed
MSS_VOLT_VPP_SLOPE_EFF_CONFIG
Units: uV/DRAM
0
volatile-zeroed
MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG
Units: mV
0
volatile-zeroed
MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG
Units: 1/Amps
0
volatile-zeroed
MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG
Units: mV
0
volatile-zeroed
MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG
Maximum voltage limit for the dynamic VID DDR3 VDDR
voltage setpoint. In mV.
0
volatile-zeroed
MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG
Units: 1/Amps
0
volatile-zeroed
MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG
Units: mV
0
volatile-zeroed
MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG
Maximum voltage limit for the dynamic VID DDR4 VDDR voltage
setpoint. In mV.
0
volatile-zeroed
CLEAR_DIMM_SPD_ENABLE
Used to enable clearing of SPD on all present DIMMs. This attribute is
set via attribute override.
volatile-zeroed
WOF_FREQUENCY_UPLIFT_SELECTED
The selected WOF frequency uplift table.
22,13
volatile-zeroed
HBRT_HYP_ID
Effective ID used by the hypervisor to specify a given target. A value
of 0xFFFFFFFFFFFFFFFF means invalid/unknown.
0
volatile-zeroed
IS_DRTM_MPIPL_HB
Indicates if this is a DRTM MPIPL flow or not.
0x00 = Not a DRTM MPIPL
0x01 = DRTM MPIPL
0
volatile-zeroed
DRTM_PAYLOAD_ADDR_MB_HB
Physical address of DRTM payload in megabytes. 0 MB is not considered to
be a valid DRTM payload address
0
volatile-zeroed
FORCE_PRE_PAYLOAD_DRTM
If Hostboot is compiled with CONFIG_DRTM_TRIGGERING, controls
whether Hostboot will initiate a DRTM late launch sequence in place of
loading the payload. This attribute should always be compiled in not to
force the late launch sequence; it is designed to be changed via
attribute overrides only, to facilitate testing.
0x00: Do not force a DRTM late launch sequence
0x01: Force a DRTM late launch sequence (if not a DRTM boot)
0
volatile-zeroed
ATTN_CHK_ALL_PROCS
Used to tell ATTN code whether to chk MASTER(0) OR all PROCs(1)
when the checkForIplAttns routine is called.
volatile-zeroed
MASTER_MBOX_SCRATCH
Value of the master mailbox scratch regs
at the beginning of the boot. Need to save these
away since HB uses some of them for communication purposes.
8
volatile-zeroed
HB_RSV_MEM_NEXT_SECTION
The next HB reserved memory section available to assign
a new reserved memory range.
volatile-zeroed
HB_TPM_INIT_ATTEMPTED
Whether TPM initialization was attempted or not
0x00 (false) = Did not attempt to initialize TPM
0x01 (true) = Attempted to initialize TPM
volatile-zeroed
TPM_ROLE
Enumeration of possible roles a TPM can play within a node. A TPM has
the primary role if it's connected to the acting master processor,
otherwise it has the backup role.
TPM_PRIMARY
0
TPM_BACKUP
1
TPM_ROLE
Whether the TPM is primary or backup within its parent node. It is
dynamically computed during the boot.
volatile-zeroed
HB_TPM_MUTEX
Mutex to guard TPM access
volatile-zeroed
HB_TPM_LOG_MGR_PTR
Pointer to TPM log manager
0
volatile-zeroed
HB_SECURITY_MODE
HB specific attribute which is aliased to the FAPI attribute
ATTR_SECURITY_MODE and customized into the SBE image. If 0b0, SBE
will disable proc security (via SAB bit) if mailbox scratch register 3
bit 6 is set. Otherwise, if 0b1, SBE will not override proc security.
TODO RTC 170650: When SBE image is signed in all environments, set
default to 0b1 and rely on SBE signing header to configure the final
value, This may require hbOnly support for volatile attributes.
0x00
volatile-zeroed
ATTR_SECURITY_MODE
DIRECT
ALLOW_ATTR_OVERRIDES_IN_SECURE_MODE
Indicates if Attribute Overrides are allowed when the system is booted
in secure mode. The default is 0x0, where attribute overrides are not
allowed. However, the SBE can read mailbox scratch register 3 bit 7
to set it to 0x1, meaning that attribute overrides are allowed. The SBE
passes this information up to hostboot via the bootloader.
0x00 = Attribute Overrides are not allowed (default)
0x01 = Attribute Overrides are allowed
0x00
volatile-zeroed