ALLOW_ATTR_OVERRIDES_IN_SECURE_MODE Indicates if Attribute Overrides are allowed when the system is booted in secure mode. The default is 0x0, where attribute overrides are not allowed. However, the SBE can read mailbox scratch register 3 bit 7 to set it to 0x1, meaning that attribute overrides are allowed. The SBE passes this information up to hostboot via the bootloader. 0x00 = Attribute Overrides are not allowed (default) 0x01 = Attribute Overrides are allowed 0x00 volatile-zeroed ASSUME_SBE_QUIESCED Returns whether to treat SBE as quiesced or not. When Hostboot goes through an SBE update (always during key transition, possibly during normal flow), it may attempt to quiesce the SBE. Whether or not this was successful, firmware should treat the SBE as if it had been quiesced (and inhibit attribute synchronization during shutdown, etc.) Valid values (bool): 0x00: Do not assume SBE is quiesced !0x00: Assume SBE is quiesced 0 volatile-zeroed ATTN_CHK_ALL_PROCS Used to tell ATTN code whether to chk MASTER(0) OR all PROCs(1) when the checkForIplAttns routine is called. volatile-zeroed CENTAUR_REGISTER_CACHE_PTR Pointer to Secure Boot Centaur SCOM register cache volatile-zeroed Are we doing checkstop analysis on systems as we are booting back up based on information captured in FIRDATA section. CHKSTOP_ANALYSIS_ON_STARTUP volatile-zeroed Enum for CHKSTOP_ANALYSIS_ON_STARTUP NOT_ANALYZING_DEFAULT 0 ANALYZING_CHECKSTOP 1 CHKSTOP_ANALYSIS_ON_STARTUP CLEAR_DIMM_SPD_ENABLE Used to enable clearing of SPD on all present DIMMs. This attribute is set via attribute override. volatile-zeroed DIMM_SPD_BYTE_SIZE The size of DIMM (in bytes) within the SPD. This a raw value, 512 = 512 bytes, 1024 = 1024 bytes or 1 kilobyte, etc. This is set programatically, not designed for a static value. volatile-zeroed DRTM_PAYLOAD_ADDR_MB_HB Physical address of DRTM payload in megabytes. 0 MB is not considered to be a valid DRTM payload address 0 volatile-zeroed EARLY_TESTCASES_ISTEP Indicates which istep we should execute the CXX testcases after, if CONFIG_EARLY_TESTCASES is set. Format: 0xMMmm, where MM=major step, mm=minor step, e.g. 6.9=0x0609. 0x0609 non-volatile EEPROM_PAGE_ARRAY Used to keep track of which EEPROM page the current I2C master bus is set to 0 = PAGE_ZERO 1 = PAGE_ONE 2 = UNKNOWN_PAGE 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2 4,4 volatile FORCE_PRE_PAYLOAD_DRTM If Hostboot is compiled with CONFIG_DRTM_TRIGGERING, controls whether Hostboot will initiate a DRTM late launch sequence in place of loading the payload. This attribute should always be compiled in not to force the late launch sequence; it is designed to be changed via attribute overrides only, to facilitate testing. 0x00: Do not force a DRTM late launch sequence 0x01: Force a DRTM late launch sequence (if not a DRTM boot) 0 volatile-zeroed FREQ_MCA_MHZ The frequency of the memory controller channel. In synchronous mode, this is equivalent to ATTR_FREQ_PB_MHZ. This may be independently set per pair of memory channels if operating in asynchronous mode, but this configuration is not anticipated. This clock drives the MCU queues, and all the associated logic that drives the inputs to the DMI and reads its outputs non-volatile ATTR_FREQ_MCA_MHZ DIRECT FSI_MASTER_MUTEX Mutex for FSI Master Operations volatile-zeroed FSI_SCOM_MUTEX Mutex for FSI-based SCOM Operations volatile-zeroed HBRT_HYP_ID Effective ID used by the hypervisor to specify a given target. A value of 0xFFFFFFFFFFFFFFFF means invalid/unknown. 0 volatile-zeroed HB_EXISTING_IMAGE Indicates which logical nodes have a hostboot image. volatile-zeroed HB_INITIATED_PM_RESET Indicates that a chip has already been put into reset elsewhere such that the next reset request will be skipped. volatile-zeroed HB_INITIATED_PM_RESET Enum for HB_INITIATED_PM_RESET INACTIVE 0 IN_PROGRESS 1 COMPLETE 2 HB_MUTEX_TEST_LOCK Host boot mutex for testing volatile-zeroed HB_NODE_COMM_ABUS_MUTEX Mutex to guard Node Comm ABUS register access volatile-zeroed HB_NODE_COMM_XBUS_MUTEX Mutex to guard Node Comm XBUS register access volatile-zeroed HB_RECURSIVE_MUTEX_TEST_LOCK Host boot recursive mutex for testing volatile-zeroed HB_RSV_MEM_NEXT_SECTION The next HB reserved memory section available to assign a new reserved memory range. volatile-zeroed HB_SBE_SEEPROM_VERSION_MISMATCH Describes if the processor's SBE's seeprom versions match or not 0x0 = MATCH 0x1 = MISMATCH volatile-zeroed HB_TARGET_SCOMABLE This attribute indicates if the target can be SCOMed. It's used in FSP only but declared here because the attribute is defined in chip_attributes.xml, which is a common file between FSP and HB (without this, HB will get a compilation error). 0x0 volatile-zeroed ATTR_TARGET_SCOMABLE DIRECT HB_TPM_INIT_ATTEMPTED Whether TPM initialization was attempted or not 0x00 (false) = Did not attempt to initialize TPM 0x01 (true) = Attempted to initialize TPM volatile-zeroed HB_TPM_LOG_MGR_PTR Pointer to TPM log manager 0 volatile-zeroed HB_TPM_MUTEX Mutex to guard TPM access volatile-zeroed HIDDEN_ERRLOGS_ENABLE Used to decide whether or not to prevent INFORMATIONAL/RECOVERED error logs from being sent to the BMC via SEL/eSEL, saved to the PNOR, and displayed to the console. 0 = Prevent INFORMATIONAL/RECOVERED error logs from being processed. 1 = Send only INFORMATIONAL error logs. 2 = Send only RECOVERED error logs. 3 = Allow all hidden error logs to be processed. 0 volatile HIDDEN_ERRLOGS_ENABLE Enumeration of HIDDEN_ERRLOGS_ENABLE NO_HIDDEN_LOGS 0 ALLOW_INFORMATIONAL 1 ALLOW_RECOVERED 2 ALLOW_ALL_LOGS 3 HOMER_HCODE_LOADED Attribute to check if HCODE is loaded in HOMER volatile-zeroed HOMER_VIRT_ADDR Virtual address where HOMER memory is mapped into. If value is zero, memory must be mapped into virtual space. volatile-zeroed I2C_ENGINE_MUTEX_0 Mutex for I2C Master engine 0 volatile-zeroed I2C_ENGINE_MUTEX_1 Mutex for I2C Master engine 1 volatile-zeroed I2C_ENGINE_MUTEX_2 Mutex for I2C Master engine 2 volatile-zeroed I2C_ENGINE_MUTEX_3 Mutex for I2C Master engine 3 volatile-zeroed I2C_PAGE_MUTEX_0 Mutex to protect page select operations for I2C Master engine 0 volatile-zeroed I2C_PAGE_MUTEX_1 Mutex to protect page select operations for I2C Master engine 1 volatile-zeroed I2C_PAGE_MUTEX_2 Mutex to protect page select operations for I2C Master engine 2 volatile-zeroed I2C_PAGE_MUTEX_3 Mutex to protect page select operations for I2C Master engine 3 volatile-zeroed IBSCOM_ENABLE_OVERRIDE Used to force IBSCOM enabled for lab testing volatile-zeroed IBSCOM_MUTEX Mutex for Inband SCOM Operations volatile-zeroed IBSCOM_VIRTUAL_ADDR Cached Virtual Address of Inband Scom memory space for this Chip volatile-zeroed IPC_NODE_BUFFER_GLOBAL_ADDRESS Global IPC Buffer Addresseses for each Node dimension: node number (0:7) 8 volatile-zeroed IPMI_SENSOR_ARRAY Enumeration defining the offsets into the IPMI_SENSORS array. NAME_OFFSET 0x00 NUMBER_OFFSET 0x01 IS_DRTM_MPIPL_HB Indicates if this is a DRTM MPIPL flow or not. 0x00 = Not a DRTM MPIPL 0x01 = DRTM MPIPL 0 volatile-zeroed IS_MPIPL_HB 1 = in Memory Preserving IPL mode. 0 = in normal IPL mode. volatile-zeroed ATTR_IS_MPIPL DIRECT IS_SLAVE_DRAWER 0 = is master node, 1 = is slave node 0 volatile-zeroed MASTER_MBOX_SCRATCH Value of the master mailbox scratch regs at the beginning of the boot. Need to save these away since HB uses some of them for communication purposes. 8 volatile-zeroed MEMD_OFFSET Working offset for MEMD section, this allows us to move between the different MEMD instances and the MEMD header. volatile-zeroed MMIO_VM_ADDR Virtual memory address this device has been mapped to. 0 volatile-zeroed MPIPL_HB_MDRT_COUNT Actual MDRT count in Memory Preserving IPL mode. 0 volatile-zeroed MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG Maximum voltage limit for the dynamic VID DDR3 VDDR voltage setpoint. In mV. 0 volatile-zeroed MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG Maximum voltage limit for the dynamic VID DDR4 VDDR voltage setpoint. In mV. 0 volatile-zeroed MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG Units: mV 0 volatile-zeroed MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG Units: 1/Amps 0 volatile-zeroed MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG Units: mV 0 volatile-zeroed MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG Units: 1/Amps 0 volatile-zeroed MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG Units: mV 0 volatile-zeroed MSS_VOLT_VPP_SLOPE_EFF_CONFIG Units: uV/DRAM 0 volatile-zeroed OCC_COMMON_AREA_PHYS_ADDR Physical address where OCC Common Area is placed in mainstore. volatile-zeroed While in Secureboot, this value is set to 1 the first time attribute override is attempted and error logged. OVERRIDES_ATTEMPTED_FLAG volatile-zeroed 0x00 0 1 PART_NUMBER The part number for a particular FRU target 48 volatile-zeroed ATTR_PART_NUMBER DIRECT PDA_CAPTURED_THREAD_REG_ARRAY_ADDR Processor Dump Area Table's captured thread register state array address. 0 volatile-zeroed PDA_CAPTURED_THREAD_REG_ARRAY_SIZE Processor Dump Area Table's captured thread register state array size. 0 volatile-zeroed PDA_THREAD_REG_ENTRY_SIZE Processor Dump Area Table's thread register entry size. 0 volatile-zeroed PDA_THREAD_REG_STATE_ENTRY_FORMAT Processor Dump Area Table's thread entry format. 0 volatile-zeroed SBE_COMM_ADDR Virtual address where SBE Communications are placed in mainstore. This area is used for SBE message passing and may contain an SBE command or the response to it from HBRT. volatile-zeroed SBE_FFDC_ADDR Virtual address where SBE FFDC is placed in mainstore. volatile-zeroed SCAN_MUTEX Mutex for SCAN operations 0 volatile-zeroed SCOM_IND_MUTEX Mutex for Indirect SCOM read operation volatile-zeroed SENSOR_NAME Enumeration indicating the IPMI sensor name, which will be used by hostboot when determining the sensor number to return. The sensor name consists of one byte of sensor type plus one byte of sub-type, to differentiate similar sensors under the same target. Our implementaion uses the IPMI defined entity ID as the sub-type. PROC_TEMP 0x0103 DIMM_TEMP 0x0120 CORE_TEMP 0x01D0 STATE 0x0500 MEMBUF_TEMP 0x01D1 GPU_TEMP 0x01D8 GPU_MEM_TEMP 0x01D9 VRM_VDD_TEMP 0x01DA GPU_STATE 0x17D8 PROC_STATE 0x0703 CORE_STATE 0x07D0 HOST_AUTO_REBOOT_CONTROL 0x0921 DIMM_STATE 0x0C20 HB_VOLATILE 0x0C21 MEMBUF_STATE 0x0CD1 FW_BOOT_PROGRESS 0x0F22 SYSTEM_EVENT 0x1201 OS_BOOT 0x1F23 HOST_STATUS 0x2223 OCC_ACTIVE 0x07D2 CORE_FREQ 0xC1D0 APSS_CHANNEL 0xC2D7 PCI_ACTIVE 0xC423 REBOOT_COUNT 0xC322 FAULT 0xC700 BACKPLANE_FAULT 0xC707 REF_CLOCK_FAULT 0xC7D4 PCI_CLOCK_FAULT 0xC7D5 TOD_CLOCK_FAULT 0xC7D6 APSS_FAULT 0xC7D7 VRM_VDD_FAULT 0xC707 DERATING_FACTOR 0xC815 REDUNDANT_PS_POLICY 0xCA22 TURBO_ALLOWED 0xCB03 TPM_REQUIRED 0xCC03 PCI_BIFURCATED 0xCD03 SERIAL_NUMBER The serial number for a particular FRU target 18 volatile-zeroed ATTR_SERIAL_NUMBER DIRECT SPCWKUP_COUNT Keep track of the calls to Special Wakeup. Increment for each call to enable, decrement for each call to disable. Not thread-safe, used at runtime which is single-threaded. volatile-zeroed TPM_MODEL Indicates TPM Model (or family) for a TPM Target 0x00 = Undetermined (reserved if actively detected in the future) 0x01 = Nuvoton 65x (default) 0x02 = Nuvoton 75x 1 non-volatile TPM_ROLE Enumeration of possible roles a TPM can play within a node. A TPM has the primary role if it's connected to the acting master processor, otherwise it has the backup role. TPM_PRIMARY 0 TPM_BACKUP 1 TPM_ROLE Whether the TPM is primary or backup within its parent node. It is dynamically computed during the boot. volatile-zeroed VPD_SWITCHES Attribute storing VPD state information VPD flags pnorCacheValid Set when this target's VPD data has been loaded from EEPROM into the PNOR. uint8_t 1 0 pnorCacheValidRT See pnorCacheValid. Allows runtime version to be set separately from common version. uint8_t 1 0 disableWriteToPnorRT Set to disable write-thru to PNOR at runtime uint8_t 1 0 reserved Reserved for future expansion uint8_t 5 0 volatile-zeroed WOF_FREQUENCY_UPLIFT_SELECTED The selected WOF frequency uplift table. 22,13 volatile-zeroed XSCOM_VIRTUAL_ADDR Cached Virtual Address of Xscom memory space for this Chip volatile-zeroed