CLASS
Enumeration indicating the target's class
NA
0
CARD
1
ENC
2
CHIP
3
UNIT
4
DEV
5
SYS
6
LOGICAL_CARD
7
MAX
8
NA
TYPE
Enumeration indicating the target's type
NA
0
SYS
NODE
DIMM
SCM
DCM
MEMBUF
PROC
MEMVRM
PROCVRM
EX
CORE
L2
L3
L4
MCS
MBS
MBA
MEM_PORT
PERVASIVE
POWERBUS
XBUS
ABUS
PCI
TP
DMI
DPSS
APSS
OCC
PSI
FSP
PNOR
LAST_IN_RANGE
NA
MODEL
Enumeration indicating the target's model
NA
0
RESERVED
16
VENICE
MURANO
CENTAUR
48
JEDEC
80
CDIMM
POWER8
112
NA
ENGINE_TYPE
Enumeration indicating the target's engine type
NA
0
ENGINE_IIC
1
ENGINE_SCOM
2
NA
FSI_MASTER_TYPE
Enumeration indicating the master's FSI type
MFSI
0
CMFSI
1
NO_MASTER
2
NO_MASTER
CLASS
Attribute indicating the target's class
CLASS
non-volatile
TYPE
Attribute indicating the target's type
TYPE
non-volatile
MODEL
Attribute indicating the target's model
MODEL
non-volatile
ENGINE_TYPE
Attribute indicating the target's engine type
ENGINE_TYPE
non-volatile
SCRATCH_UINT8_1
Scratch attribute that can be used for dev/test
0
volatile-zeroed
ATTR_SCRATCH_UINT8_1
DIRECT
SCRATCH_UINT8_2
Scratch attribute that can be used for dev/test
0
volatile-zeroed
ATTR_SCRATCH_UINT8_2
DIRECT
SCRATCH_UINT32_1
Scratch attribute that can be used for dev/test
0
volatile-zeroed
ATTR_SCRATCH_UINT32_1
DIRECT
SCRATCH_UINT32_2
Scratch attribute that can be used for dev/test
0
volatile-zeroed
ATTR_SCRATCH_UINT32_2
DIRECT
SCRATCH_UINT64_1
Scratch attribute that can be used for dev/test
0
volatile-zeroed
ATTR_SCRATCH_UINT64_1
DIRECT
SCRATCH_UINT64_2
Scratch attribute that can be used for dev/test
0
volatile-zeroed
ATTR_SCRATCH_UINT64_2
DIRECT
SCRATCH_UINT8_ARRAY_1
Scratch attribute that can be used for dev/test
0
32
volatile-zeroed
ATTR_SCRATCH_UINT8_ARRAY_1
DIRECT
SCRATCH_UINT8_ARRAY_2
Scratch attribute that can be used for dev/test
0
2, 3, 4
volatile-zeroed
ATTR_SCRATCH_UINT8_ARRAY_2
DIRECT
SCRATCH_UINT32_ARRAY_1
Scratch attribute that can be used for dev/test
0
8
volatile-zeroed
ATTR_SCRATCH_UINT32_ARRAY_1
DIRECT
SCRATCH_UINT32_ARRAY_2
Scratch attribute that can be used for dev/test
0
2,3
volatile-zeroed
ATTR_SCRATCH_UINT32_ARRAY_2
DIRECT
SCRATCH_UINT64_ARRAY_1
Scratch attribute that can be used for dev/test
0
4
volatile-zeroed
ATTR_SCRATCH_UINT64_ARRAY_1
DIRECT
SCRATCH_UINT64_ARRAY_2
Scratch attribute that can be used for dev/test
0
2,2
volatile-zeroed
ATTR_SCRATCH_UINT64_ARRAY_2
DIRECT
DUMMY_RW
Dummy attribute with read/write permissions
5
1,3,5
non-volatile
ATTR_DUMMY_SCRATCH_PLAT_INIT_UINT8
DIRECT
DUMMY_WO
Dummy attribute with write-only permissions
0
non-volatile
DUMMY_RO
Dummy attribute with read-only permissions
0
non-volatile
DUMMY_HEAP_ZERO_DEFAULT
Dummy attribute on the heap with zero initialization
5
volatile-zeroed
PHYS_PATH
Physical hierarchical path to the target
EntityPath
non-volatile
AFFINITY_PATH
Hierarchical path to the target with respect to logical affinity
EntityPath
non-volatile
POWER_PATH
Hierarchical path to the target with respect to power
EntityPath
non-volatile
PRIMARY_CAPABILITIES
Attribute which describes capabilities of a target
Structure which defines a target's primary capabilities.
A target can only support at most FSI SCOM and one of the other two SCOM
types. Applicable for all targets. Structure is read-only.
supportsFsiScom
0b0: Target does not support FSI SCOM;
0b1: Target supports FSI SCOM
uint8_t
1
0
supportsXscom
0b0: Target does not support XSCOM;
0b1: Target supports FSI XSCOM
uint8_t
1
0
supportsInbandScom
0b0: Target does not support inband SCOM
uint8_t
1
0
reserved
Reserved for future use
uint8_t
5
0
non-volatile
SCOM_SWITCHES
Attribute storing information about which SCOM path to use
Structure which defines which SCOM to use at a point in
time. Only applicable if target supports one or more SCOM types. Only
one bit (of the first three) can ever be set at any one time.
useFsiScom
0b0: Do not use FSI SCOM at this time. 0b1: Use FSI
SCOM at this time
uint8_t
1
0
useXscom
0b0: Do not use XSCOM at this time. 0b1: Use XSCOM at
this time
uint8_t
1
0
useInbandScom
0b0: Do not use inband SCOM at this time. 0b1: Use
inband SCOM at this time
uint8_t
1
0
reserved
Reserved for future expansion
uint8_t
5
0
volatile
XSCOM_VIRTUAL_ADDR
Cached Virtual Address of Xscom memory space for this Chip
0
volatile-zeroed
FSI_MASTER_CHIP
Chip which contains the FSI master logic that drives this slave
EntityPath
non-volatile
FSI_MASTER_TYPE
Type of Master FSI connection to this slave (MFSI or cMFSI)
FSI_MASTER_TYPE
non-volatile
FSI_MASTER_PORT
Which port is this chip hanging off of
0
non-volatile
FSI_SLAVE_CASCADE
Slave cascade position
0
non-volatile
FSI_OPTION_FLAGS
Reserved for any special flags we might need to access FSI
0
non-volatile
FSI_MASTER_MUTEX
Mutex for FSI Master Operations
0
volatile-zeroed
EXECUTION_PLATFORM
Which execution platform the HW Procedure is running on
Some HWPs (e.g. special wakeup) use different registers for different
platforms to avoid arbitration problems when multiple platforms do
the same thing concurrently
HOST = 0x01, FSP = 0x02, OCC = 0x03
non-volatile
ATTR_EXECUTION_PLATFORM
DIRECT
IS_SIMULATION
env: 1 = Awan/HWSimulator. 0 = Simics/RealHW.
0
non-volatile
ATTR_IS_SIMULATION
DIRECT
HWAS_STATE
HardWare Availability Service State Attribute.
Keeps track of Target values poweredOn, present, functional,
and changedSinceLastIPL
struct - so far contains 5 booleans
poweredOn
boolean: Target is powered on, or Not.
comes up as powered off.
uint8_t
1
0
present
Target is present in the system.
comes up as Not PRESENT.
uint8_t
1
0
functional
Target is Functional.
comes up as Not FUNCTIONAL
uint8_t
1
0
changedSinceLastIPL
Target has changed since last IPL.
comes up as FALSE.
uint8_t
1
0
dumpfunctional
FSP Only, used by DUMP applet to indicate targets dump capability.
Comes up as 0 which indicates the target is not dump capable
uint8_t
1
0
volatile
NUMERIC_POD_TYPE_TEST
Attribute which tests numeric POD types
Numeric POD type test structure
fsiPath
Entity path for testing purposes
EntityPath
physical:sys-0
className
Class for testing purposes
CLASS
CHIP
uint8
Test uint8
uint8_t
0xAB
uint16
Test uint16
uint16_t
0xABCD
uint32
Test uint32
uint32_t
0xABCDEF01
uint64
Test uint64
uint64_t
0xABCDEF0123456789
int8
Test int8
int8_t
-124
int16
Test int16
int16_t
-32764
int32
Test int32
int32_t
-2147483644
int64
Test int64
int64_t
-9223372036854775804
non-volatile
DECONFIG_GARDABLE
If the Target is Deconfigurable and GARDable
0
non-volatile
HB_MUTEX_TEST_LOCK
Host boot mutex for testing
0
volatile-zeroed
ISTEP_MODE
If True, puts HostBoot into SPLess SingleStep mode.
0
non-volatile
EEPROM_ADDR_INFO0
Information needed to address the EEPROM slaves
Structure to define the addressing for an I2C slave device.
i2cMasterPath
Entity path to the processor containing the I2C master (FOR DIMMS
ONLY)
EntityPath
physical:sys-0
port
Port from the I2C Master device. This is a 6-bit value.
uint8_t
0x80
devAddr
Device address on the I2C bus. This is a 7-bit value.
uint8_t
0x80
engine
I2C master engine. This is a 2-bit value.
uint8_t
0x80
non-volatile
EEPROM_ADDR_INFO1
Information needed to address the EERPROM slaves
Structure to define the addressing for an I2C slave device.
i2cMasterPath
Entity path to the processor containing the I2C master (FOR DIMMS
ONLY)
EntityPath
physical:sys-0
port
Port from the I2C Master device. This is a 6-bit value.
uint8_t
0x80
devAddr
Device address on the I2C bus. This is a 7-bit value.
uint8_t
0x80
engine
I2C master engine. This is a 2-bit value.
uint8_t
0x80
non-volatile
I2C_ENGINE_MUTEX_0
Mutex for I2C Master engine 0
0
volatile-zeroed
I2C_ENGINE_MUTEX_1
Mutex for I2C Master engine 1
0
volatile-zeroed
I2C_ENGINE_MUTEX_2
Mutex for I2C Master engine 2
0
volatile-zeroed
MSS_VOLT
DRAM Voltage. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_MSS_VOLT
DIRECT
MSS_FREQ
Frequency of memory channel in MHz. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_MSS_FREQ
DIRECT
MSS_DIMM_MFG_ID_CODE
DIMM Manufacturer ID Code. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_MSS_DIMM_MFG_ID_CODE
DIRECT
EFF_DIMM_RANKS_CONFIGED
DIMM ranks configured. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_EFF_DIMM_RANKS_CONFIGED
DIRECT
EFF_NUM_RANKS_PER_DIMM
Number of ranks per DIMM. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_EFF_NUM_RANKS_PER_DIMM
DIRECT
EFF_DIMM_TYPE
Type of DIMM. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DIMM_TYPE
DIRECT
EFF_DRAM_WIDTH
DRAM Device Width. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_WIDTH
DIRECT
EFF_DRAM_GEN
DRAM Generation. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_GEN
DIRECT
EFF_PRIMARY_RANK_GROUP0
Primary RankGroup0. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_PRIMARY_RANK_GROUP0
DIRECT
EFF_PRIMARY_RANK_GROUP1
Primary RankGroup1. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_PRIMARY_RANK_GROUP1
DIRECT
EFF_PRIMARY_RANK_GROUP2
Primary RankGroup2. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_PRIMARY_RANK_GROUP2
DIRECT
EFF_PRIMARY_RANK_GROUP3
Primary RankGroup3. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_PRIMARY_RANK_GROUP3
DIRECT
EFF_SECONDARY_RANK_GROUP0
Secondary RankGroup0. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_SECONDARY_RANK_GROUP0
DIRECT
EFF_SECONDARY_RANK_GROUP1
Secondary RankGroup1. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_SECONDARY_RANK_GROUP1
DIRECT
EFF_SECONDARY_RANK_GROUP2
Secondary RankGroup2. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_SECONDARY_RANK_GROUP2
DIRECT
EFF_SECONDARY_RANK_GROUP3
Secondary RankGroup3. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_SECONDARY_RANK_GROUP3
DIRECT
EFF_TERTIARY_RANK_GROUP0
Tertiary RankGroup0. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_TERTIARY_RANK_GROUP0
DIRECT
EFF_TERTIARY_RANK_GROUP1
Tertiary RankGroup1. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_TERTIARY_RANK_GROUP1
DIRECT
EFF_TERTIARY_RANK_GROUP2
Tertiary RankGroup2. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_TERTIARY_RANK_GROUP2
DIRECT
EFF_TERTIARY_RANK_GROUP3
Tertiary RankGroup3. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_TERTIARY_RANK_GROUP3
DIRECT
EFF_QUATERNARY_RANK_GROUP0
Quaternary RankGroup0. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_QUATERNARY_RANK_GROUP0
DIRECT
EFF_QUATERNARY_RANK_GROUP1
Quaternary RankGroup1. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_QUATERNARY_RANK_GROUP1
DIRECT
EFF_QUATERNARY_RANK_GROUP2
Quaternary RankGroup2. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_QUATERNARY_RANK_GROUP2
DIRECT
EFF_QUATERNARY_RANK_GROUP3
Quaternary RankGroup3. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_EFF_QUATERNARY_RANK_GROUP3
DIRECT
EFF_ODT_RD
Rank Read ODT. Initialized and used by HWPs.
0
2,2,4
volatile-zeroed
ATTR_EFF_ODT_RD
DIRECT
EFF_ODT_WR
Rank Write ODT. Initialized and used by HWPs.
0
2,2,4
volatile-zeroed
ATTR_EFF_ODT_WR
DIRECT
EFF_DRAM_RON
DRAM Ron. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_EFF_DRAM_RON
DIRECT
EFF_DRAM_RTT_NOM
DRAM Rtt_Nom. Initialized and used by HWPs.
0
2,2,4
volatile-zeroed
ATTR_EFF_DRAM_RTT_NOM
DIRECT
EFF_DRAM_RTT_WR
DRAM Rtt_WR. Initialized and used by HWPs.
0
2,2,4
volatile-zeroed
ATTR_EFF_DRAM_RTT_WR
DIRECT
EFF_DRAM_WR_VREF
DRAM Write Vref. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_WR_VREF
DIRECT
EFF_CEN_DRV_IMP_DQ_DQS
Centaur DQ and DQS Drive Impedance. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_CEN_DRV_IMP_DQ_DQS
DIRECT
EFF_CEN_DRV_IMP_CMD
Centaur Command Drive Impedance. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_CEN_DRV_IMP_CMD
DIRECT
EFF_CEN_DRV_IMP_CNTL
Centaur Control Drive Impedance. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_CEN_DRV_IMP_CNTL
DIRECT
EFF_CEN_RCV_IMP_DQ_DQS
Centaur DQ and DQS Receiver Impedance. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_CEN_RCV_IMP_DQ_DQS
DIRECT
EFF_CEN_SLEW_RATE_DQ_DQS
Centaur DQ and DQS Slew Rate. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_CEN_SLEW_RATE_DQ_DQS
DIRECT
EFF_CEN_SLEW_RATE_CMD
Centaur Command Slew Rate. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_CEN_SLEW_RATE_CMD
DIRECT
EFF_CEN_SLEW_RATE_CNTL
Centaur Control Slew Rate. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_CEN_SLEW_RATE_CNTL
DIRECT
EFF_CEN_RD_VREF
Centaur Read Vref. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_CEN_RD_VREF
DIRECT
EFF_DIMM_SIZE
DIMM Size. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_EFF_DIMM_SIZE
DIRECT
EFF_DIMM_SIZE_CONFIGED
Actual Configured DIMM Size. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_EFF_DIMM_SIZE_CONFIGED
DIRECT
EFF_DRAM_DENSITY
DRAM Density. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_DENSITY
DIRECT
EFF_DRAM_TRCD
DRAM RAS to CAS Delay. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_TRCD
DIRECT
EFF_DRAM_TRRD
DRAM Row ACT to Row ACT Delay. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_TRRD
DIRECT
EFF_DRAM_TRP
DRAM Row Precharge Delay. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_TRP
DIRECT
EFF_DRAM_TRAS
DRAM ACT to Precharge Delay. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_TRAS
DIRECT
EFF_DRAM_TRC
DRAM ACT to ACT/Refresh Delay. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_TRC
DIRECT
EFF_DRAM_TRFI
Refresh Interval. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_TRFI
DIRECT
EFF_DRAM_TRFC
DRAM Refresh Recovery Delay. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_TRFC
DIRECT
EFF_DRAM_TWTR
DRAM Internal Write to Read Delay. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_TWTR
DIRECT
EFF_DRAM_TRTP
DRAM Internal Read to Precharge Delay. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_TRTP
DIRECT
EFF_DRAM_TFAW
DRAM Four ACT Window Delay. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_TFAW
DIRECT
EFF_DRAM_BL
DRAM Burst Length. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_BL
DIRECT
EFF_DRAM_CL
DRAM CAS Latency. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_CL
DIRECT
EFF_DRAM_AL
DRAM Additive Latency. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_AL
DIRECT
EFF_DRAM_CWL
DRAM CAS Write Latency. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_CWL
DIRECT
EFF_DRAM_RBT
DRAM Read Burst Type. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_RBT
DIRECT
EFF_DRAM_TM
DRAM Test Mode. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_TM
DIRECT
EFF_DRAM_DLL_RESET
DRAM DLL Reset. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_DLL_RESET
DIRECT
EFF_DRAM_WR
DRAM Write Recovery. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_WR
DIRECT
EFF_DRAM_DLL_PPD
DRAM DLL Precharge PD. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_DLL_PPD
DIRECT
EFF_DRAM_DLL_ENABLE
DRAM DLL Enable. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_DLL_ENABLE
DIRECT
EFF_DRAM_TDQS
DRAM TDQS. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_TDQS
DIRECT
EFF_DRAM_WR_LVL_ENABLE
DRAM Write Level Enable. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_WR_LVL_ENABLE
DIRECT
EFF_DRAM_OUTPUT_BUFFER
DRAM output buffer. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_OUTPUT_BUFFER
DIRECT
EFF_DRAM_PASR
DRAM Partial Array Self-Refresh. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_PASR
DIRECT
EFF_DRAM_ASR
DRAM Auto Self-Refresh. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_ASR
DIRECT
EFF_DRAM_SRT
DRAM Self-Refresh Temperature Range. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_SRT
DIRECT
EFF_MPR_LOC
Multi Purpose Register Location. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_MPR_LOC
DIRECT
EFF_MPR_MODE
Multi Purpose Register Mode. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_MPR_MODE
DIRECT
EFF_DIMM_RCD_CNTL_WORD_0_15
DIMM RCD Control Word. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15
DIRECT
EFF_SCHMOO_MODE
Specifies the schmoo mode to use during draminit_train_adv. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_SCHMOO_MODE
DIRECT
EFF_SCHMOO_TEST_VALID
Specifies the schmoo test to run during draminit_train_adv. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_SCHMOO_TEST_VALID
DIRECT
EFF_SCHMOO_PARAM_VALID
Specifies the schmoo parameters to use during draminit_train_adv. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_SCHMOO_PARAM_VALID
DIRECT
EFF_MEMCAL_INTERVAL
Specifies the memcal interval in clocks. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_MEMCAL_INTERVAL
DIRECT
EFF_ZQCAL_INTERVAL
Specifies the zqcal interval in clocks. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_ZQCAL_INTERVAL
DIRECT
MSS_THROTTLE_NUMERATOR
DIMM throttle numerator. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_MSS_THROTTLE_NUMERATOR
DIRECT
MSS_THROTTLE_DENOMINATOR
DIMM throttle denominator. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_MSS_THROTTLE_DENOMINATOR
DIRECT
MSS_THROTTLE_CHANNEL_NUMERATOR
Channel throttle numerator. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_MSS_THROTTLE_CHANNEL_NUMERATOR
DIRECT
MSS_THROTTLE_CHANNEL_DENOMINATOR
Channel throttle denominator. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_MSS_THROTTLE_CHANNEL_DENOMINATOR
DIRECT
MSS_WATT_TARGET
Channel total memory watts. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_MSS_WATT_TARGET
DIRECT
MSS_POWER_SLOPE
DIMM Power slope value. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_MSS_POWER_SLOPE
DIRECT
MSS_POWER_INT
DIMM Power intercept value. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_MSS_POWER_INT
DIRECT
MSS_DIMM_MAXBANDWIDTH_GBS
DIMM Max Bandwidth in GBs. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_MSS_DIMM_MAXBANDWIDTH_GBS
DIRECT
MSS_DIMM_MAXBANDWIDTH_MRS
DIMM Max Bandwidth in MRs. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_MSS_DIMM_MAXBANDWIDTH_MRS
DIRECT
MSS_CHANNEL_MAXBANDWIDTH_GBS
Channel Max Bandwidth in GBs. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_MSS_CHANNEL_MAXBANDWIDTH_GBS
DIRECT
MSS_CHANNEL_MAXBANDWIDTH_MRS
Channel Max Bandwidth MRs. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_MSS_CHANNEL_MAXBANDWIDTH_MRS
DIRECT
MSS_DIMM_MAXPOWER
DIMM Max Power output. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_MSS_DIMM_MAXPOWER
DIRECT
MSS_CHANNEL_MAXPOWER
Channel Max Power output. Initialized and used by HWPs.
0
2
volatile-zeroed
ATTR_MSS_CHANNEL_MAXPOWER
DIRECT
MSS_MEMSIZE_MBA
At the MBA level, how much memory is available. Initialized by HWP.
0
volatile-zeroed
ATTR_MSS_MEMSIZE_MBA
DIRECT
FSI_SCOM_MUTEX
Mutex for FSI-based SCOM Operations
0
volatile-zeroed
EC
attribute indicating the chip target's EC level
0
volatile-zeroed
ATTR_EC
DIRECT
CHIP_ID
attribute indicating the chip's ID
0
volatile-zeroed
ATTR_CHIP_ID
DIRECT
FSI_GP_REG_SCOM_ACCESS
attribute indicating if the chip's FSI GP regs have scom access
non-volatile
ATTR_FSI_GP_REG_SCOM_ACCESS
DIRECT
L2_R_T0_EPS
L2 tier0 read epsilon register value.
0
volatile-zeroed
ATTR_L2_R_T0_EPS
DIRECT
L2_R_T1_EPS
L2 tier1 read epsilon register value.
0
volatile-zeroed
ATTR_L2_R_T1_EPS
DIRECT
L2_R_T2_EPS
L2 tier2 read epsilon register value.
0
volatile-zeroed
ATTR_L2_R_T2_EPS
DIRECT
L2_FORCE_R_T2_EPS
L2 force tier2 read epsilon protect (all tiers).
0
volatile-zeroed
ATTR_L2_FORCE_R_T2_EPS
DIRECT
L2_W_EPS
L2 write epsilon register value.
0
volatile-zeroed
ATTR_L2_W_EPS
DIRECT
L3_R_T0_EPS
L3 tier0 read epsilon register value.
0
volatile-zeroed
ATTR_L3_R_T0_EPS
DIRECT
L3_R_T1_EPS
L3 tier1 read epsilon register value.
0
volatile-zeroed
ATTR_L3_R_T1_EPS
DIRECT
L3_R_T2_EPS
L3 tier2 read epsilon register value.
0
volatile-zeroed
ATTR_L3_R_T2_EPS
DIRECT
L3_FORCE_R_T2_EPS
L3 force tier2 read epsilon protect (all tiers).
0
volatile-zeroed
ATTR_L3_FORCE_R_T2_EPS
DIRECT
L3_W_EPS
L3 write epsilon register value.
0
volatile-zeroed
ATTR_L3_W_EPS
DIRECT
SCOM_IND_MUTEX
Mutex for Indirect SCOM read operation
0
volatile-zeroed
CHIP_UNIT
A unit (chiplet) 's offset number within the chip.
0
non-volatile
ATTR_CHIP_UNIT_POS
DIRECT
POSITION
Position of target relative to node
0
non-volatile
MBA_PORT
MBA port this DIMM is connected to
0
non-volatile
ATTR_MBA_PORT
DIRECT
MBA_DIMM
MBA port DIMM number of this DIMM
0
non-volatile
ATTR_MBA_DIMM
DIRECT
CEN_DQ_TO_DIMM_CONN_DQ
Centaur DQ to DIMM connector DQ mapping for a JEDEC DIMM.
Uint8 value for each Centaur DQ (0-79).
The value is the corresponding DIMM Connector DQ.
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,
20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,
60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79
80
non-volatile
PROC_EPS_TABLE_TYPE
Enumeration indicating the PROC_EPS_TABLE_TYPE
EPS_TYPE_LE
1
EPS_TYPE_HE
2
PROC_EPS_TABLE_TYPE
System attribute.
Processor epsilon table type. Used to calculate the processor nest
epsilon register values.
non-volatile
ATTR_PROC_EPS_TABLE_TYPE
DIRECT
PROC_FABRIC_PUMP_MODE
Enumeration indicating the PROC_FABRIC_PUMP_MODE
MODE1
1
MODE2
2
PROC_FABRIC_PUMP_MODE
System attribute.
Processor SMP Fabric broadcast scope configuration.
MODE1 = default = chip/group/system/remote group/foreign.
MODE2 = group/system/remote group/foreign.
Provided by the Machine Readable Workbook.
non-volatile
ATTR_PROC_FABRIC_PUMP_MODE
DIRECT
PROC_X_BUS_WIDTH
Enumeration indicating the PROC_X_BUS_WIDTH
W4BYTE
1
W8BYTE
2
PROC_X_BUS_WIDTH
System attribute.
Processor SMP X bus width.
Provided by the Machine Readable Workbook.
non-volatile
ATTR_PROC_X_BUS_WIDTH
DIRECT
ALL_MCS_IN_INTERLEAVING_GROUP
System attribute.
If all MCS chiplets are in an interleaving group (1=true, 0=false).
If true the SMP fabric is setup in normal mode.
If false the SMP fabric is setup in checkerboard mode.
Provided by the Machine Readable Workbook.
non-volatile
ATTR_ALL_MCS_IN_INTERLEAVING_GROUP
DIRECT
FABRIC_NODE_ID
Chip attribute.
Logical fabric node the chip belongs to.
Provided by the Machine Readable Workbook.
Can vary across drawers.
non-volatile
ATTR_FABRIC_NODE_ID
DIRECT
FABRIC_CHIP_ID
Chip attribute.
Logical fabric chip id for this chip (position within the fabric).
Provided by the Machine Readable Workbook.
Can vary across drawers.
non-volatile
ATTR_FABRIC_CHIP_ID
DIRECT
CHIP_HAS_SBE
Chip attribute.
If true, the chip has an SBE and the associated registers.
Provided by the Machine Readable Workbook.
non-volatile
ATTR_CHIP_HAS_SBE
DIRECT
FREQ_PROC_REFCLOCK
System attribute.
The frequency of the processor refclock in MHz.
Provided by the Machine Readable Workbook.
The corresponding HWPF attribute:
- Is read by the set_ref_clock HWP to find out the desired frequency.
- Can be overridden to adjust the refclock frequency.
non-volatile
ATTR_FREQ_PROC_REFCLOCK
DIRECT
FREQ_MEM_REFCLOCK
System attribute.
The frequency of the memory refclock in MHz.
Provided by the Machine Readable Workbook.
The corresponding HWPF attribute:
- Is read by the set_ref_clock HWP to find out the desired frequency.
- Can be overridden to adjust the refclock frequency.
non-volatile
ATTR_FREQ_MEM_REFCLOCK
DIRECT
FREQ_CORE_FLOOR
System attribute.
The lowest frequency that a core can be set to in MHz.
This is the same for all cores in the system.
TODO Provided by TBD. Current thinking is MRW or MVPD.
If MRW then this attribute will stay here.
If MVPD then this attribute will be deleted.
non-volatile
ATTR_FREQ_CORE_FLOOR
DIRECT
FREQ_PB
System attribute.
The frequency of a processor's PB chiplet in MHz.
This is the same for all PB chiplets in the system.
The corresponding HWPF attribute:
- Is set by a HWP that runs after SBE HWPs setup the PB PLL. It
reads ATTR_FREQ_PROC_REFCLOCK and the PB PLL settings.
volatile-zeroed
ATTR_FREQ_PB
DIRECT
FREQ_A
System attribute.
The frequency of a processor's A-bus chiplet in MHz.
This is the same for all A-bus chiplets in the system.
The corresponding HWPF attribute:
- Is set by the HWP that sets up the A-bus PLL.
volatile-zeroed
ATTR_FREQ_A
DIRECT
FREQ_X
System attribute.
The frequency of a processor's X-bus chiplet in MHz.
This is the same for all X-bus chiplets in the system.
The corresponding HWPF attribute:
- Is set by the HWP that sets up the X-bus PLL.
volatile-zeroed
ATTR_FREQ_X
DIRECT
MVPD_FREQ_CORE_NOMINAL
Chip attribute.
The nominal frequency of the processor cores in MHz.
TODO This attribute should be from MVPD.
When MVPD function is present, this attribute should be deleted.
The corresponding HWPF attribute request should map to a function
that calls the MVPD driver (in the same way as DIMM SPD).
For now, just default to 3GHz
3000
non-volatile
ATTR_MVPD_FREQ_CORE_NOMINAL
DIRECT
HUID
Hardware Unit ID
SSSSNNNNTTTTTTTTiiiiiiiiiiiiiiii
S=System
N=Node Number
T=Target Type (matches TYPE attribute)
i=Instance/Sequence number of target, relative to node
0xFFFFFFFF
non-volatile
SP_FUNCTIONS
Attribute which describes what the SP is or is not doing in this system
Structure which defines a system's SP functions.
Applicable for System target only. Structure is read-only.
fsiSlaveInit
0b0: SP does not initialize FSI slave logic, Hostboot must;
0b1: SP does initialize FSI slave logic so Hostboot should not
uint8_t
1
1
mailboxEnabled
0b0: There is no SP mailbox support;
0b1: There is SP mailbox support
uint8_t
1
0
fsiMasterInit
0b0: SP does not initialize FSI master logic, Hostboot must;
0b1: SP does initialize FSI master logic so Hostboot should not
uint8_t
1
1
reserved
Reserved for future use
uint8_t
5
0
non-volatile
TEST_NULL_STRING
Test attribute; string with empty default value
10
volatile
TEST_MIN_STRING
Test attribute; smallest string possible given size
a
10
volatile
TEST_MAX_STRING
Test attribute; largest string possible given size
abc
4
volatile
TEST_NO_DEFAULT_STRING
Test attribute; string with no default supplied
10
volatile
VPD_REC_NUM
Record offset for this target's VPD
0xFFFF
non-volatile
PEER_TARGET
Peer target's address of a A/X-bus connection.
NULL means address 0 for no peer target. If a
target instance overrides the default with the
peer target's PHYS_PATH. The target compiler will
convert the valid PHYS_PATH string into the runtime
virtual address of the peer target instance.
NULL
non-volatile
PAYLOAD_BASE
Base address (target HRMOR) of the payload. Value is in MB.
256
volatile
PAYLOAD_ENTRY
The offset from base address of the payload entry-point.
Current default is 0x180
0x180
volatile
EFF_DRAM_BANKS
Number of DRAM banks. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_BANKS
DIRECT
EFF_DRAM_ROWS
Number of DRAM rows. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_ROWS
DIRECT
EFF_DRAM_COLS
Number of DRAM columns. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_DRAM_COLS
DIRECT
EFF_DIMM_RCD_IBT
DIMM RCD IBT. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_EFF_DIMM_RCD_IBT
DIRECT
EFF_DIMM_RCD_MIRROR_MODE
DIMM RCD Mirror mode. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_EFF_DIMM_RCD_MIRROR_MODE
DIRECT
EFF_IBM_TYPE
Specifies the memory topology type. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_EFF_IBM_TYPE
DIRECT
EFF_NUM_DROPS_PER_PORT
Specifies the number of DIMM dimensions that are valid per port. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_EFF_NUM_DROPS_PER_PORT
DIRECT
EFF_STACK_TYPE
Specifies the DRAM package type. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_EFF_STACK_TYPE
DIRECT
EFF_NUM_MASTER_RANKS_PER_DIMM
Specifies the number of master ranks per DIMM. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM
DIRECT
EFF_NUM_PACKAGES_PER_RANK
Specifies the number of DRAM packages per rank. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_EFF_NUM_PACKAGES_PER_RANK
DIRECT
EFF_NUM_DIES_PER_PACKAGE
Specifies the number of DRAM dies per package. Initialized and used by HWPs.
0
2,2
volatile-zeroed
ATTR_EFF_NUM_DIES_PER_PACKAGE
DIRECT
MSS_SPARE_BYTE
This says that the system can have a 10th byte. Initialized and used by HWPs.
0
volatile-zeroed
ATTR_MSS_SPARE_BYTE
DIRECT
MSS_MEM_MC_IN_GROUP
A 8 bit vector that would be a designation of which MC are involved in the group. Initialized and used by HWPs.
0
8
volatile-zeroed
ATTR_MSS_MEM_MC_IN_GROUP
DIRECT
MSS_MCA_HASH_MODE
sets up the centaur hash mode policy. Mode values are 0, 1, and 2.
0
non-volatile
ATTR_MSS_MCA_HASH_MODE
DIRECT
MSS_MBA_ADDR_INTERLEAVE_BIT
sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. valid values are 23 through 32.
0
non-volatile
ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT
DIRECT
MSS_MBA_CACHELINE_INTERLEAVE_MODE
centaur interleave mode. 1 = 256-BIT, 0 = 128-BIT.
0
non-volatile
ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE
DIRECT
MSS_CACHE_ENABLE
Specifies if a Memory Buffer chip L4 cache is enabled or disabled
For good memory buffer chips, L4 is enabled
Firmware can set to disabled for a particular chip if the cache is
not functional
1 = enabled, 0 = disabled.
1
volatile
ATTR_MSS_CACHE_ENABLE
DIRECT
MSS_PREFETCH_ENABLE
Prefteching enable. 1 = enable, 0 = disable.
0
non-volatile
ATTR_MSS_PREFETCH_ENABLE
DIRECT
MSS_CLEANER_ENABLE
L4 cleaner enable. 1 = enable, 0 = disable.
0
non-volatile
ATTR_MSS_CLEANER_ENABLE
DIRECT
MSS_LAB_OVERRIDE_FOR_MEM_PLL
override the default Centaur MEM PLL settings with user-specified scan chain data. 1 = ON, 0 = OFF.
0
volatile-zeroed
ATTR_MSS_LAB_OVERRIDE_FOR_MEM_PLL
DIRECT
EI_BUS_RX_MSB_LSB_SWAP
PRBS scramble pattern per lane on DMI bus for p8 and centaur.
0
non-volatile
ATTR_EI_BUS_RX_MSB_LSB_SWAP
DIRECT
EI_BUS_TX_MSB_LSB_SWAP
PRBS scramble pattern per lane on DMI bus for p8 and centaur.
0
non-volatile
ATTR_EI_BUS_TX_MSB_LSB_SWAP
DIRECT
PROC_MEM_BASES
read/write HWP attribute mapped to TARGETING
Non-mirrored memory base addresses
creator: mss_setup_bars
consumer: proc_setup_bars, platform
firmware notes:
64-bit RA
eight independent non-mirrored segments are supported
(max number based on Venice design)
8
volatile-zeroed
ATTR_PROC_MEM_BASES
DIRECT
PROC_MEM_SIZES
read/write HWP attribute mapped to TARGETING
Size of non-mirrored memory regions
creator: mss_setup_bars
consumer: proc_setup_bars, platform
firmware notes:
for given index value, address space assumed to be contiguous
from ATTR_PROC_MEM_BASES value at matching index
eight independent non-mirrored segments are supported
(max number based on Venice design)
8
volatile-zeroed
ATTR_PROC_MEM_SIZES
DIRECT
PROC_MIRROR_BASES
Mirrored memory base addresses
creator: mss_setup_bars
consumer: proc_setup_bars, platform
firmware notes:
64-bit RA
four independent mirrored segments are supported
(max number based on Venice design)
4
volatile-zeroed
ATTR_PROC_MIRROR_BASES
DIRECT
PROC_MIRROR_SIZES
Size of mirrored memory region
creator: mss_setup_bars
consumer: proc_setup_bars, platform
firmware notes:
for given index value, address space assumed to be contiguous
from ATTR_PROC_MIRROR_BASES value at matching index
four independent mirrored segments are supported
(max number based on Venice design)
4
volatile-zeroed
ATTR_PROC_MIRROR_SIZES
DIRECT
PROC_L3_BAR1_REG
read/write HWP attribute mapped to TARGETING
L3 BAR1 register value
creator: proc_setup_bars
consumer: winkle image setup procedures
notes:
64-bit register value
SCOM address: 0x1001080B
volatile-zeroed
ATTR_PROC_L3_BAR1_REG
DIRECT
PROC_L3_BAR2_REG
read/write HWP attribute mapped to TARGETING
L3 BAR2 register value
creator: proc_setup_bars
consumer: winkle image setup procedures
notes:
64-bit register value
SCOM address: 0x10010813
volatile-zeroed
ATTR_PROC_L3_BAR2_REG
DIRECT
PROC_L3_BAR_GROUP_MASK_REG
read/write HWP attribute mapped to TARGETING
L3 BAR Group Mask register value
creator: proc_setup_bars
consumer: winkle image setup procedures
notes:
64-bit register value
SCOM address: 0x10010816
volatile-zeroed
ATTR_PROC_L3_BAR_GROUP_MASK_REG
DIRECT
FREQ_CORE
firmware notes:
Nominal processor's core DPLL frequency (MHz).
Default value provided by Machine Readable Workbook.
This attribute is the current value.
@note this should be initialized by istep 7.1 proc_a_x_pci_dmi_pll_setup
volatile-zeroed
ATTR_FREQ_CORE
DIRECT
PROC_PCIE_NOT_F_LINK
firmware notes:
Set IPL time mux/switch between PCIE PHB/F link function
(one per foreign link)
0,0
2
volatile
ATTR_PROC_PCIE_NOT_F_LINK
DIRECT
SLW_IMAGE_ADDR
Location of runtime winkle image for this processor chip.
Written by host_build_winkle (istep 15.1)
volatile-zeroed
SLW_IMAGE_SIZE
Size of runtime winkle image for this processor chip.
Written by host_build_winkle (istep 15.1)
volatile-zeroed
PROC_MCS_GROUPS
Per MCS group number
Value is index for PROC_MEM_BASES and PROC_MEM_SIZES arrays
creator: mss_eff_grouping.C
consumer: HDAT
0,0,0,0,0,0,0,0
8
volatile
ATTR_PROC_MCS_GROUPS
DIRECT
XSCOM_BASE_ADDRESS
System XSCOM base address
0x0003FC0000000000
non-volatile
IBSCOM_BASE_ADDR
System Inband Scom base address
0x0003E00000000000
non-volatile
MIRROR_BASE_ADDRESS
System Mirrorable base address
0x0002000000000000
non-volatile
FSP_BASE_ADDR
Base Address of FSP IO Region
0x0003FFE000000000
non-volatile
ATTR_PROC_FSP_BAR_BASE_ADDR
DIRECT
FSP_BAR_SIZE
Size of FSP IO Region
0x0000000100000000
non-volatile
ATTR_PROC_FSP_BAR_SIZE
DIRECT
FSP_MMIO_MASK_SIZE
MMIO Mask for FSP IO Region
0x0000000100000000
non-volatile
ATTR_PROC_FSP_MMIO_MASK_SIZE
DIRECT
PSI_BRIDGE_BASE_ADDR
Base Address of PSI Bridge Logic
0xFFFFFFFFFFFFFFFF
non-volatile
ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR
DIRECT
INTP_BASE_ADDR
Base Address of Interrupt Presenter
0xFFFFFFFFFFFFFFFF
non-volatile
ATTR_PROC_INTP_BAR_BASE_ADDR
DIRECT
PHB_BASE_ADDRS
Base Address of PHB Register Space
0xFFFFFFFFFFFFFFFF,
0xFFFFFFFFFFFFFFFF,
0xFFFFFFFFFFFFFFFF,
0xFFFFFFFFFFFFFFFF
4
non-volatile
PCI_BASE_ADDRS
Base Address of PCI Memory Space
0x0003D00000000000,
0x0003FFFE40100000,
0x0003FFFE40200000,
0x0003FFFE40300000
4
non-volatile
MEM_BASE
Base Address for all mainstore behind this processor
0xFFFFFFFFFFFFFFFF
non-volatile
ATTR_PROC_MEM_BASE
DIRECT
MIRROR_BASE
Base Address for all mirrored mainstore behind this processor
0xFFFFFFFFFFFFFFFF
non-volatile
ATTR_PROC_MIRROR_BASE
DIRECT
RNG_BASE_ADDR
Base Address of RNG IO Region
0xFFFFFFFFFFFFFFFF
non-volatile
ATTR_PROC_NX_MMIO_BAR_BASE_ADDR
DIRECT
RNG_BAR_SIZE
Size of RNG IO Region
0x000000000001000
non-volatile
IMT_BASE_ADDR
Base Address of In-Memory Trace Region
Set by FSP-based tooling
0xFFFFFFFFFFFFFFFF
non-volatile
IMT_BAR_SIZE
Size of IMT IO Region
Set by FSP-based tooling
0x0000000000000000
non-volatile
MSS_MCS_GROUP
Data Structure from eff grouping to setup bars to help determine different groups
Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
// Mirroring [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
Measured in GB
0
16,16
volatile-zeroed
ATTR_MSS_MCS_GROUP
DIRECT
MSS_MCS_GROUP_32
Data Structure from eff grouping to setup bars to help determine different groups
Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
// Mirroring [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
Measured in GB
0
16,16
volatile-zeroed
ATTR_MSS_MCS_GROUP_32
DIRECT
MSS_EFF_DIMM_FUNCTIONAL_VECTOR
A bit vector (per Dean's request) specifying if a DIMM is functional. DIMM attributes, such as SIZE, are qualified by this bit vector. The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional. 0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional. A fully populated system would have the value of 0xCC. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none
This factors in functionality
0
volatile-zeroed
ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR
DIRECT
MSS_INTERLEAVE_ENABLE
Used in the setting of groups. It is a bit vector. If the value BITWISE_AND 1 = 1 then groups of 1 are enabled with special checkerboard modes needed, if the value BITWISE_AND 2 = 2, then groups of 2 are possible; if value BITWISE_AND 4, the groups of 4 are possible; if value BITWISE_AND 8, the groups of 8 are possible. If no groups can formed according to this input, then an error will be thrown.
0
non-volatile
ATTR_MSS_INTERLEAVE_ENABLE
DIRECT
EFF_CKE_MAP
Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_cke consumer: various firmware notes: none
0
2,2,4
volatile-zeroed
ATTR_EFF_CKE_MAP
DIRECT
EFF_DIMM_SPARE
Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg consumer: various firmware notes: load from spd
0
2,2,4
volatile-zeroed
ATTR_EFF_DIMM_SPARE
DIRECT
EFF_SCHMOO_WR_EYE_MIN_MARGIN
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
0
volatile-zeroed
ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN
DIRECT
EFF_SCHMOO_RD_EYE_MIN_MARGIN
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
0
volatile-zeroed
ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN
DIRECT
EFF_SCHMOO_DQS_CLK_MIN_MARGIN
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
0
volatile-zeroed
ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN
DIRECT
EFF_SCHMOO_RD_GATE_MIN_MARGIN
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
0
volatile-zeroed
ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN
DIRECT
EFF_SCHMOO_ADDR_CMD_MIN_MARGIN
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
0
volatile-zeroed
ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN
DIRECT
MSS_CAL_STEP_ENABLE
A bit vector denoting valid cal steps to run during dram_init_train. [0] EXT_ZQCAL
[1] WR_LEVEL
[2] DQS_ALIGN
[3] RDCLK_ALIGN
[4] READ_CTR
[5] WRITE_CTR
[6] COARSE_WR
[7] COARSE_RD
bits6:7 will be consumed together to form COARSE_LVL.
0
volatile-zeroed
ATTR_MSS_CAL_STEP_ENABLE
DIRECT
MSS_MEM_IPL_COMPLETE
A numerical number indicating if the memory procedures are complete. written by mss_setup_bars when the bars are now functional in the processor.
0
volatile-zeroed
ATTR_MSS_MEM_IPL_COMPLETE
DIRECT
NOMINAL_FREQ_MHZ
Nominal frequency in mhz for all processors in the system based on module VPD processing.
0
non-volatile
ATTR_MNFG_FLAGS
Provides the mnfg flags
in a single value. The bits are
masked together so the single value
will have data on several mnfg flags.
Should note that the MNFG_FLAG_BIT enum
is used to provide the value of the
different mnfg flags. A user can bitwise
'OR' several of the MNFG_FLAG_BIT values
together to indicate that multiple mnfg
flags are set.
@TODO via RTC: 35451
The HostBoot side can only read the mnfg
flag attribute. However the FSP side will
need to read and write the mnfg flag
attributes. For now making it so both sides
are read and writeable but will need to revisit
to find a better way to handle persistency when
the hostboot and FSP differ.
0x0000000000000000
non-volatile
MNFG_FLAG_BIT
Enumeration indicating the mnfg flags
that are set by the user. The values can be
combined using a bitwise 'OR'. The values will
need to be kept in sync with the FAPI
enumerator values. Also the enumeration type
is used by the ATTR_MNFG_FLAGS attribute. Should
note that the MNFG_FLAG_BIT values are of type uint32_t
MNFG_THRESHOLDS
0x00000001
MNFG_AVP_ENABLE
0x00000002
MNFG_HDAT_AVP_ENABLE
0x00000004
MNFG_SRC_TERM
0x00000008
MNFG_IPL_MEMORY_CE_CHECKINGE
0x00000010
MNFG_FAST_BACKGROUND_SCRUB
0x00000020
MNFG_TEST_DRAM_REPAIRS
0x00000040
MNFG_DISABLE_DRAM_REPAIRS
0x00000080
MNFG_ENABLE_EXHAUSTIVE_PATTERN_TEST
0x00000100
MNFG_ENABLE_STANDARD_PATTERN_TEST
0x00000200
MNFG_ENABLE_MINIMUM_PATTERN_TEST
0x00000400