CLASS
Enumeration indicating the target's class
NA
0
CARD
1
ENC
2
CHIP
3
UNIT
4
DEV
5
SYS
6
LOGICAL_CARD
7
MAX
8
NA
TYPE
Enumeration indicating the target's type
NA
0
SYS
1
NODE
2
DIMM
3
MEMBUF
4
PROC
5
EX
6
CORE
7
L2
8
L3
9
L4
10
MCS
11
MBA
13
XBUS
14
ABUS
15
PCI
16
DPSS
17
APSS
18
OCC
19
PSI
20
FSP
21
PNOR
22
OSC
23
TODCLK
24
CONTROL_NODE
25
OSCREFCLK
26
OSCPCICLK
27
REFCLKENDPT
28
PCICLKENDPT
29
TEST_FAIL
30
LAST_IN_RANGE
31
NA
MODEL
Enumeration indicating the target's model
NA
0
RESERVED
16
VENICE
MURANO
CENTAUR
48
JEDEC
80
CDIMM
POWER8
112
NA
ENGINE_TYPE
Enumeration indicating the target's engine type
NA
0
ENGINE_IIC
1
ENGINE_SCOM
2
NA
FSI_MASTER_TYPE
Enumeration indicating the master's FSI type
MFSI
0
CMFSI
1
NO_MASTER
2
NO_MASTER
CLASS
Attribute indicating the target's class
CLASS
non-volatile
TYPE
Attribute indicating the target's type
TYPE
non-volatile
MODEL
Attribute indicating the target's model
MODEL
non-volatile
ENGINE_TYPE
Attribute indicating the target's engine type
ENGINE_TYPE
non-volatile
SCRATCH_UINT8_1
Scratch attribute that can be used for dev/test
volatile-zeroed
ATTR_SCRATCH_UINT8_1
DIRECT
SCRATCH_UINT8_2
Scratch attribute that can be used for dev/test
volatile-zeroed
ATTR_SCRATCH_UINT8_2
DIRECT
SCRATCH_UINT32_1
Scratch attribute that can be used for dev/test
volatile-zeroed
ATTR_SCRATCH_UINT32_1
DIRECT
SCRATCH_UINT32_2
Scratch attribute that can be used for dev/test
volatile-zeroed
ATTR_SCRATCH_UINT32_2
DIRECT
SCRATCH_UINT64_1
Scratch attribute that can be used for dev/test
volatile-zeroed
ATTR_SCRATCH_UINT64_1
DIRECT
SCRATCH_UINT64_2
Scratch attribute that can be used for dev/test
volatile-zeroed
ATTR_SCRATCH_UINT64_2
DIRECT
SCRATCH_UINT8_ARRAY_1
Scratch attribute that can be used for dev/test
32
volatile-zeroed
ATTR_SCRATCH_UINT8_ARRAY_1
DIRECT
SCRATCH_UINT8_ARRAY_2
Scratch attribute that can be used for dev/test
2, 3, 4
volatile-zeroed
ATTR_SCRATCH_UINT8_ARRAY_2
DIRECT
SCRATCH_UINT32_ARRAY_1
Scratch attribute that can be used for dev/test
8
volatile-zeroed
ATTR_SCRATCH_UINT32_ARRAY_1
DIRECT
SCRATCH_UINT32_ARRAY_2
Scratch attribute that can be used for dev/test
2,3
volatile-zeroed
ATTR_SCRATCH_UINT32_ARRAY_2
DIRECT
SCRATCH_UINT64_ARRAY_1
Scratch attribute that can be used for dev/test
4
volatile-zeroed
ATTR_SCRATCH_UINT64_ARRAY_1
DIRECT
SCRATCH_UINT64_ARRAY_2
Scratch attribute that can be used for dev/test
2,2
volatile-zeroed
ATTR_SCRATCH_UINT64_ARRAY_2
DIRECT
DUMMY_RW
Dummy attribute with read/write permissions
5
1,3,5
non-volatile
ATTR_DUMMY_SCRATCH_PLAT_INIT_UINT8
DIRECT
DUMMY_WO
Dummy attribute with write-only permissions
0
non-volatile
DUMMY_RO
Dummy attribute with read-only permissions
0
non-volatile
DUMMY_HEAP_ZERO_DEFAULT
Dummy attribute on the heap with zero initialization
volatile-zeroed
PHYS_PATH
Physical hierarchical path to the target
EntityPath
non-volatile
AFFINITY_PATH
Hierarchical path to the target with respect to logical affinity
EntityPath
non-volatile
POWER_PATH
Hierarchical path to the target with respect to power
EntityPath
non-volatile
PRIMARY_CAPABILITIES
Attribute which describes capabilities of a target
Structure which defines a target's primary capabilities.
A target can only support at most FSI SCOM and one of the other two SCOM
types. Applicable for all targets. Structure is read-only.
supportsFsiScom
0b0: Target does not support FSI SCOM;
0b1: Target supports FSI SCOM
uint8_t
1
0
supportsXscom
0b0: Target does not support XSCOM;
0b1: Target supports FSI XSCOM
uint8_t
1
0
supportsInbandScom
0b0: Target does not support inband SCOM
uint8_t
1
0
reserved
Reserved for future use
uint8_t
5
0
non-volatile
SCOM_SWITCHES
Attribute storing information about which SCOM path to use
Structure which defines which SCOM to use at a point in
time. Only applicable if target supports one or more SCOM types. Only
one bit (of the first three) can ever be set at any one time.
useFsiScom
0b0: Do not use FSI SCOM at this time. 0b1: Use FSI
SCOM at this time
uint8_t
1
0
useXscom
0b0: Do not use XSCOM at this time. 0b1: Use XSCOM at
this time
uint8_t
1
0
useInbandScom
0b0: Do not use inband SCOM at this time. 0b1: Use
inband SCOM at this time
uint8_t
1
0
reserved
Reserved for future expansion
uint8_t
5
0
volatile
FSI_MASTER_CHIP
Chip which contains the FSI master logic that drives this slave
EntityPath
non-volatile
FSI_MASTER_TYPE
Type of Master FSI connection to this slave (MFSI or cMFSI)
FSI_MASTER_TYPE
non-volatile
FSI_MASTER_PORT
Which port is this chip hanging off of
0
non-volatile
FSI_SLAVE_CASCADE
Slave cascade position
0
non-volatile
FSI_OPTION_FLAGS
Reserved for any special flags we might need to access FSI
0
non-volatile
EXECUTION_PLATFORM
Which execution platform the HW Procedure is running on
Some HWPs (e.g. special wakeup) use different registers for different
platforms to avoid arbitration problems when multiple platforms do
the same thing concurrently
HOST = 0x01, FSP = 0x02, OCC = 0x03
non-volatile
ATTR_EXECUTION_PLATFORM
DIRECT
IS_SIMULATION
env: 1 = Awan/HWSimulator. 0 = Simics/RealHW.
0
non-volatile
ATTR_IS_SIMULATION
DIRECT
HWAS_STATE
HardWare Availability Service State Attribute.
Keeps track of Target values poweredOn, present, functional
struct - 4 booleans and a PLID
deconfiguredByEid
if this target was deconfigured,
this will be a special DECONFIGURED_BY_ enum,
OR it will be the errlog EID that caused it,
either directly or by association,
uint32_t
0
poweredOn
0b0: Target is not powered on (is off);
0b1: Target is powered on;
uint8_t
1
0
present
0b0: Target is not present in the system;
0b1: Target is present in the system
uint8_t
1
0
functional
0b0: Target is not functional;
0b1: Target is functional
uint8_t
1
0
dumpfunctional
FSP Only, used by DUMP applet;
0b0: target is dump capabile;
0b1: target is not dump capabile;
uint8_t
1
0
volatile
HWAS_STATE_CHANGED_FLAG
HardWare Availability Service State Changed Attribute.
Keeps track of changedSinceChecked state, indicates if the
target has changed since last checked by the appropriate service.
This is a bit field of flags (see HWAS_CHANGED_BIT enumeration
that follows).
0x0
non-volatile
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
HardWare Availability Service State Changed Mask.
Used when a target changes (ie, via HCDB change) to set the
HWAS_STATE_CHANGED_FLAG, so that the appropriate services will
all handle the change.
This is a bit field of flags (see HWAS_CHANGED_BIT enumeration
that follows).
0x0
non-volatile
HWAS_CHANGED_BIT
Enumeration indicating the services that are concerned
with target changes (ie, via HCDB change).
The values can be combined using a bitwise 'OR'.
GARD
0x00000001
MEMDIAG
0x00000002
PSIDIAG
0x00000004
DIAG_MASK
0x00000006
NUMERIC_POD_TYPE_TEST
Attribute which tests numeric POD types
Numeric POD type test structure
fsiPath
Entity path for testing purposes
EntityPath
physical:sys-0
className
Class for testing purposes
CLASS
CHIP
uint8
Test uint8
uint8_t
0xAB
uint16
Test uint16
uint16_t
0xABCD
uint32
Test uint32
uint32_t
0xABCDEF01
uint64
Test uint64
uint64_t
0xABCDEF0123456789
int8
Test int8
int8_t
-124
int16
Test int16
int16_t
-32764
int32
Test int32
int32_t
-2147483644
int64
Test int64
int64_t
-9223372036854775804
non-volatile
DECONFIG_GARDABLE
If the Target is directly deconfigurable and GARDable; target
may still be deconfigured in 'by association' processing.
0
non-volatile
ISTEP_MODE
If True, puts HostBoot into SPLess SingleStep mode.
0
non-volatile
EEPROM_VPD_PRIMARY_INFO
Information needed to address the EEPROM slaves
Structure to define the addressing for an I2C
slave device.
i2cMasterPath
Entity path to the chip that contains the I2C
master
EntityPath
physical:sys-0
port
Port from the I2C Master device. This is a 6-bit
value.
uint8_t
0x80
devAddr
Device address on the I2C bus. This is a 7-bit value,
but then shifted 1 bit left.
uint8_t
0x80
engine
I2C master engine. This is a 2-bit
value.
uint8_t
0x80
non-volatile
EEPROM_VPD_BACKUP_INFO
Information needed to address the EERPROM slaves
Structure to define the addressing for an I2C
slave device.
i2cMasterPath
Entity path to the chip that contains the I2C
master
EntityPath
physical:sys-0
port
Port from the I2C Master device. This is a 6-bit
value.
uint8_t
0x80
devAddr
Device address on the I2C bus. This is a 7-bit value,
but then shifted 1 bit left.
uint8_t
0x80
engine
I2C master engine. This is a 2-bit
value.
uint8_t
0x80
non-volatile
EEPROM_SBE_PRIMARY_INFO
Information needed to address the EERPROM slaves
Structure to define the addressing for an I2C
slave device.
i2cMasterPath
Entity path to the chip that contains the I2C
master
EntityPath
physical:sys-0
port
Port from the I2C Master device. This is a 6-bit
value.
uint8_t
0x80
devAddr
Device address on the I2C bus. This is a 7-bit value,
but then shifted 1 bit left.
uint8_t
0x80
engine
I2C master engine. This is a 2-bit
value.
uint8_t
0x80
non-volatile
EEPROM_SBE_BACKUP_INFO
Information needed to address the EERPROM slaves
Structure to define the addressing for an I2C
slave device.
i2cMasterPath
Entity path to the chip that contains the I2C
master
EntityPath
physical:sys-0
port
Port from the I2C Master device. This is a 6-bit
value.
uint8_t
0x80
devAddr
Device address on the I2C bus. This is a 7-bit value,
but then shifted 1 bit left.
uint8_t
0x80
engine
I2C master engine. This is a 2-bit
value.
uint8_t
0x80
non-volatile
EC
attribute indicating the chip target's EC level
volatile-zeroed
ATTR_EC
DIRECT
CHIP_ID
attribute indicating the chip's ID
volatile-zeroed
ATTR_CHIP_ID
DIRECT
FSI_GP_REG_SCOM_ACCESS
attribute indicating if the chip's FSI GP regs have scom access
non-volatile
ATTR_FSI_GP_REG_SCOM_ACCESS
DIRECT
L2_R_T0_EPS
L2 tier0 read epsilon register value.
volatile-zeroed
ATTR_L2_R_T0_EPS
DIRECT
L2_R_T1_EPS
L2 tier1 read epsilon register value.
volatile-zeroed
ATTR_L2_R_T1_EPS
DIRECT
L2_R_T2_EPS
L2 tier2 read epsilon register value.
volatile-zeroed
ATTR_L2_R_T2_EPS
DIRECT
L2_FORCE_R_T2_EPS
L2 force tier2 read epsilon protect (all tiers).
volatile-zeroed
ATTR_L2_FORCE_R_T2_EPS
DIRECT
L2_W_EPS
L2 write epsilon register value.
volatile-zeroed
ATTR_L2_W_EPS
DIRECT
L3_R_T0_EPS
L3 tier0 read epsilon register value.
volatile-zeroed
ATTR_L3_R_T0_EPS
DIRECT
L3_R_T1_EPS
L3 tier1 read epsilon register value.
volatile-zeroed
ATTR_L3_R_T1_EPS
DIRECT
L3_R_T2_EPS
L3 tier2 read epsilon register value.
volatile-zeroed
ATTR_L3_R_T2_EPS
DIRECT
L3_FORCE_R_T2_EPS
L3 force tier2 read epsilon protect (all tiers).
volatile-zeroed
ATTR_L3_FORCE_R_T2_EPS
DIRECT
L3_W_EPS
L3 write epsilon register value.
volatile-zeroed
ATTR_L3_W_EPS
DIRECT
CHIP_UNIT
A unit (chiplet) 's offset number within the chip.
0
non-volatile
ATTR_CHIP_UNIT_POS
DIRECT
POSITION
Position of target relative to node
0
non-volatile
MBA_PORT
MBA port this DIMM is connected to
0
non-volatile
ATTR_MBA_PORT
DIRECT
MBA_DIMM
MBA port DIMM number of this DIMM
0
non-volatile
ATTR_MBA_DIMM
DIRECT
CEN_DQ_TO_DIMM_CONN_DQ
Centaur DQ to DIMM connector DQ mapping for a JEDEC DIMM.
Uint8 value for each Centaur DQ (0-79).
The value is the corresponding DIMM Connector DQ.
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,
20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,
60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79
80
non-volatile
PROC_EPS_TABLE_TYPE
Enumeration indicating the PROC_EPS_TABLE_TYPE
EPS_TYPE_LE
1
EPS_TYPE_HE
2
PROC_EPS_TABLE_TYPE
System attribute.
Processor epsilon table type. Used to calculate the processor nest
epsilon register values.
non-volatile
ATTR_PROC_EPS_TABLE_TYPE
DIRECT
PROC_FABRIC_PUMP_MODE
Enumeration indicating the PROC_FABRIC_PUMP_MODE
MODE1
1
MODE2
2
PROC_FABRIC_PUMP_MODE
System attribute.
Processor SMP Fabric broadcast scope configuration.
MODE1 = default = chip/group/system/remote group/foreign.
MODE2 = group/system/remote group/foreign.
Provided by the Machine Readable Workbook.
non-volatile
ATTR_PROC_FABRIC_PUMP_MODE
DIRECT
PROC_X_BUS_WIDTH
Enumeration indicating the PROC_X_BUS_WIDTH
W4BYTE
1
W8BYTE
2
PROC_X_BUS_WIDTH
System attribute.
Processor SMP X bus width.
Provided by the Machine Readable Workbook.
non-volatile
ATTR_PROC_X_BUS_WIDTH
DIRECT
ALL_MCS_IN_INTERLEAVING_GROUP
System attribute.
If all MCS chiplets are in an interleaving group (1=true, 0=false).
If true the SMP fabric is setup in normal mode.
If false the SMP fabric is setup in checkerboard mode.
Provided by the Machine Readable Workbook.
non-volatile
ATTR_ALL_MCS_IN_INTERLEAVING_GROUP
DIRECT
FABRIC_NODE_ID
Chip attribute.
Logical fabric node the chip belongs to.
Provided by the Machine Readable Workbook.
Can vary across drawers.
non-volatile
ATTR_FABRIC_NODE_ID
DIRECT
FABRIC_CHIP_ID
Chip attribute.
Logical fabric chip id for this chip (position within the fabric).
Provided by the Machine Readable Workbook.
Can vary across drawers.
non-volatile
ATTR_FABRIC_CHIP_ID
DIRECT
CHIP_HAS_SBE
Chip attribute.
If true, the chip has an SBE and the associated registers.
Provided by the Machine Readable Workbook.
non-volatile
ATTR_CHIP_HAS_SBE
DIRECT
FREQ_PROC_REFCLOCK
System attribute.
The frequency of the processor refclock in MHz.
Provided by the MRW.
non-volatile
ATTR_FREQ_PROC_REFCLOCK
DIRECT
FREQ_PROC_REFCLOCK_KHZ
System attribute.
The frequency of the processor refclock in KHz.
Provided by the MRW.
non-volatile
ATTR_FREQ_PROC_REFCLOCK_KHZ
DIRECT
FREQ_MEM_REFCLOCK
System attribute.
The frequency of the memory refclock in MHz.
Provided by the MRW.
non-volatile
ATTR_FREQ_MEM_REFCLOCK
DIRECT
FREQ_CORE_FLOOR
System attribute.
The lowest frequency that a core can be set to in MHz.
This is the same for all cores in the system.
Provided by the MRW.
non-volatile
ATTR_FREQ_CORE_FLOOR
DIRECT
FREQ_PB
System attribute.
The frequency of a processor's PB chiplet in MHz.
This is the same for all PB chiplets in the system.
Provided by the MRW.
non-volatile
ATTR_FREQ_PB
DIRECT
FREQ_A
System attribute.
The frequency of a processor's A-bus chiplet in MHz.
This is the same for all A-bus chiplets in the system.
Provided by the MRW.
non-volatile
ATTR_FREQ_A
DIRECT
FREQ_X
System attribute.
The frequency of a processor's X-bus chiplet in MHz.
This is the same for all X-bus chiplets in the system.
Provided by the MRW.
non-volatile
ATTR_FREQ_X
DIRECT
MVPD_FREQ_CORE_NOMINAL
Chip attribute.
The nominal frequency of the processor cores in MHz.
TODO This attribute should be from MVPD.
When MVPD function is present, this attribute should be deleted.
The corresponding HWPF attribute request should map to a function
that calls the MVPD driver (in the same way as DIMM SPD).
For now, just default to 3GHz
3000
non-volatile
ATTR_MVPD_FREQ_CORE_NOMINAL
DIRECT
HUID
Hardware Unit ID
SSSSNNNNTTTTTTTTiiiiiiiiiiiiiiii
S=System
N=Node Number
T=Target Type (matches TYPE attribute)
i=Instance/Sequence number of target, relative to node
0xFFFFFFFF
non-volatile
SP_FUNCTIONS
Attribute which describes what the SP is or is not doing in this system
Structure which defines a system's SP functions.
Applicable for System target only. Structure is read-only.
fsiSlaveInit
0b0: SP does not initialize FSI slave logic, Hostboot must;
0b1: SP does initialize FSI slave logic so Hostboot should not
uint8_t
1
1
mailboxEnabled
0b0: There is no SP mailbox support;
0b1: There is SP mailbox support
uint8_t
1
0
fsiMasterInit
0b0: SP does not initialize FSI master logic, Hostboot must;
0b1: SP does initialize FSI master logic so Hostboot should not
uint8_t
1
1
hardwareChangeDetection
0b0: SP does not perform hardware change detection, Hostboot must;
0b1: SP does perform hardware change detection (HCDB) so Hostboot should not
uint8_t
1
1
powerLineDisturbance
0b0: SP does not perform Power Line Disturbance (PLD) detection, Hostboot must;
0b1: SP does perform Power Line Disturbance (PLD) detection so Hostboot should not
uint8_t
1
1
reserved
Reserved for future use
uint8_t
3
0
non-volatile
HB_SETTINGS
Attribute which describes how the SP has configured features in
Hostboot.
Structure which defines a system's HB settings.
Applicable for System target only.
traceContinuous
Enable / Disable continuous trace.
0b0: Continuous trace is disabled.
0b1: Continuous trace is enabled.
uint8_t
1
0
traceScanDebug
Override trace debug selection for SCAN component.
0b0: TRACS entries for SCAN have default behavior.
0b1: TRACS entries for SCAN are enabled.
uint8_t
1
0
reserved
Reserved for future use
uint8_t
6
0
non-volatile
TEST_NULL_STRING
Test attribute; string with empty default value
10
volatile
TEST_MIN_STRING
Test attribute; smallest string possible given size
a
10
volatile
TEST_MAX_STRING
Test attribute; largest string possible given size
abc
4
volatile
TEST_NO_DEFAULT_STRING
Test attribute; string with no default supplied
10
volatile
VPD_REC_NUM
Record offset for this target's VPD
0xFFFF
non-volatile
PEER_TARGET
Peer target's address of a A/X-bus connection.
NULL means address 0 for no peer target. If a
target instance overrides the default with the
peer target's PHYS_PATH. The target compiler will
convert the valid PHYS_PATH string into the runtime
virtual address of the peer target instance.
NULL
non-volatile
PAYLOAD_BASE
Base address (target HRMOR) of the payload. Value is in MB.
256
volatile
PAYLOAD_ENTRY
The offset from base address of the payload entry-point.
Current default is 0x180
0x180
volatile
PAYLOAD_KIND
Enumeration indicating what kind of payload is to be started
UNKNOWN
0
PHYP
1
SAPPHIRE
2
NONE
3
UNKNOWN
PAYLOAD_KIND
Attribute indicating what kind of payload is to be started.
PAYLOAD_KIND
non-volatile
HB_HRMOR_NODAL_BASE
Hostboot HRMOR = (HB_HRMOR_NODAL_BASE * node) + offset.
0x400000000000
volatile
FABRIC_TO_PHYSICAL_NODE_MAP
Correlate HDAT node number (physical) to the logical node
(based on the PIR) that contains the host boot image.
0,255,255,255,255,255,255,255
8
volatile
PROC_MEM_BASES
read/write HWP attribute mapped to TARGETING
Non-mirrored memory base addresses
creator: mss_setup_bars
consumer: proc_setup_bars, platform
firmware notes:
64-bit RA
eight independent non-mirrored segments are supported
(max number based on Venice design)
8
volatile-zeroed
ATTR_PROC_MEM_BASES
DIRECT
PROC_MEM_SIZES
read/write HWP attribute mapped to TARGETING
Size of non-mirrored memory regions
creator: mss_setup_bars
consumer: proc_setup_bars, platform
firmware notes:
for given index value, address space assumed to be contiguous
from ATTR_PROC_MEM_BASES value at matching index
eight independent non-mirrored segments are supported
(max number based on Venice design)
8
volatile-zeroed
ATTR_PROC_MEM_SIZES
DIRECT
PROC_MIRROR_BASES
Mirrored memory base addresses
creator: mss_setup_bars
consumer: proc_setup_bars, platform
firmware notes:
64-bit RA
four independent mirrored segments are supported
(max number based on Venice design)
4
volatile-zeroed
ATTR_PROC_MIRROR_BASES
DIRECT
PROC_MIRROR_SIZES
Size of mirrored memory region
creator: mss_setup_bars
consumer: proc_setup_bars, platform
firmware notes:
for given index value, address space assumed to be contiguous
from ATTR_PROC_MIRROR_BASES value at matching index
four independent mirrored segments are supported
(max number based on Venice design)
4
volatile-zeroed
ATTR_PROC_MIRROR_SIZES
DIRECT
PROC_L3_BAR1_REG
read/write HWP attribute mapped to TARGETING
L3 BAR1 register value
creator: proc_setup_bars
consumer: winkle image setup procedures
notes:
64-bit register value
SCOM address: 0x1001080B
volatile-zeroed
ATTR_PROC_L3_BAR1_REG
DIRECT
PROC_L3_BAR2_REG
read/write HWP attribute mapped to TARGETING
L3 BAR2 register value
creator: proc_setup_bars
consumer: winkle image setup procedures
notes:
64-bit register value
SCOM address: 0x10010813
volatile-zeroed
ATTR_PROC_L3_BAR2_REG
DIRECT
PROC_L3_BAR_GROUP_MASK_REG
read/write HWP attribute mapped to TARGETING
L3 BAR Group Mask register value
creator: proc_setup_bars
consumer: winkle image setup procedures
notes:
64-bit register value
SCOM address: 0x10010816
volatile-zeroed
ATTR_PROC_L3_BAR_GROUP_MASK_REG
DIRECT
FREQ_CORE
firmware notes:
Nominal processor's core DPLL frequency (MHz).
Default value provided by Machine Readable Workbook.
This attribute is the current value.
@note this should be initialized by istep 7.1 proc_a_x_pci_dmi_pll_setup
volatile-zeroed
ATTR_FREQ_CORE
DIRECT
PROC_PCIE_NOT_F_LINK
firmware notes:
Set IPL time mux/switch between PCIE PHB/F link function
(one per foreign link)
1,1
2
volatile
ATTR_PROC_PCIE_NOT_F_LINK
DIRECT
PROC_MCS_GROUPS
Per MCS group number
Value is index for PROC_MEM_BASES and PROC_MEM_SIZES arrays
creator: mss_eff_grouping.C
consumer: HDAT
0,0,0,0,0,0,0,0
8
volatile
ATTR_PROC_MCS_GROUPS
DIRECT
XSCOM_BASE_ADDRESS
System XSCOM base address
0x0003FC0000000000
non-volatile
IBSCOM_MCS_BASE_ADDR
MCS Inband Scom base address
0x0003E00000000000
non-volatile
ATTR_MCS_INBAND_BASE_ADDRESS
DIRECT
IBSCOM_PROC_BASE_ADDR
PROC Inband Scom base address
0x0003E00000000000
non-volatile
MIRROR_BASE_ADDRESS
System Mirrorable base address
0x0002000000000000
non-volatile
FSP_BASE_ADDR
Base Address of FSP IO Region
0x0003FFE000000000
non-volatile
ATTR_PROC_FSP_BAR_BASE_ADDR
DIRECT
FSP_BAR_SIZE
Size of FSP IO Region
0x0000000100000000
non-volatile
ATTR_PROC_FSP_BAR_SIZE
DIRECT
FSP_MMIO_MASK_SIZE
MMIO Mask for FSP IO Region
0x0000000100000000
non-volatile
ATTR_PROC_FSP_MMIO_MASK_SIZE
DIRECT
PSI_BRIDGE_BASE_ADDR
Base Address of PSI Bridge Logic
0xFFFFFFFFFFFFFFFF
non-volatile
ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR
DIRECT
INTP_BASE_ADDR
Base Address of Interrupt Presenter
0xFFFFFFFFFFFFFFFF
non-volatile
ATTR_PROC_INTP_BAR_BASE_ADDR
DIRECT
PHB_BASE_ADDRS
Base Address of PHB Register Space
0xFFFFFFFFFFFFFFFF,
0xFFFFFFFFFFFFFFFF,
0xFFFFFFFFFFFFFFFF,
0xFFFFFFFFFFFFFFFF
4
non-volatile
PCI_BASE_ADDRS
Base Address of PCI Memory Space
0x0003D00000000000,
0x0003FFFE40100000,
0x0003FFFE40200000,
0x0003FFFE40300000
4
non-volatile
MEM_BASE
Base Address for all mainstore behind this processor
volatile-zeroed
ATTR_PROC_MEM_BASE
DIRECT
MIRROR_BASE
Base Address for all mirrored mainstore behind this processor
volatile-zeroed
ATTR_PROC_MIRROR_BASE
DIRECT
RNG_BASE_ADDR
Base Address of RNG IO Region
0xFFFFFFFFFFFFFFFF
non-volatile
ATTR_PROC_NX_MMIO_BAR_BASE_ADDR
DIRECT
RNG_BAR_SIZE
Size of RNG IO Region
0x000000000001000
non-volatile
IMT_BASE_ADDR
Base Address of In-Memory Trace Region
Set by FSP-based tooling
0xFFFFFFFFFFFFFFFF
non-volatile
IMT_BAR_SIZE
Size of IMT IO Region
Set by FSP-based tooling
0x0000000000000000
non-volatile
PROC_EPS_GB_PERCENTAGE
firmware notes:
Guardband percentage to apply to baseline epsilon values
volatile-zeroed
ATTR_PROC_EPS_GB_PERCENTAGE
DIRECT
PROC_EPS_GB_DIRECTION
firmware notes:
Direction to apply guardband margin (positive/negative)
volatile-zeroed
ATTR_PROC_EPS_GB_DIRECTION
DIRECT
PROC_FABRIC_ASYNC_SAFE_MODE
firmware notes:
Set to force all asynchronous boundary crossings into safe mode.
volatile-zeroed
ATTR_PROC_FABRIC_ASYNC_SAFE_MODE
DIRECT
FREQ_PCIE
The frequency of a processor's PCI-e bus in MHz.
This is the same for all PCI-e busses in the system.
Provided by the MRW.
non-volatile
ATTR_FREQ_PCIE
DIRECT
NOMINAL_FREQ_MHZ
Nominal frequency in mhz for all processors in the system based on module VPD processing.
0
non-volatile
MNFG_FLAGS
Provides the mnfg flags
in a single value. The bits are
masked together so the single value
will have data on several mnfg flags.
Should note that the MNFG_FLAG_BIT enum
is used to provide the value of the
different mnfg flags. A user can bitwise
'OR' several of the MNFG_FLAG_BIT values
together to indicate that multiple mnfg
flags are set.
@TODO via RTC: 35451
The HostBoot side can only read the mnfg
flag attribute. However the FSP side will
need to read and write the mnfg flag
attributes. For now making it so both sides
are read and writeable but will need to revisit
to find a better way to handle persistency when
the hostboot and FSP differ.
0x0000000000000000
non-volatile
ATTR_MNFG_FLAGS
DIRECT
MNFG_FLAG_BIT
Enumeration indicating the mnfg flags
that are set by the user. The values can be
combined using a bitwise 'OR'. The values will
need to be kept in sync with the FAPI
enumerator values. Also the enumeration type
is used by the ATTR_MNFG_FLAGS attribute. Should
note that the MNFG_FLAG_BIT values are of type uint32_t
MNFG_THRESHOLDS
0x00000001
MNFG_AVP_ENABLE
0x00000002
MNFG_HDAT_AVP_ENABLE
0x00000004
MNFG_SRC_TERM
0x00000008
MNFG_IPL_MEMORY_CE_CHECKINGE
0x00000010
MNFG_FAST_BACKGROUND_SCRUB
0x00000020
MNFG_TEST_DRAM_REPAIRS
0x00000040
MNFG_DISABLE_DRAM_REPAIRS
0x00000080
MNFG_ENABLE_EXHAUSTIVE_PATTERN_TEST
0x00000100
MNFG_ENABLE_STANDARD_PATTERN_TEST
0x00000200
MNFG_ENABLE_MINIMUM_PATTERN_TEST
0x00000400
MNFG_DISABLE_FABRIC_eREPAIR
0x00000800
MNFG_DISABLE_MEMORY_eREPAIR
0x00001000
MNFG_FABRIC_DEPLOY_LANE_SPARES
0x00002000
MNFG_DMI_DEPLOY_LANE_SPARES
0x00004000
MNFG_PSI_DIAGNOSTIC
0x00008000
PROC_DPLL_DIVIDER
PROC_CHIP Attribute
volatile-zeroed
ATTR_PROC_DPLL_DIVIDER
DIRECT
PM_POWER_PROXY_TRACE_TIMER
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_POWER_PROXY_TRACE_TIMER
DIRECT
PM_PPT_TIMER_MATCH_VALUE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_PPT_TIMER_MATCH_VALUE
DIRECT
PM_PPT_TIMER_TICK
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_PPT_TIMER_TICK
DIRECT
PM_AISS_TIMEOUT
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_AISS_TIMEOUT
DIRECT
PM_PSTATE_STEPSIZE
PROC_CHIP Attribute
Used to setup the PMC voltage controller
Producer: proc_build_pstate_tables.C
Consumer: OCC pstate_init()
volatile-zeroed
ATTR_PM_PSTATE_STEPSIZE
DIRECT
PM_EXTERNAL_VRM_STEPDELAY_RANGE
PROC_CHIP Attribute
A 4 bit field selects one of the the upper 16bit of a 19bit counter (16+3) incremented in the nest/4 domain
Consumer: proc_pm.scominit
volatile-zeroed
ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE
DIRECT
PM_EXTERNAL_VRM_STEPDELAY_VALUE
PROC_CHIP Attribute
Consumer: proc_pm.scominit
volatile-zeroed
ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE
DIRECT
PM_PMC_HANGPULSE_DIVIDER
PROC_CHIP Attribute
Producer: proc_pm_init
Consumer: proc_pm.scominit
volatile-zeroed
ATTR_PM_PMC_HANGPULSE_DIVIDER
DIRECT
PM_PVSAFE_PSTATE
PROC_CHIP Attribute
Pstate that is invoked in the PMC voltage controller upon the loss of the OCC Heartbeat..
Producer: proc_pm_init.C
Consumer: proc_pm.scominit
volatile-zeroed
ATTR_PM_PVSAFE_PSTATE
DIRECT
PM_SPIVID_FRAME_SIZE
PROC_CHIP Attribute
Supported values: 0x20 (32d)
Chip Select assertion duration is spi_frame_size + 2
volatile-zeroed
ATTR_PM_SPIVID_FRAME_SIZE
DIRECT
PM_SPIVID_IN_DELAY_FRAME1
PROC_CHIP Attribute
Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured
volatile-zeroed
ATTR_PM_SPIVID_IN_DELAY_FRAME1
DIRECT
PM_SPIVID_IN_DELAY_FRAME2
PROC_CHIP Attribute
Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured
volatile-zeroed
ATTR_PM_SPIVID_IN_DELAY_FRAME2
DIRECT
PM_SPIVID_CLOCK_POLARITY
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_SPIVID_CLOCK_POLARITY
DIRECT
PM_SPIVID_CLOCK_PHASE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_SPIVID_CLOCK_PHASE
DIRECT
PM_SPIVID_CLOCK_DIVIDER
PROC_CHIP Attribute
For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjusted between 600MHz and 0.29MHz (cycle time 1.66ns...3.41us, in 1.66ns steps). However, a practical range is 0.5...25MHz.
volatile-zeroed
ATTR_PM_SPIVID_CLOCK_DIVIDER
DIRECT
PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS
PROC_CHIP Attribute
Consumer: proc_pmc_init
volatile-zeroed
ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS
DIRECT
PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE
PROC_CHIP Attribute
Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time
0x00000: Wait 1 SPI Clock
0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses
For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle.
volatile-zeroed
ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE
DIRECT
PM_SPIVID_INTER_RETRY_DELAY_VALUE
PROC_CHIP Attribute
Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time
0x0000: Wait 1 SPI Clock
0x0001 - 0xFFFF: value = number of ~100ns_hang_pulses
For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle.
volatile-zeroed
ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE
DIRECT
PM_SPIVID_INTER_RETRY_DELAY
PROC_CHIP Attribute
Consumer: proc_pmc_init
volatile-zeroed
ATTR_PM_SPIVID_INTER_RETRY_DELAY
DIRECT
PM_SPIVID_CRC_GEN_ENABLE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_SPIVID_CRC_GEN_ENABLE
DIRECT
PM_SPIVID_CRC_CHECK_ENABLE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_SPIVID_CRC_CHECK_ENABLE
DIRECT
PM_SPIVID_MAJORITY_VOTE_ENABLE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE
DIRECT
PM_SPIVID_MAX_RETRIES
PROC_CHIP Attribute
0x00: No retry
0x01 to 0x1F: 1 to 31 respectively
volatile-zeroed
ATTR_PM_SPIVID_MAX_RETRIES
DIRECT
PM_SPIVID_CRC_POLYNOMIAL_ENABLES
PROC_CHIP Attribute
An 8 bit mask vector to enable XORs in the CRC generation and checking LFSRs at the respective bit position. MSB (x^8) is omitted since it is always enabled, so the mask layout is (x^7,x^6,x^5,x^4,x^3,x^2,x^1,1)
Planned CRC8 polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1
Value to enable planned polynomial: 0b1101_0101 (=0xD5)
volatile-zeroed
ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES
DIRECT
PM_OCC_HEARTBEAT_TIME
PROC_CHIP Attribute
Consumer: OCC FW
volatile-zeroed
ATTR_PM_OCC_HEARTBEAT_TIME
DIRECT
PM_SLEEP_WINKLE_REQUEST_TIMEOUT
PROC_CHIP Attribute
Consumer: proc_pmc_init.C. Will be translated to a DYNAMIC ATTRIBUTE for use by proc_pm..scominit as a multiple of PM hang pulses.. Counter starts at 0, is increased with every tp_pmc_hang_pulse as long as PORE is busy and set the PMC local FIR bit 19 when count = threshold.
volatile-zeroed
ATTR_PM_SLEEP_WINKLE_REQUEST_TIMEOUT
DIRECT
PM_SLEEP_ENTRY
PROC_CHIP Attribute
Set Assisted if power off serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency
Producer: MRWB
Consumer: proc_pm_init and proc_pcbs_init
volatile-zeroed
ATTR_PM_SLEEP_ENTRY
DIRECT
PM_SLEEP_EXIT
PROC_CHIP Attribute
Set to Assisted if power on serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency
Must be set to Assisted if ATTR_PM_SLEEP_TYPE=Deep as this necessary for restore.
Setting to Hardware is a test mode for Fast only.
Producer: MRWB
Consumer: proc_pm_init and proc_pcbs_init.
volatile-zeroed
ATTR_PM_SLEEP_EXIT
DIRECT
PM_SLEEP_TYPE
PROC_CHIP Attribute
Selects which voltage level to place the Core domain PFETs upon Sleep entry. 0 = Vret (Fast Sleep Mode), 1 = Voff (Deep Sleep Mode)
Producer: MRWB
Consumer: proc_pm_init and proc_pcbs_init
volatile-zeroed
ATTR_PM_SLEEP_TYPE
DIRECT
PM_WINKLE_TYPE
PROC_CHIP Attribute
Selects which voltage level to place the Core and ECO domain PFETs upon Winkle entry. 0 = Vret (Fast Winkle Mode), 1 = Voff (Deep Winkle Mode)
volatile-zeroed
ATTR_PM_WINKLE_TYPE
DIRECT
PM_PFET_POWERUP_CORE_DELAY0
PROC_CHIP Attribute
0
non-volatile
ATTR_PM_PFET_POWERUP_CORE_DELAY0
DIRECT
PM_PFET_POWERUP_CORE_DELAY1
PROC_CHIP Attribute
0
non-volatile
ATTR_PM_PFET_POWERUP_CORE_DELAY1
DIRECT
PM_PFET_POWERUP_CORE_DELAY0_VALUE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE
DIRECT
PM_PFET_POWERUP_CORE_DELAY1_VALUE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE
DIRECT
PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT
PROC_CHIP Attribute
0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0;
1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1
volatile-zeroed
ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT
DIRECT
PM_PFET_POWERDOWN_CORE_DELAY0
PROC_CHIP Attribute
0
non-volatile
ATTR_PM_PFET_POWERDOWN_CORE_DELAY0
DIRECT
PM_PFET_POWERDOWN_CORE_DELAY1
PROC_CHIP Attribute
0
non-volatile
ATTR_PM_PFET_POWERDOWN_CORE_DELAY1
DIRECT
PM_PFET_POWERDOWN_CORE_DELAY0_VALUE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE
DIRECT
PM_PFET_POWERDOWN_CORE_DELAY1_VALUE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE
DIRECT
PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT
PROC_CHIP Attribute
0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0;
1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1
volatile-zeroed
ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT
DIRECT
PM_PFET_POWERUP_ECO_DELAY0
PROC_CHIP Attribute
0
non-volatile
ATTR_PM_PFET_POWERUP_ECO_DELAY0
DIRECT
PM_PFET_POWERUP_ECO_DELAY1
PROC_CHIP Attribute
0
non-volatile
ATTR_PM_PFET_POWERUP_ECO_DELAY1
DIRECT
PM_PFET_POWERUP_ECO_DELAY0_VALUE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE
DIRECT
PM_PFET_POWERUP_ECO_DELAY1_VALUE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE
DIRECT
PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT
PROC_CHIP Attribute
0 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY0;
1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1
volatile-zeroed
ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT
DIRECT
PM_PFET_POWERDOWN_ECO_DELAY0
PROC_CHIP Attribute
0
non-volatile
ATTR_PM_PFET_POWERDOWN_ECO_DELAY0
DIRECT
PM_PFET_POWERDOWN_ECO_DELAY1
PROC_CHIP Attribute
0
non-volatile
ATTR_PM_PFET_POWERDOWN_ECO_DELAY1
DIRECT
PM_PFET_POWERDOWN_ECO_DELAY0_VALUE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE
DIRECT
PM_PFET_POWERDOWN_ECO_DELAY1_VALUE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE
DIRECT
PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT
DIRECT
PM_PSTATE0_FREQUENCY
PROC_CHIP Attribute
Producer: proc_build_gpstate.C
Consumers: proc_pcbs_init.C, proc_pcbs_lpst_init.C,
volatile-zeroed
ATTR_PM_PSTATE0_FREQUENCY
DIRECT
PM_IVRMS_ENABLED
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_IVRMS_ENABLED
DIRECT
PM_SAFE_PSTATE
PROC_CHIP Attribute
Valid Values:-128 thru 127
Producer: proc_pm_init.C
DYNAMIC_ATTRIBUTE
Consumer: proc_pcbs_init.C
Establishes the Pstate that the core chiplet will take on if:
psafe less-than-or-equal PMSR[global_actual_pstate]
AND any of the following conditions are true:
Loss of OCC Heartbeat if occ_heartbeat_en is set
PMGP0[force_safe_mode] is set
If psafe greater-than PMSR[global_actual_pstate], the global_actual_pstate is forced.
The value of Psafe needs to be at or below the nominal Pstate to make sure safe operation of all chiplets.
volatile-zeroed
ATTR_PM_SAFE_PSTATE
DIRECT
PM_RESONANT_CLOCK_ENABLE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_RESONANT_CLOCK_ENABLE
DIRECT
PM_RESONANT_CLOCK_FULL_CSB_PSTATE
PROC_CHIP Attribute
Defines the Pstate for the point at which clock sector buffers should be at full strength. This is to support Vmin operation.
volatile-zeroed
ATTR_PM_RESONANT_CLOCK_FULL_CSB_PSTATE
DIRECT
PM_RESONANT_CLOCK_LFRLOW_PSTATE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE
DIRECT
PM_RESONANT_CLOCK_LFRUPPER_PSTATE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE
DIRECT
PM_RESONANT_CLOCK_HFRLOW_PSTATE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE
DIRECT
PM_RESONANT_CLOCK_HFRHIGH_PSTATE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE
DIRECT
PM_SPIPSS_FRAME_SIZE
PROC_CHIP Attribute
Supported values: 0x10 (16d),
Chip Select assertion duration is spi_frame_size + 2
volatile-zeroed
ATTR_PM_SPIPSS_FRAME_SIZE
DIRECT
PM_SPIPSS_OUT_COUNT
PROC_CHIP Attribute
Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size are ignored.
volatile-zeroed
ATTR_PM_SPIPSS_OUT_COUNT
DIRECT
PM_SPIPSS_IN_DELAY
PROC_CHIP Attribute
Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured
volatile-zeroed
ATTR_PM_SPIPSS_IN_DELAY
DIRECT
PM_SPIPSS_IN_COUNT
PROC_CHIP Attribute
Supported values: 0x000 to spi_frame_size. The actual number of bits captured is spi_frame_size - spi_in_delay
volatile-zeroed
ATTR_PM_SPIPSS_IN_COUNT
DIRECT
PM_SPIPSS_CLOCK_POLARITY
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_SPIPSS_CLOCK_POLARITY
DIRECT
PM_SPIPSS_CLOCK_PHASE
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_SPIPSS_CLOCK_PHASE
DIRECT
PM_SPIPSS_CLOCK_DIVIDER
PROC_CHIP Attribute
volatile-zeroed
ATTR_PM_SPIPSS_CLOCK_DIVIDER
DIRECT
PM_SPIPSS_INTER_FRAME_DELAY_SETTING
PROC_CHIP Attribute
Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time
0x00000: Wait 1 PSS Clock
0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses
For values greater than 0x00000, the actual delay is 1 PSS Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 PSSI clock cycle.
Producer: proc_pm_init
Consumer: proc_pss_init
volatile-zeroed
ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING
DIRECT
PM_SPIPSS_INTER_FRAME_DELAY
PROC_CHIP Attribute
Consumer: proc_pm_init
Produces ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING
volatile-zeroed
ATTR_PM_SPIPSS_INTER_FRAME_DELAY
DIRECT
PM_PBAX_RCV_RESERV_TIMEOUT
PROC_CHIP Attribute
Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received under the following conditions:
Data Hi packet accepted and timeout waiting for Data Lo packet.
Reservation aquired and timeout waiting for Data Hi packet.
00000 Data Timeout is Disabled
00001 divided hang pulse = PBAX hang pulse
00010 divided hang pulse = PBAX hang pulse/2
00011 divided hang pulse = PBAX hang pulse/3
. . .
11111 divided hang pulse = PBAX hang pulse/31
volatile-zeroed
ATTR_PM_PBAX_RCV_RESERV_TIMEOUT
DIRECT
PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE
PROC_CHIP Attribute
Mode bit to count overcommit retries for the send retry threshold when sending PBAX commands on the powerbus.
volatile-zeroed
ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE
DIRECT
PM_PBAX_SND_RETRY_THRESHOLD
PROC_CHIP Attribute
Defines the maximum number of retry attempts by the Send Engine for any phase of the PBAX transaction set before the operation is dropped and status bit are set. This does not count PowerBus overcommit retries unless snd_retry_count_overcom bit is set.
0x00 : No Timeout
0x01 : 1 attempt
0x02 : 2 attempts
.etc.
0xFF : 255 attempts
volatile-zeroed
ATTR_PM_PBAX_SND_RETRY_THRESHOLD
DIRECT
PM_PBAX_SND_RESERV_TIMEOUT
PROC_CHIP Attribute
Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received after attempting to acquire a reservation with the PBAX Receive engine before declaring a Send Reservation Timeout error.
00000 Send Reservation Timeout is Disabled
00001 divided hang pulse = PBAX hang pulse
00010 divided hang pulse = PBAX hang pulse/2
00011 divided hang pulse = PBAX hang pulse/3
. . .
11111 divided hang pulse = PBAX hang pulse/31
volatile-zeroed
ATTR_PM_PBAX_SND_RESERV_TIMEOUT
DIRECT
PM_SPWUP_FSP
EX_CHIPLET Attribute
volatile-zeroed
ATTR_PM_SPWUP_FSP
DIRECT
PM_SPWUP_OCC
EX_CHIPLET Attribute
volatile-zeroed
ATTR_PM_SPWUP_OCC
DIRECT
PM_SPWUP_PHYP
EX_CHIPLET Attribute
volatile-zeroed
ATTR_PM_SPWUP_PHYP
DIRECT
PM_EXTERNAL_VRM_STEPSIZE
SYSTEM Attribute
Step size (binary in microvolts) to take upon external VRM voltage
transitions. The value set here must take into account where internal
VRMs are enabled or not as, when they are enabled, the step size must
account for the tracking (eg PFET strength recalculation) for the step.
Consumer: proc_build_pstate_tables.C, proc_pmc_init.C -config
Provided by the Machine Readable Workbook after system characterization.
non-volatile
ATTR_PM_EXTERNAL_VRM_STEPSIZE
DIRECT
PM_EXTERNAL_VRM_STEPDELAY
SYSTEM Attribute
Step delay (binary in microseconds) after a voltage change
Consumer: proc_pmc_init -config
Provided by the Machine Readable Workbook after system characterization.
non-volatile
ATTR_PM_EXTERNAL_VRM_STEPDELAY
DIRECT
PM_SPIVID_FREQUENCY
SYSTEM Attribute
SPI Clock Frequency (binary in MHz)
Consumer: proc_pm_effective
Produces ATTR_PM_SPIVID_CLOCK_DIVIDER
Provided by the Machine Readable Workbook.
non-volatile
ATTR_PM_SPIVID_FREQUENCY
DIRECT
PM_SPIVID_PORT_ENABLE
PROC_CHIP Attribute
Defines the configuration of the SPIVID ports from the target.
- NONE means that no VRM is attached.
- PORTxNONRED means that the indicated port is used in a non-redundant
configuration.
- REDUNDANT means that all three are connected and considered redundant.
Provided by the Machine Readable Workbook.
non-volatile
ATTR_PM_SPIVID_PORT_ENABLE
DIRECT
PM_SAFE_FREQUENCY
SYSTEM Attribute
Indicates the frequency that the cores will be moved to in the event of
the loss of the OCC Heartbead. This value needs to be at or below the
nominal frequency to make sure safe operation of all chiplets.
Valid Values:-128 thru 127
The value is translated to the Pstate space.
Consumer: proc_pm_effective.C
DYNAMIC_ATTRIBUTE: ATTR_PM_SAFE_PSTATE
Consumer: proc_pcbs_init.C
TODO: Dean said this may either be provided by the Machine Readable
Workbook or Todd R's power management def file.
non-volatile
ATTR_PM_SAFE_FREQUENCY
DIRECT
PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY
SYSTEM Attribute
Frequency (binary in MHz) for the point at which clock sector buffers
should be at full strength. This is to support Vmin operation.
Setting cannot overlap the Low or High bands.
Provided by the Machine Readable Workbook after system characterization.
non-volatile
ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY
DIRECT
PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY
SYSTEM Attribute
Frequency (binary in MHz)) for the lower end of the Low Frequency
Resonant band
Provided by the Machine Readable Workbook after system characterization.
non-volatile
ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY
DIRECT
PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY
SYSTEM Attribute
Frequency (binary in MHz) for the upper end of the Low Frequency
Resonant band
Provided by the Machine Readable Workbook after system characterization.
non-volatile
ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY
DIRECT
PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY
SYSTEM Attribute
Frequency (binary in MHz) for the lower end of the High Frequency
Resonant band
Provided by the Machine Readable Workbook after system characterization.
non-volatile
ATTR_PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY
DIRECT
PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY
SYSTEM Attribute
Frequency (binary in MHz)) for the upper end of the High Frequency
Resonant band
Provided by the Machine Readable Workbook after system characterization.
non-volatile
ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY
DIRECT
PM_SPIPSS_FREQUENCY
SYSTEM Attribute
SPIPSS Clock Frequency (binary in MHz)
Valid range: 0.5MHz to 25MHz
Consumer: proc_pmc_init
Provided by the Machine Readable Workbook.
non-volatile
ATTR_PM_SPIPSS_FREQUENCY
DIRECT
PM_APSS_CHIP_SELECT
PROC_CHIP Attribute
Defines which of the PSS chip selects that the APSS is connected
Provided by the Machine Readable Workbook.
non-volatile
ATTR_PM_APSS_CHIP_SELECT
DIRECT
PM_PBAX_NODEID
PROC_CHIP Attribute
Receive PBAX Nodeid. Value that indicates this PBA's PBAX Node affinity.
This is matched to pbax_nodeid of the PMISC Address phase.
Provided by the Machine Readable Workbook.
non-volatile
ATTR_PM_PBAX_NODEID
DIRECT
PM_PBAX_CHIPID
PROC_CHIP Attribute
Receive PBAX Chipid. Value that indicates this PBA's PBAX Chipid within
the PBAX node. Is matched to pbax_chipid of the Address phase if
pbax_type=unicast.
Provided by the Machine Readable Workbook.
non-volatile
ATTR_PM_PBAX_CHIPID
DIRECT
PM_PBAX_BRDCST_ID_VECTOR
PROC_CHIP Attribute
Receive PBAX Broadcast Group. Vector that is indexed when decoded PMISC
pbax_type=broadcast with the decoded PMISC pbax_chipid value. If the
bit in this vector at the decoded bit location is a 1, then this receive
engine will participate in the broadcast operation.
Provided by the Machine Readable Workbook.
non-volatile
ATTR_PM_PBAX_BRDCST_ID_VECTOR
DIRECT
FREQ_CORE_MAX
SYSTEM Attribute
Maximum frequency (binary in MHz) that any processor in the system will
run. Used to define the top end of the PState range in the frequency space.
From this, the ATTR_PROCPM_PSTATE0_FREQUENCY is computed using
ATTR_SYSTEM_REFCLK_FREQUENCY to determine the step size.
Consumers: proc_build_gpstate_table.C (among others)
TODO: Dean's proposal is that each platform will iterate over all chips,
reading the super-turbo frequency from MVPD #V and set this attribute
to the lowest value.
non-volatile
ATTR_FREQ_CORE_MAX
DIRECT
OVERRIDE_MVPD_NOM_FREQ_MHZ
Module VPD #V keyword Nominal Frequency in MHZ
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_NOM_FREQ_MHZ
DIRECT
OVERRIDE_MVPD_V_NEST_NOM_VOLTAGE
Module VPD #V keyword V-nest nominal voltage
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_V_NEST_NOM_VOLTAGE
DIRECT
OVERRIDE_MVPD_I_NEST_NOM_CURRENT
Module VPD #V keyword I-nest nominal current
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_I_NEST_NOM_CURRENT
DIRECT
OVERRIDE_MVPD_V_CS_NOM_VOLTAGE
Module VPD #V keyword V-cs nominal voltage
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_V_CS_NOM_VOLTAGE
DIRECT
OVERRIDE_MVPD_I_CS_NOM_CURRENT
Module VPD #V keyword I-cs nominal current
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_I_CS_NOM_CURRENT
DIRECT
OVERRIDE_MVPD_PS_FREQ_MHZ
Module VPD #V keyword PowerSave Frequency in MHZ
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_PS_FREQ_MHZ
DIRECT
OVERRIDE_MVPD_V_NEST_PS_VOLTAGE
Module VPD #V keyword V-nest powersave voltage
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_V_NEST_PS_VOLTAGE
DIRECT
OVERRIDE_MVPD_I_NEST_PS_CURRENT
Module VPD #V keyword I-nest powersave current
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_I_NEST_PS_CURRENT
DIRECT
OVERRIDE_MVPD_V_CS_PS_VOLTAGE
Module VPD #V keyword V-cs powersave voltage
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_V_CS_PS_VOLTAGE
DIRECT
OVERRIDE_MVPD_I_CS_PS_CURRENT
Module VPD #V keyword I-cs powersave current
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_I_CS_PS_CURRENT
DIRECT
OVERRIDE_MVPD_TURBO_FREQ_MHZ
Module VPD #V keyword turbo frequency in MHZ
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_TURBO_FREQ_MHZ
DIRECT
OVERRIDE_MVPD_V_NEST_TURBO_VOLTAGE
Module VPD #V keyword V-nest turbo voltage
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_V_NEST_TURBO_VOLTAGE
DIRECT
OVERRIDE_MVPD_I_NEST_TURBO_CURRENT
Module VPD #V keyword I-nest turbo current
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_I_NEST_TURBO_CURRENT
DIRECT
OVERRIDE_MVPD_V_CS_TURBO_VOLTAGE
Module VPD #V keyword V-cs turbo voltage
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_V_CS_TURBO_VOLTAGE
DIRECT
OVERRIDE_MVPD_I_CS_TURBO_CURRENT
Module VPD #V keyword I-cs turbo current
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_I_CS_TURBO_CURRENT
DIRECT
OVERRIDE_MVPD_FVMIN_FREQ_MHZ
Module VPD #V keyword fvmin frequency MHZ
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_FVMIN_FREQ_MHZ
DIRECT
OVERRIDE_MVPD_V_NEST_FVMIN_VOLTAGE
Module VPD #V keyword V-nest fvmin voltage
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_V_NEST_FVMIN_VOLTAGE
DIRECT
OVERRIDE_MVPD_I_NEST_FVMIN_CURRENT
Module VPD #V keyword I-nest fvmin current
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_I_NEST_FVMIN_CURRENT
DIRECT
OVERRIDE_MVPD_V_CS_FVMIN_VOLTAGE
Module VPD #V keyword V-cs fvmin voltage
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_V_CS_FVMIN_VOLTAGE
DIRECT
OVERRIDE_MVPD_I_CS_FVMIN_CURRENT
Module VPD #V keyword I-cs fvmin current
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_I_CS_FVMIN_CURRENT
DIRECT
OVERRIDE_MVPD_LAB_FREQ_MHZ
Module VPD #V keyword lab frequency MHZ
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_LAB_FREQ_MHZ
DIRECT
OVERRIDE_MVPD_V_NEST_LAB_VOLTAGE
Module VPD #V keyword V-nest lab voltage
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_V_NEST_LAB_VOLTAGE
DIRECT
OVERRIDE_MVPD_I_NEST_LAB_CURRENT
Module VPD #V keyword I-nest lab current
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_I_NEST_LAB_CURRENT
DIRECT
OVERRIDE_MVPD_V_CS_LAB_VOLTAGE
Module VPD #V keyword V-cs lab voltage
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_V_CS_LAB_VOLTAGE
DIRECT
OVERRIDE_MVPD_I_CS_LAB_CURRENT
Module VPD #V keyword I-cs lab current
consumer: p8_build_pstate_datablock, others
firmware notes: Used as override attribute for pstate procedure
volatile-zeroed
ATTR_OVERRIDE_MVPD_I_CS_LAB_CURRENT
DIRECT
PROC_PCIE_IOP_CONFIG
PCIE IOP lane configuration
creator: platform
consumer: proc_pcie_scominit
firmware notes:
Encoded PCIE IOP lane configuration
non-volatile
ATTR_PROC_PCIE_IOP_CONFIG
DIRECT
PROC_PCIE_IOP_SWAP
PCIE IOP swap configuration
creator: platform
consumer: proc_pcie_scominit
firmware notes:
Encoded PCIE IOP swap configuration
Array index: IOP number (0:1)
2
non-volatile
ATTR_PROC_PCIE_IOP_SWAP
DIRECT
PROC_PCIE_PHB_ACTIVE
PCIE PHB valid mask
creator: platform
consumer: proc_pcie_scominit
firmware notes:
Bit mask defining set of active/valid PHBs
bit0=PHB0, bit1=PHB1, bit2=PHB2
non-volatile
ATTR_PROC_PCIE_PHB_ACTIVE
DIRECT
PROC_PCIE_IOP_G3_PLL_CONTROL0
creator: platform (MRW)
consumer: proc_pcie_scominit
firmware notes:
PCIe Gen3 PLL Control Register 0.
ATUNE/CPISEL.
Array index: IOP number(0:1)
2
non-volatile
ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0
DIRECT
PROC_PCIE_IOP_G2_PLL_CONTROL0
creator: platform (MRW)
consumer: proc_pcie_scominit
firmware notes:
PCIe Gen2/Gen1 PLL Control Register 0.
ATUNE/CPISEL.
Array index: IOP number(0:1)
2
non-volatile
ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0
DIRECT
PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0
creator: platform (MRW)
consumer: proc_pcie_scominit
notes:
PCIe PLL Global Control Register 0.
REFISRC/REFISINK.
Array index: IOP number (0:1)
2
non-volatile
ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0
DIRECT
PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1
creator: platform (MRW)
consumer: proc_pcie_scominit
notes:
PCIe PLL Global Control Register 1.
ENBGDOCPSRC/ENBGDOCAMP/REFVREG.
Array index: IOP number (0:1)
2
non-volatile
ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1
DIRECT
PROC_PCIE_IOP_PCS_CONTROL0
creator: platform (MRW)
consumer: proc_pcie_scominit
notes:
PCIe PCS Control Register 0.
BITLOCKTIME/ADDDREMDELTA_810_B/STARTUPDELTA_810_B/ADDDREMDELTA_810_A/
STARTUPDELTA_A/RXREJECTHANDLING/EQCOMLETERESPONSE.
Array index: IOP number (0:1)
2
non-volatile
ATTR_PROC_PCIE_IOP_PCS_CONTROL0
DIRECT
PROC_PCIE_IOP_PCS_CONTROL1
creator: platform (MRW)
consumer: proc_pcie_scominit
notes:
PCIe PCS Control Register 1.
RXSIGDETSETTING/ADDDREMDELTA_128130_B/STARTUPDELTA_128130_B/
ADDDREMDELTA_128130_A/STARTUPDELTA_128130_A.
Array index: IOP number (0:1)
2
non-volatile
ATTR_PROC_PCIE_IOP_PCS_CONTROL1
DIRECT
PROC_PCIE_IOP_TX_FIFO_OFFSET
creator: platform (MRW)
consumer: proc_pcie_scominit
notes:
PCIe TX FIFO Offset Register.
G3OFFSET/G2OFFSET/G1OFFSET.
First array index: IOP number (0:1)
Second array index: Lane number (0:15)
2,16
non-volatile
ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET
DIRECT
PROC_PCIE_IOP_TX_RCVRDETCNTL
creator: platform (MRW)
consumer: proc_pcie_scominit
notes:
PCIe TX Receiver Detect Control Register.
VREFSEL/RCVRDETCNT/DETDRVC/PH1WAIT.
First array index: IOP number (0:1)
Second array index: Lane number (0:15)
2,16
non-volatile
ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL
DIRECT
PROC_PCIE_IOP_TX_BWLOSS1
creator: platform (MRW)
consumer: proc_pcie_scominit
notes:
PCIe TX Bandwidth Loss Coefficient Register.
GEN3BWCOEFF/GEN2BWCOEFF/GEN1BWCOEFF.
First array index: IOP number (0:1)
Second array index: Lane number (0:15)
2,16
non-volatile
ATTR_PROC_PCIE_IOP_TX_BWLOSS1
DIRECT
PROC_PCIE_IOP_RX_VGA_CONTROL2
creator: platform (MRW)
consumer: proc_pcie_scominit
notes:
PCIe RX VGA Control Register 2.
GAIN2/GAIN1.
First array index: IOP number (0:1)
Second array index: Lane number (0:15)
2,16
non-volatile
ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2
DIRECT
PROC_PCIE_IOP_RX_PEAK
creator: platform (MRW)
consumer: proc_pcie_scominit
notes:
PCIe RX Receiver Peaking Value Register.
PEAK1/PEAK2/PEAK3.
First array index: IOP number (0:1)
Second array index: Lane number (0:15)
2,16
non-volatile
ATTR_PROC_PCIE_IOP_RX_PEAK
DIRECT
PROC_PCIE_IOP_RX_SDL
creator: platform (MRW)
consumer: proc_pcie_scominit
notes:
PCIe RX Signal Detect Level Register.
SDLVL3/SDLVL2/SDLVL1.
First array index: IOP number (0:1)
Second array index: Lane number (0:15)
2,16
non-volatile
ATTR_PROC_PCIE_IOP_RX_SDL
DIRECT
PROC_PCIE_IOP_ZCAL_CONTROL
creator: platform (MRW)
consumer: proc_pcie_scominit
notes:
PCIe ZCAL Control Register.
CMPEVALDLY.
Array index: IOP number (0:1)
2
non-volatile
ATTR_PROC_PCIE_IOP_ZCAL_CONTROL
DIRECT
VMEM_ID
Voltage Memory Rail Manager ID. Currently HB only needs
to configured the Vmem voltage rail manger during the IPL. The ID
is an arbitary value and needed as correlation token between HB and
HWSV. It will be generated by the genHwsvMrwXml.pl.
0
non-volatile
NEST_FREQ_MHZ
Nest frequency in MHz
Default should be 2000 MHz per Greg Still
2000
volatile
ATTR_NEST_FREQ_MHZ
DIRECT
CHIP_REGIONS_TO_ENABLE
Called to get data to customize an IPL or SLW image with data indicating
which chip regions the SBE should enable
The data is in the format of the Module VPD PG (Partial Good Vector)
keyword which is an 32 entry array of 16bit words, each word
represents a chiplet and a defined set of bits within the word
represents regions that are good. The 16 bit word is embedded within
a 64bit word as described in the MVPD spec to reflect the clock
controller region register layout:
bits 0:3 are reserved -> set to 0
bits 4:19 are the 16 bit data word
bits 20:63 are reserved -> set to 0
A platform needs to return data indicating the chip regions to enable,
this may not be just the MVPD partial-good data, it may also not enable
other chips and chiplets it has decided are non-functional - this is
why it is not a standard MVPD query.
32
volatile-zeroed
ATTR_CHIP_REGIONS_TO_ENABLE
DIRECT
BOOT_FREQ_MHZ
Boot frequency in MHZ. Default is 50% of nominal.
2400
volatile
ATTR_BOOT_FREQ_MHZ
DIRECT
EX_GARD_BITS
Vector to communicate the guarded EX chiplets to SBE
One Guard bit per EX chiplet, bit location aligned to chiplet ID
(bit 16: EX00, bit 17: EX01, bit 18: EX02 ... bit 31: EX15)
Guarded EX chiplets are marked by a '1'.
0
volatile
ATTR_EX_GARD_BITS
DIRECT
PIB_I2C_REFCLOCK
i2c reference clock for the system.
default is 0x4 => I2C speed = ~1Mhz per Andreas Koenig
0x4
volatile
ATTR_PIB_I2C_REFCLOCK
DIRECT
PROC_ADU_UNTRUSTED_BAR_BASE_ADDR
ADU Untrusted BAR base address (secure mode)
creator: platform
firmware notes:
64-bit address representing BAR RA
0x0000000000000000
non-volatile
ATTR_PROC_ADU_UNTRUSTED_BAR_BASE_ADDR
DIRECT
PIB_I2C_NEST_PLL
i2c pll for the system
default is 0x26 (For PIB @500 MHz (2 GHz nest)) for
I2C speed = ~1Mhz per Andreas Koenig.
0x026
volatile
ATTR_PIB_I2C_NEST_PLL
DIRECT
PROC_ADU_UNTRUSTED_BAR_SIZE
ADU Untrusted BAR size (secure mode)
creator: platform
firmware notes:
mask applied to RA 14:43
0x0000000004000000
non-volatile
ATTR_PROC_ADU_UNTRUSTED_BAR_SIZE
DIRECT
SBE_IMAGE_OFFSET
HostBoot image for SBE, offset to account for ECC
Default is calculated from Hostboot base image of 0x3ece000
0xffef0000
volatile
ATTR_SBE_IMAGE_OFFSET
DIRECT
PROC_PSI_UNTRUSTED_BAR0_BASE_ADDR
PSI Untrusted BAR0 base address (secure mode)
creator: platform
firmware notes:
64-bit address representing BAR RA
0x0000000000000000
non-volatile
ATTR_PROC_PSI_UNTRUSTED_BAR0_BASE_ADDR
DIRECT
BOOT_VOLTAGE
Boot Voltage for system.
0:2 -> port enables (3b - system design based:
port 0 for non-redundant systems (100); all ports for non-redundant (111))
3 -> Unused
- current recommended default = 1000b
4:7 -> phase enables (4b - defined by the system power design)
- current recommended default = 0000b
8:15 -> VDD voltage (1B in VRM-11 encoded form - 6.25mV increments)
note: VPD is in 5mV increments
- current recommended default = 0x52
16:23 -> VCS voltage (1B in VRM-11 encoded form - 6.25mV increments)
note: VPD is in 5mV increments
-current recommended default = 0x4a
24:31 -> Unused = 0x00
0x80524a00
volatile
ATTR_BOOT_VOLTAGE
DIRECT
PROC_PSI_UNTRUSTED_BAR0_SIZE
PSI Untrusted BAR0 size (secure mode)
creator: platform
firmware notes:
mask applied to RA 14:43
0x0000000004000000
non-volatile
ATTR_PROC_PSI_UNTRUSTED_BAR0_SIZE
DIRECT
PROC_PSI_UNTRUSTED_BAR1_BASE_ADDR
PSI Untrusted BAR1 base address (secure mode)
creator: platform
firmware notes:
64-bit address representing BAR RA
0x0000000000000000
non-volatile
ATTR_PROC_PSI_UNTRUSTED_BAR1_BASE_ADDR
DIRECT
PROC_PSI_UNTRUSTED_BAR1_SIZE
PSI Untrusted BAR1 size (secure mode)
creator: platform
firmware notes:
mask applied to RA 14:43
0x0000000004000000
non-volatile
ATTR_PROC_PSI_UNTRUSTED_BAR1_SIZE
DIRECT
PROC_SECURITY_SETUP_VECTOR
Secureboot 64-bit proc_sbe_security_setup_vector used
by proc_sbe_security_setup.S. 0s are an unsecure SBE image
creator: platform
firmware notes:
64-bit proc_sbe_security_setup_vector
0x0000000000000000
non-volatile
ATTR_PROC_SECURITY_SETUP_VECTOR
DIRECT
MSS_VOLT
DRAM Voltage. Initialized and used by HWPs.
volatile-zeroed
ATTR_MSS_VOLT
DIRECT
MSS_FREQ
Frequency of memory channel in MHz. Initialized and used by HWPs.
volatile-zeroed
ATTR_MSS_FREQ
DIRECT
MSS_DIMM_MFG_ID_CODE
DIMM Manufacturer ID Code. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_MSS_DIMM_MFG_ID_CODE
DIRECT
EFF_DIMM_RANKS_CONFIGED
DIMM ranks configured. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_EFF_DIMM_RANKS_CONFIGED
DIRECT
EFF_NUM_RANKS_PER_DIMM
Number of ranks per DIMM. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_EFF_NUM_RANKS_PER_DIMM
DIRECT
EFF_DIMM_TYPE
Type of DIMM. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DIMM_TYPE
DIRECT
EFF_CUSTOM_DIMM
DIMM is a custom DIMM. Sometimes this is known as a CDIMM, but technically, we could support Custom DIMMs of different types than an UDIMM, such as RDIMM and LRDIMM. Created in mss_eff_cnfg
volatile-zeroed
ATTR_EFF_CUSTOM_DIMM
DIRECT
EFF_DRAM_WIDTH
DRAM Device Width. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_WIDTH
DIRECT
EFF_DRAM_GEN
DRAM Generation. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_GEN
DIRECT
EFF_PRIMARY_RANK_GROUP0
Primary RankGroup0. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_PRIMARY_RANK_GROUP0
DIRECT
EFF_PRIMARY_RANK_GROUP1
Primary RankGroup1. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_PRIMARY_RANK_GROUP1
DIRECT
EFF_PRIMARY_RANK_GROUP2
Primary RankGroup2. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_PRIMARY_RANK_GROUP2
DIRECT
EFF_PRIMARY_RANK_GROUP3
Primary RankGroup3. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_PRIMARY_RANK_GROUP3
DIRECT
EFF_SECONDARY_RANK_GROUP0
Secondary RankGroup0. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_SECONDARY_RANK_GROUP0
DIRECT
EFF_SECONDARY_RANK_GROUP1
Secondary RankGroup1. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_SECONDARY_RANK_GROUP1
DIRECT
EFF_SECONDARY_RANK_GROUP2
Secondary RankGroup2. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_SECONDARY_RANK_GROUP2
DIRECT
EFF_SECONDARY_RANK_GROUP3
Secondary RankGroup3. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_SECONDARY_RANK_GROUP3
DIRECT
EFF_TERTIARY_RANK_GROUP0
Tertiary RankGroup0. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_TERTIARY_RANK_GROUP0
DIRECT
EFF_TERTIARY_RANK_GROUP1
Tertiary RankGroup1. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_TERTIARY_RANK_GROUP1
DIRECT
EFF_TERTIARY_RANK_GROUP2
Tertiary RankGroup2. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_TERTIARY_RANK_GROUP2
DIRECT
EFF_TERTIARY_RANK_GROUP3
Tertiary RankGroup3. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_TERTIARY_RANK_GROUP3
DIRECT
EFF_QUATERNARY_RANK_GROUP0
Quaternary RankGroup0. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_QUATERNARY_RANK_GROUP0
DIRECT
EFF_QUATERNARY_RANK_GROUP1
Quaternary RankGroup1. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_QUATERNARY_RANK_GROUP1
DIRECT
EFF_QUATERNARY_RANK_GROUP2
Quaternary RankGroup2. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_QUATERNARY_RANK_GROUP2
DIRECT
EFF_QUATERNARY_RANK_GROUP3
Quaternary RankGroup3. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_QUATERNARY_RANK_GROUP3
DIRECT
EFF_ODT_RD
Rank Read ODT. Initialized and used by HWPs.
2,2,4
volatile-zeroed
ATTR_EFF_ODT_RD
DIRECT
EFF_ODT_WR
Rank Write ODT. Initialized and used by HWPs.
2,2,4
volatile-zeroed
ATTR_EFF_ODT_WR
DIRECT
EFF_DRAM_RON
DRAM Ron. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_EFF_DRAM_RON
DIRECT
EFF_DRAM_RTT_NOM
DRAM Rtt_Nom. Initialized and used by HWPs.
2,2,4
volatile-zeroed
ATTR_EFF_DRAM_RTT_NOM
DIRECT
EFF_DRAM_RTT_WR
DRAM Rtt_WR. Initialized and used by HWPs.
2,2,4
volatile-zeroed
ATTR_EFF_DRAM_RTT_WR
DIRECT
EFF_DRAM_WR_VREF
DRAM Write Vref. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_DRAM_WR_VREF
DIRECT
EFF_DRAM_WRDDR4_VREF
DRAM Write Vref for DDR4. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_DRAM_WRDDR4_VREF
DIRECT
EFF_CEN_DRV_IMP_DQ_DQS
Centaur DQ and DQS Drive Impedance. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_DRV_IMP_DQ_DQS
DIRECT
EFF_CEN_DRV_IMP_ADDR
Centaur Address Drive Impedance. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_DRV_IMP_ADDR
DIRECT
EFF_CEN_DRV_IMP_CNTL
Centaur Control Drive Impedance. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_DRV_IMP_CNTL
DIRECT
EFF_CEN_DRV_IMP_CLK
Centaur Clock Drive Impedance. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_DRV_IMP_CLK
DIRECT
EFF_CEN_DRV_IMP_SPCKE
Centaur Spare Clock Drive Impedance. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_DRV_IMP_SPCKE
DIRECT
EFF_CEN_RCV_IMP_DQ_DQS
Centaur DQ and DQS Receiver Impedance. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_RCV_IMP_DQ_DQS
DIRECT
EFF_CEN_SLEW_RATE_DQ_DQS
Centaur DQ and DQS Slew Rate. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_SLEW_RATE_DQ_DQS
DIRECT
EFF_CEN_SLEW_RATE_ADDR
Centaur Address Slew Rate. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_SLEW_RATE_ADDR
DIRECT
EFF_CEN_SLEW_RATE_CLK
Centaur Clock Slew Rate. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_SLEW_RATE_CLK
DIRECT
EFF_CEN_SLEW_RATE_SPCKE
Centaur Spare Clock Slew Rate. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_SLEW_RATE_SPCKE
DIRECT
EFF_CEN_SLEW_RATE_CNTL
Centaur Control Slew Rate. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_SLEW_RATE_CNTL
DIRECT
EFF_CEN_RD_VREF
Centaur Read Vref. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_RD_VREF
DIRECT
EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO
Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO
DIRECT
EFF_CEN_DRV_IMP_CLK_SCHMOO
Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_DRV_IMP_CLK_SCHMOO
DIRECT
EFF_CEN_DRV_IMP_SPCKE_SCHMOO
Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_DRV_IMP_SPCKE_SCHMOO
DIRECT
EFF_CEN_DRV_IMP_CNTL_SCHMOO
Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_DRV_IMP_CNTL_SCHMOO
DIRECT
EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO
Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO
DIRECT
EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO
Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO
DIRECT
EFF_CEN_SLEW_RATE_CLK_SCHMOO
Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_SLEW_RATE_CLK_SCHMOO
DIRECT
EFF_CEN_SLEW_RATE_SPCKE_SCHMOO
Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO
DIRECT
EFF_CEN_SLEW_RATE_ADDR_SCHMOO
Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_SLEW_RATE_ADDR_SCHMOO
DIRECT
EFF_CEN_SLEW_RATE_CNTL_SCHMOO
Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_SLEW_RATE_CNTL_SCHMOO
DIRECT
EFF_DRAM_WR_VREF_SCHMOO
Enables for which VREF to use on the WR Schmoo. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_DRAM_WR_VREF_SCHMOO
DIRECT
EFF_DRAM_WRDDR4_VREF_SCHMOO
Enables for which VREF to use on the WR Schmoo for DDR4. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_DRAM_WRDDR4_VREF_SCHMOO
DIRECT
EFF_CEN_RD_VREF_SCHMOO
Enables for which VREF value can be used in timing adjustments. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_EFF_CEN_RD_VREF_SCHMOO
DIRECT
EFF_DIMM_SIZE
DIMM Size. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_EFF_DIMM_SIZE
DIRECT
EFF_DRAM_BANKS
Number of DRAM banks. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_BANKS
DIRECT
EFF_DRAM_ROWS
Number of DRAM rows. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_ROWS
DIRECT
EFF_DRAM_COLS
Number of DRAM columns. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_COLS
DIRECT
EFF_DRAM_DENSITY
DRAM Density. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_DENSITY
DIRECT
EFF_DRAM_TRCD
DRAM RAS to CAS Delay. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_TRCD
DIRECT
EFF_DRAM_TRRD
DRAM Row ACT to Row ACT Delay. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_TRRD
DIRECT
EFF_DRAM_TRP
DRAM Row Precharge Delay. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_TRP
DIRECT
EFF_DRAM_TRAS
DRAM ACT to Precharge Delay. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_TRAS
DIRECT
EFF_DRAM_TRC
DRAM ACT to ACT/Refresh Delay. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_TRC
DIRECT
EFF_DRAM_TRFI
Refresh Interval. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_TRFI
DIRECT
EFF_DRAM_TRFC
DRAM Refresh Recovery Delay. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_TRFC
DIRECT
EFF_DRAM_TWTR
DRAM Internal Write to Read Delay. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_TWTR
DIRECT
EFF_DRAM_TRTP
DRAM Internal Read to Precharge Delay. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_TRTP
DIRECT
EFF_DRAM_TFAW
DRAM Four ACT Window Delay. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_TFAW
DIRECT
EFF_DRAM_BL
DRAM Burst Length. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_BL
DIRECT
EFF_DRAM_CL
DRAM CAS Latency. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_CL
DIRECT
EFF_DRAM_AL
DRAM Additive Latency. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_AL
DIRECT
EFF_DRAM_CWL
DRAM CAS Write Latency. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_CWL
DIRECT
EFF_DRAM_RBT
DRAM Read Burst Type. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_RBT
DIRECT
EFF_DRAM_TM
DRAM Test Mode. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_TM
DIRECT
EFF_DRAM_DLL_RESET
DRAM DLL Reset. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_DLL_RESET
DIRECT
EFF_DRAM_WR
DRAM Write Recovery. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_WR
DIRECT
EFF_DRAM_DLL_PPD
DRAM DLL Precharge PD. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_DLL_PPD
DIRECT
EFF_DRAM_DLL_ENABLE
DRAM DLL Enable. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_DLL_ENABLE
DIRECT
EFF_DRAM_TDQS
DRAM TDQS. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_TDQS
DIRECT
EFF_DRAM_WR_LVL_ENABLE
DRAM Write Level Enable. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_WR_LVL_ENABLE
DIRECT
EFF_DRAM_OUTPUT_BUFFER
DRAM output buffer. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_OUTPUT_BUFFER
DIRECT
EFF_DRAM_PASR
DRAM Partial Array Self-Refresh. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_PASR
DIRECT
EFF_DRAM_ASR
DRAM Auto Self-Refresh. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_ASR
DIRECT
EFF_DRAM_SRT
DRAM Self-Refresh Temperature Range. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_DRAM_SRT
DIRECT
EFF_MPR_LOC
Multi Purpose Register Location. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_MPR_LOC
DIRECT
EFF_MPR_MODE
Multi Purpose Register Mode. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_MPR_MODE
DIRECT
EFF_DIMM_RCD_CNTL_WORD_0_15
DIMM RCD Control Word. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15
DIRECT
EFF_DIMM_RCD_IBT
DIMM RCD IBT. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_EFF_DIMM_RCD_IBT
DIRECT
EFF_DIMM_RCD_MIRROR_MODE
DIMM RCD Mirror mode. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_EFF_DIMM_RCD_MIRROR_MODE
DIRECT
EFF_SCHMOO_MODE
Specifies the schmoo mode to use during draminit_train_adv. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_SCHMOO_MODE
DIRECT
EFF_SCHMOO_ADDR_MODE
Specifies the schmoo mode to use during draminit_train_adv. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_SCHMOO_ADDR_MODE
DIRECT
EFF_SCHMOO_TEST_VALID
Specifies the schmoo test to run during draminit_train_adv. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_SCHMOO_TEST_VALID
DIRECT
EFF_SCHMOO_PARAM_VALID
Specifies the schmoo parameters to use during draminit_train_adv. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_SCHMOO_PARAM_VALID
DIRECT
EFF_SCHMOO_WR_EYE_MIN_MARGIN
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
volatile-zeroed
ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN
DIRECT
EFF_SCHMOO_RD_EYE_MIN_MARGIN
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
volatile-zeroed
ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN
DIRECT
EFF_SCHMOO_DQS_CLK_MIN_MARGIN
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
volatile-zeroed
ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN
DIRECT
EFF_SCHMOO_RD_GATE_MIN_MARGIN
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
volatile-zeroed
ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN
DIRECT
EFF_SCHMOO_ADDR_CMD_MIN_MARGIN
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
volatile-zeroed
ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN
DIRECT
EFF_MEMCAL_INTERVAL
Specifies the memcal interval in clocks. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_MEMCAL_INTERVAL
DIRECT
EFF_ZQCAL_INTERVAL
Specifies the zqcal interval in clocks. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_ZQCAL_INTERVAL
DIRECT
EFF_IBM_TYPE
Specifies the memory topology type. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_EFF_IBM_TYPE
DIRECT
EFF_NUM_DROPS_PER_PORT
Specifies the number of DIMM dimensions that are valid per port. Initialized and used by HWPs.
volatile-zeroed
ATTR_EFF_NUM_DROPS_PER_PORT
DIRECT
EFF_STACK_TYPE
Specifies the DRAM package type. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_EFF_STACK_TYPE
DIRECT
EFF_NUM_MASTER_RANKS_PER_DIMM
Specifies the number of master ranks per DIMM. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM
DIRECT
EFF_NUM_PACKAGES_PER_RANK
Specifies the number of DRAM packages per rank. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_EFF_NUM_PACKAGES_PER_RANK
DIRECT
EFF_NUM_DIES_PER_PACKAGE
Specifies the number of DRAM dies per package. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_EFF_NUM_DIES_PER_PACKAGE
DIRECT
MSS_MEM_THROTTLE_NUMERATOR_PER_MBA
DIMM throttle numerator. Initialized and used by HWPs.
volatile-zeroed
ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA
DIRECT
MSS_MEM_THROTTLE_DENOMINATOR
DIMM throttle denominator. Initialized and used by HWPs.
volatile-zeroed
ATTR_MSS_MEM_THROTTLE_DENOMINATOR
DIRECT
MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP
This is the throttle numerator setting for cfg_nm_n_per_chip. Initialized and used by HWPs.
volatile-zeroed
ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP
DIRECT
MSS_MEM_WATT_TARGET
Channel total memory watts. Initialized and used by HWPs.
volatile-zeroed
ATTR_MSS_MEM_WATT_TARGET
DIRECT
MSS_POWER_SLOPE
DIMM Power slope value. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_MSS_POWER_SLOPE
DIRECT
MSS_POWER_SLOPE2
DIMM Power slope value. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_MSS_POWER_SLOPE2
DIRECT
MSS_POWER_INT
DIMM Power intercept value. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_MSS_POWER_INT
DIRECT
MSS_POWER_INT2
DIMM Power intercept value. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_MSS_POWER_INT2
DIRECT
MSS_DIMM_MAXBANDWIDTH_GBS
DIMM Max Bandwidth in GBs. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_MSS_DIMM_MAXBANDWIDTH_GBS
DIRECT
MSS_DIMM_MAXBANDWIDTH_MRS
DIMM Max Bandwidth in MRs. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_MSS_DIMM_MAXBANDWIDTH_MRS
DIRECT
MSS_CHANNEL_MAXBANDWIDTH_GBS
Channel Max Bandwidth in GBs. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_MSS_CHANNEL_MAXBANDWIDTH_GBS
DIRECT
MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS
Channel Pair Max Bandwidth in GBs. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS
DIRECT
MSS_CHANNEL_MAXBANDWIDTH_MRS
Channel Max Bandwidth MRs. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_MSS_CHANNEL_MAXBANDWIDTH_MRS
DIRECT
MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS
Channel Pair Max Bandwidth MRs. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS
DIRECT
MSS_DIMM_MAXPOWER
DIMM Max Power output. Initialized and used by HWPs.
2,2
volatile-zeroed
ATTR_MSS_DIMM_MAXPOWER
DIRECT
MSS_CHANNEL_MAXPOWER
Channel Max Power output. Initialized and used by HWPs.
2
volatile-zeroed
ATTR_MSS_CHANNEL_MAXPOWER
DIRECT
MSS_CHANNEL_PAIR_MAXPOWER
Channel Pair Max Power output. Initialized and used by HWPs.
volatile-zeroed
ATTR_MSS_CHANNEL_PAIR_MAXPOWER
DIRECT
MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA
Runtime throttle numerator setting for cfg_nm_n_per_mba. Initialized and used by HWPs.
volatile-zeroed
ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA
DIRECT
MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR
Runtime throttle denominator setting for cfg_nm_m. Initialized and used by HWPs.
volatile-zeroed
ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR
DIRECT
MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP
Runtime throttle numerator setting for cfg_nm_n_per_chip. Initialized and used by HWPs.
volatile-zeroed
ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP
DIRECT
MSS_ZSERIES
Determines if the code is Zseries type or P Series. The platform determines this and this attribute is mostly used in the initfiles so that we can share the same initialization code with the zSeries team
0
non-volatile
ATTR_MSS_ZSERIES
DIRECT
MSS_NWELL_MISPLACEMENT
Set by the platform depending on DD1 vs DD1.01. If true, then SI settings affected by the NWELL problem are adjusted. Used in eff_config
volatile-zeroed
ATTR_MSS_NWELL_MISPLACEMENT
DIRECT
MSS_INTERLEAVE_ENABLE
Used in the setting of groups. It is a bit vector. If the value BITWISE_AND 1 = 1 then groups of 1 are enabled with special checkerboard modes needed, if the value BITWISE_AND 2 = 2, then groups of 2 are possible; if value BITWISE_AND 4, the groups of 4 are possible; if value BITWISE_AND 8, the groups of 8 are possible. If no groups can formed according to this input, then an error will be thrown.
0x07
non-volatile
ATTR_MSS_INTERLEAVE_ENABLE
DIRECT
MSS_MBA_ADDR_INTERLEAVE_BIT
sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. valid values are 23 through 32.
0
non-volatile
ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT
DIRECT
MSS_MBA_CACHELINE_INTERLEAVE_MODE
centaur interleave mode. 1 = 256-BIT, 0 = 128-BIT.
0
non-volatile
ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE
DIRECT
MSS_CACHE_ENABLE
Specifies if a Memory Buffer chip L4 cache is enabled or disabled
For good memory buffer chips, L4 is enabled
Firmware can set to disabled for a particular chip if the cache is
not functional
1 = enabled, 0 = disabled.
0
volatile
ATTR_MSS_CACHE_ENABLE
DIRECT
MSS_PREFETCH_ENABLE
Prefteching enable. 1 = enable, 0 = disable.
0
non-volatile
ATTR_MSS_PREFETCH_ENABLE
DIRECT
MSS_CLEANER_ENABLE
L4 cleaner enable. 1 = enable, 0 = disable.
0
non-volatile
ATTR_MSS_CLEANER_ENABLE
DIRECT
MSS_LAB_OVERRIDE_FOR_MEM_PLL
override the default Centaur MEM PLL settings with user-specified scan chain data. 1 = ON, 0 = OFF.
volatile-zeroed
ATTR_MSS_LAB_OVERRIDE_FOR_MEM_PLL
DIRECT
MSS_MEM_MC_IN_GROUP
A 8 bit vector that would be a designation of which MC are involved in the group. Initialized and used by HWPs.
8
volatile-zeroed
ATTR_MSS_MEM_MC_IN_GROUP
DIRECT
MSS_MCS_GROUP_32
Data Structure from eff grouping to setup bars to help determine different groups
Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
// Mirroring [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
Measured in GB
16,16
volatile-zeroed
ATTR_MSS_MCS_GROUP_32
DIRECT
MSS_EFF_DIMM_FUNCTIONAL_VECTOR
A bit vector (per Dean's request) specifying if a DIMM is functional. DIMM attributes, such as SIZE, are qualified by this bit vector. The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional. 0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional. A fully populated system would have the value of 0xCC. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none
This factors in functionality
volatile-zeroed
ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR
DIRECT
MSS_CAL_STEP_ENABLE
A bit vector denoting valid cal steps to run during dram_init_train. [0] EXT_ZQCAL
[1] WR_LEVEL
[2] DQS_ALIGN
[3] RDCLK_ALIGN
[4] READ_CTR
[5] WRITE_CTR
[6] COARSE_WR
[7] COARSE_RD
bits6:7 will be consumed together to form COARSE_LVL.
volatile-zeroed
ATTR_MSS_CAL_STEP_ENABLE
DIRECT
MSS_MEM_IPL_COMPLETE
A numerical number indicating if the memory procedures are complete. written by mss_setup_bars when the bars are now functional in the processor.
volatile-zeroed
ATTR_MSS_MEM_IPL_COMPLETE
DIRECT
MSS_SLEW_RATE_DATA
The 4 bit result of running the slew calibration algorithm at various rates and impedances
2, 4, 4
volatile-zeroed
ATTR_MSS_SLEW_RATE_DATA
DIRECT
MSS_SLEW_RATE_ADR
The 4 bit result of running the slew calibration algorithm at various rates and impedances
2, 4, 4
volatile-zeroed
ATTR_MSS_SLEW_RATE_ADR
DIRECT
ECID
Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1
Created from running proc_getecid.C for processors
Created from running mss_get_cen_ecid.C for centaurs
2
volatile-zeroed
ATTR_ECID
DIRECT
MSS_ALLOW_SINGLE_PORT
When this value is true, then mss_eff config will allow a single port to have one dimm and will allow ports to have different sizes. Used in eff_config
0
non-volatile
ATTR_MSS_ALLOW_SINGLE_PORT
DIRECT
EFF_CEN_PHASE_ROT_M0_CLK_P0
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0
DIRECT
EFF_CEN_PHASE_ROT_M0_CLK_P1
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1
DIRECT
EFF_CEN_PHASE_ROT_M1_CLK_P0
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0
DIRECT
EFF_CEN_PHASE_ROT_M1_CLK_P1
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A0
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A1
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A2
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A3
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A4
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A5
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A6
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A7
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A8
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A9
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A10
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A11
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A12
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A13
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A14
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_A15
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_BA0
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_BA1
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_BA2
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_CASN
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_RASN
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN
DIRECT
EFF_CEN_PHASE_ROT_M_CMD_WEN
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN
DIRECT
EFF_CEN_PHASE_ROT_M_PAR
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_PAR
DIRECT
EFF_CEN_PHASE_ROT_M_ACTN
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M_ACTN
DIRECT
EFF_CEN_PHASE_ROT_M0_CNTL_CKE0
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0
DIRECT
EFF_CEN_PHASE_ROT_M0_CNTL_CKE1
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1
DIRECT
EFF_CEN_PHASE_ROT_M0_CNTL_CKE2
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2
DIRECT
EFF_CEN_PHASE_ROT_M0_CNTL_CKE3
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3
DIRECT
EFF_CEN_PHASE_ROT_M0_CNTL_CSN0
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0
DIRECT
EFF_CEN_PHASE_ROT_M0_CNTL_CSN1
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1
DIRECT
EFF_CEN_PHASE_ROT_M0_CNTL_CSN2
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2
DIRECT
EFF_CEN_PHASE_ROT_M0_CNTL_CSN3
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3
DIRECT
EFF_CEN_PHASE_ROT_M0_CNTL_ODT0
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0
DIRECT
EFF_CEN_PHASE_ROT_M0_CNTL_ODT1
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1
DIRECT
EFF_CEN_PHASE_ROT_M1_CNTL_CKE0
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0
DIRECT
EFF_CEN_PHASE_ROT_M1_CNTL_CKE1
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1
DIRECT
EFF_CEN_PHASE_ROT_M1_CNTL_CKE2
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2
DIRECT
EFF_CEN_PHASE_ROT_M1_CNTL_CKE3
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3
DIRECT
EFF_CEN_PHASE_ROT_M1_CNTL_CSN0
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0
DIRECT
EFF_CEN_PHASE_ROT_M1_CNTL_CSN1
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1
DIRECT
EFF_CEN_PHASE_ROT_M1_CNTL_CSN2
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2
DIRECT
EFF_CEN_PHASE_ROT_M1_CNTL_CSN3
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3
DIRECT
EFF_CEN_PHASE_ROT_M1_CNTL_ODT0
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0
DIRECT
EFF_CEN_PHASE_ROT_M1_CNTL_ODT1
Phase rotator value that comes from termination on the CDIMM VPD
0
2
volatile
ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1
DIRECT
MSS_DQS_SWIZZLE_TYPE
DQS Swizzle type is set by the platform to describe what kind of DQS connection is being used for register acceses. Type 0 is normal, type 1 is for systems with wiring like glacier 1. Additional types maybe defined if new boards have even different DQS swizzle features
0
non-volatile
ATTR_MSS_DQS_SWIZZLE_TYPE
DIRECT
MSS_MCS_GROUP
Data Structure from eff grouping to setup bars to help determine different groups
Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
// Mirroring [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
Measured in GB
16,16
volatile-zeroed
ATTR_MSS_MCS_GROUP
DIRECT
EFF_CKE_MAP
Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none
2,2,4
volatile-zeroed
ATTR_EFF_CKE_MAP
DIRECT
EFF_SPCKE_MAP
Rank to Spare CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none
2,2,4
volatile-zeroed
ATTR_EFF_SPCKE_MAP
DIRECT
EFF_DIMM_SPARE
Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg consumer: various firmware notes: load from spd
2,2,4
volatile-zeroed
ATTR_EFF_DIMM_SPARE
DIRECT
MSS_PSRO
Set by the centaur mss_get_cen_ecid function used diagnostic and chip characterization reporting
volatile-zeroed
ATTR_MSS_PSRO
DIRECT
EI_BUS_TX_LANE_INVERT
This attribute represents the polarity of a differential wire pair on the DMI and A buses.
creator: platform (generated based on MRW data)
See defintion in common_attributes.xml for more information.
0
non-volatile
ATTR_EI_BUS_TX_LANE_INVERT
DIRECT
PROC_PERV_BNDY_PLL_CHIPLET_ID
Chiplet ID for ring image for perv_bndy_pll ring containing filter plls and xb_pll,nest_pll
creator: platform
firmware notes:
0
volatile
ATTR_PROC_PERV_BNDY_PLL_CHIPLET_ID
DIRECT
PROC_PB_BNDY_DMIPLL_CHIPLET_ID
Chiplet ID for ring image for pb_bndy_dmipll ring
creator: platform
firmware notes:
0
volatile
ATTR_PROC_PB_BNDY_DMIPLL_CHIPLET_ID
DIRECT
PROC_AB_BNDY_PLL_CHIPLET_ID
Chiplet ID for ring image for ab_bndy_pll ring
creator: platform
firmware notes:
0
volatile
ATTR_PROC_AB_BNDY_PLL_CHIPLET_ID
DIRECT
PROC_PCI_BNDY_PLL_CHIPLET_ID
Chiplet ID for ring image for pci_bndy_pll ring
creator: platform
firmware notes:
0
volatile
ATTR_PROC_PCI_BNDY_PLL_CHIPLET_ID
DIRECT
PROC_PERV_BNDY_PLL_SCAN_SELECT
Scan select for ring image for perv_bndy_pll ring containing filter plls and xb_pll,nest_pll
creator: platform
firmware notes:
0x00100008
volatile
ATTR_PROC_PERV_BNDY_PLL_SCAN_SELECT
DIRECT
PROC_PB_BNDY_DMIPLL_SCAN_SELECT
Scan select for ring image for pb_bndy_dmipll ring
creator: platform
firmware notes:
0
volatile
ATTR_PROC_PB_BNDY_DMIPLL_SCAN_SELECT
DIRECT
PROC_AB_BNDY_PLL_SCAN_SELECT
Scan select for ring image for ab_bndy_pll ring
creator: platform
firmware notes:
0
volatile
ATTR_PROC_AB_BNDY_PLL_SCAN_SELECT
DIRECT
PROC_PCI_BNDY_PLL_SCAN_SELECT
Scan select for ring image for pci_bndy_pll ring
creator: platform
firmware notes:
0
volatile
ATTR_PROC_PCI_BNDY_PLL_SCAN_SELECT
DIRECT
SBE_SEEPROM_I2C_ADDRESS_BYTES
The number of address bytes required to address the SEEPROM memory
device that contains SBE IPL code. This will vary by device based on
the device capacity, and must be either 1, 2, 3 or 4.
4
non-volatile
ATTR_SBE_SEEPROM_I2C_ADDRESS_BYTES
DIRECT
SBE_SEEPROM_I2C_DEVICE_ADDRESS
A 2-element array containing the I2C device address of the primary (0)
and secondary (1) SEEPROM devices containing SBE IPL code.
Provided by the Machine Readable Workbook
2
volatile-zeroed
ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS
DIRECT
SBE_SEEPROM_I2C_PORT
A 2-element array containing the I2C controller port number of the
primary (0) and secondary (1) SEEPROM devices containing SBE IPL code.
Provided by the Machine Readable Workbook
2
volatile-zeroed
ATTR_SBE_SEEPROM_I2C_PORT
DIRECT
PNOR_I2C_ADDRESS_BYTES
The number of address bytes required to address the PNOR memory device
via the pseudo-I2C (LPC, ECCAX) controller. This will vary by device
based on the device capacity, and must be either 0, 1, 2, 3 or 4.
This attribute will be set to 0 for chips with no PNOR attached
(PoreVe will never run on these chips).
Provided by the Machine Readable Workbook
4
non-volatile
ATTR_PNOR_I2C_ADDRESS_BYTES
DIRECT
SYNC_BETWEEN_STEPS
Attribute to enable targetting attribute sync when in istep mode.
1 = sync will occur following each substep when ipl'ing in single step mode
0 = sync will not be done after each step
volatile-zeroed
ATTR_SYNC_BETWEEN_STEPS
DIRECT
PROC_SELECT_BOOT_MASTER
Enumeration indicating which chip should be used as the PROC_SELECT_BOOT_MASTER
PRIMARY
1
SECONDARY
2
PROC_SELECT_BOOT_MASTER
Specifies which chip should be used as the boot master
Initialized by the platform.
PRIMARY - the primary master is used for the BOOT
SECONDARY - the alternate master is used for the BOOT
Platforms are expected to set this to PRIMARY in normal operation
1
volatile
ATTR_PROC_SELECT_BOOT_MASTER
DIRECT
PROC_SELECT_SEEPROM_IMAGE
Enumeration indicating which SEEPROM image should be used for the boot master
FIRST
1
SECOND
2
PROC_SELECT_SEEPROM_IMAGE
Specifies which SEEPROM image should be used for the boot master.
FIRST - the first image was selected
SECOND - the second image was selected
Platforms are expected to set this to FIRST in normal operation
1
volatile
ATTR_PROC_SELECT_SEEPROM_IMAGE
DIRECT
ENABLED_THREADS
Bitmask of threads to enable for each processor,
Zero means enable all architected threads
volatile-zeroed
MAX_PROC_CHIPS_PER_NODE
System attribute.
The max proc chips per node available in the system.
non-volatile
MAX_EXS_PER_PROC_CHIP
System attribute.
The max EX units per proc chip available in the system.
non-volatile
MAX_DIMMS_PER_MBA_PORT
System attribute.
The max DIMMs per MBA Port available in the system.
non-volatile
MAX_MBA_PORTS_PER_MBA
System attribute.
The max MBA ports per MBA available in the system.
non-volatile
MAX_MBAS_PER_MEMBUF_CHIP
System attribute.
The max MBAS per membuf available in the system.
non-volatile
MAX_CHIPLETS_PER_PROC
System attribute.
The max chiplets per proc available in the system.
non-volatile
MAX_MCS_PER_SYSTEM
System attribute.
The max MCS units available in the system.
non-volatile
DMI_REFCLOCK_SWIZZLE
Defines Murano/Venice FSI GP8 refclock enable field bit offset (0:7) associated with this MCS chip unit.
0
non-volatile
ATTR_DMI_REFCLOCK_SWIZZLE
DIRECT
EI_BUS_TX_MSBSWAP
Source: MRW: Downstream MSB Swap and Upstream MSB Swap
Usage: TX_MSBSWAP initfile setting for DMI and A buses
This attribute represents whether or not a single clock group bus such as DMI and A bus was wired by the board designer using a feature
called MSB Swap where lane 0 of the TX chip wires to lane n-1 on the RX chip where 'n' is the width of the bus. A basic description
of this capability is that the board designer can save layers on the board wiring by crossing the wiring between the two chips in
a prescribed manner. In a non-MSB Swapped bus Lane 0 on the TX chip wires to lane 0 on the RX chip, lane 1 to lane 1 and so on.
If a bus is MSB Swapped then lane 0 of the TX chip wires to lane 'n-1' of the RX chip, lane 1 to lane 'n-2', etc. Random or
arbitrary wiring of TX to RX lanes on different chips is NOT ALLOWED.
The Master Chip of two connected chips is defined as the chip with the smaller value of (100*Node + Pos).
The Slave Chip of two connected chips is defined as the chip with the larger value of (100*Node + Pos).
The Downstream direction is defined as the direction from the Master chip to the Slave chip.
The Upstream direction is defined as the direction from the Slave chip to the Master chip.
The Downstream TX_MSBSWAP from the MRW is a uint8 value. 0x01 means the Downstream bus is wired msb to lsb etc. and
0x00 means the bus is wired normally, msb to msb, lsb to lsb (lane0 to lane0).
The Upstream TX_MSBSWAP from the MRW is a uint8 value. 0x01 means the Upstream bus is wired msb to lsb etc. and
0x00 means the bus is wired normally, msb to msb, lsb to lsb (lane0 to lane0).
It is up to the platform code to set up each ATTR_EI_BUS_TX_MSBSWAP value for the correct target endpoints.
non-volatile
ATTR_EI_BUS_TX_MSBSWAP
DIRECT
MSS_FREQ_OVERRIDE
FOR LAB USE ONLY: Frequency override of this memory channel in MHz, comprising of up to three DIMMs. Set by config file or an attribute writing program. Consumed by mss_freq. The default of AUTO means mss_freq will find the best frequencies given the DIMMs plugged in and other rules. Otherwise, this is the system frequency.
firmware notes: Platforms should initialize this attribute to AUTO (0)
volatile-zeroed
ATTR_MSS_FREQ_OVERRIDE
DIRECT
MCBIST_PATTERN
Enables mcbist data pattern selection.
volatile-zeroed
ATTR_MCBIST_PATTERN
DIRECT
MCBIST_TEST_TYPE
Enables mcbist test type selection.
volatile-zeroed
ATTR_MCBIST_TEST_TYPE
DIRECT
MCBIST_PRINTING_DISABLE
MCBIST support for printing
volatile-zeroed
ATTR_MCBIST_PRINTING_DISABLE
DIRECT
MCBIST_DATA_ENABLE
MCBIST support for enabling data
volatile-zeroed
ATTR_MCBIST_DATA_ENABLE
DIRECT
MCBIST_USER_RANK
MCBIST support for rank selection
volatile-zeroed
ATTR_MCBIST_USER_RANK
DIRECT
MCBIST_USER_BANK
MCBIST support for bank selection
volatile-zeroed
ATTR_MCBIST_USER_BANK
DIRECT
SCHMOO_MULTIPLE_SETUP_CALL
MCBIST for multiple setup
volatile-zeroed
ATTR_SCHMOO_MULTIPLE_SETUP_CALL
DIRECT
MCBIST_ADDR_MODES
Can choose mcbist address mode for full,half or quarter addressing mode.
volatile-zeroed
ATTR_MCBIST_ADDR_MODES
DIRECT
MCBIST_RANK
Defines the rank for the Mcbist
volatile-zeroed
ATTR_MCBIST_RANK
DIRECT
MCBIST_START_ADDR
Defines the start address for the Mcbist address range
volatile-zeroed
ATTR_MCBIST_START_ADDR
DIRECT
MCBIST_END_ADDR
Defines the end address for the Mcbist address range
volatile-zeroed
ATTR_MCBIST_END_ADDR
DIRECT
MCBIST_ERROR_CAPTURE
Enables error capture; basically a flag.
volatile-zeroed
ATTR_MCBIST_ERROR_CAPTURE
DIRECT
MCBIST_MAX_TIMEOUT
Define mcbist Max timeout
volatile-zeroed
ATTR_MCBIST_MAX_TIMEOUT
DIRECT
MCBIST_PRINT_PORT
Enable which port prints are required.
volatile-zeroed
ATTR_MCBIST_PRINT_PORT
DIRECT
MCBIST_STOP_ON_ERROR
Flag to stop Mcbist on Error.
volatile-zeroed
ATTR_MCBIST_STOP_ON_ERROR
DIRECT
MCBIST_DATA_SEED
Define data seed for the random data pattern or test
volatile-zeroed
ATTR_MCBIST_DATA_SEED
DIRECT
MCBIST_ADDR_INTER
The address interleave map with user cases or deafult cases of BANK_RANK,RANK_BANK,BANK_ONLY,RANK_ONLYRANKS_DIMM0,RANKS_DIMM1,USER_PATTERN.
volatile-zeroed
ATTR_MCBIST_ADDR_INTER
DIRECT
MCBIST_ADDR_NUM_ROWS
User defined constraint for limiting number of rows for addressing.
volatile-zeroed
ATTR_MCBIST_ADDR_NUM_ROWS
DIRECT
MCBIST_ADDR_NUM_COLS
User defined constraint for limiting number of columns for addressing.
volatile-zeroed
ATTR_MCBIST_ADDR_NUM_COLS
DIRECT
MCBIST_ADDR_RANK
User defined constraint for limiting number of ranks for addressing.
volatile-zeroed
ATTR_MCBIST_ADDR_RANK
DIRECT
MCBIST_ADDR_BANK
User defined constraint for limiting number of banks for addressing.
volatile-zeroed
ATTR_MCBIST_ADDR_BANK
DIRECT
MCBIST_ADDR_SLAVE_RANK_ON
If slave ranks exists;Restrict usage or enable addressing on them as well.
volatile-zeroed
ATTR_MCBIST_ADDR_SLAVE_RANK_ON
DIRECT
MCBIST_ADDR_STR_MAP
To Define custom addressing map ; Input by user.
volatile-zeroed
ATTR_MCBIST_ADDR_STR_MAP
DIRECT
MCBIST_ADDR_RAND
Flag for Addressing to go sequential manner or random.
volatile-zeroed
ATTR_MCBIST_ADDR_RAND
DIRECT
PROC_PCIE_REFCLOCK_ENABLE
PCIE refclock enable valid mask
creator: platform
consumer: proc_pcie_scominit
firmware notes:
Bit mask defining state of refclock drive enables
bit0=PCI0, bit1=PCI1, bit2=PCI2
0xE0
non-volatile
ATTR_PROC_PCIE_REFCLOCK_ENABLE
DIRECT
PROC_EX_FUNC_L3_DELTA_DATA
Delta/flip data for ex_func_l3 ring containing winkle customization settings for PBIEX programming.
Relies on PBIEX settings in reference image containing scan flush default values.
High-order 16 bits provide byte address offset for ring modification.
Low-order 8 bits provide override data for addressed byte.
Entries will be processed from index 0 to 63 (byte address of 0xFFFFFF should be used to signify last entry to process).
creator: platform
firmware notes:
0
64
non-volatile
ATTR_PROC_EX_FUNC_L3_DELTA_DATA
DIRECT
PROC_EX_FUNC_L3_LENGTH
Length of ex_func_l3 ring in bits
creator: platform
firmware notes:
non-volatile
ATTR_PROC_EX_FUNC_L3_LENGTH
DIRECT
PROC_PBIEX_ASYNC_SEL
Enumeration indicating which _PBIEX_ASYNC_SEL should be use
SEL0
0
SEL1
1
SEL2
2
PROC_PBIEX_ASYNC_SEL
Selector for ATTR_PROC_EX_FUNC_L3_DELTA_DATA value to be returned by platform.
creator: proc_build_smp
firmware notes:
volatile-zeroed
ATTR_PROC_PBIEX_ASYNC_SEL
DIRECT
PROC_DCM_INSTALLED
PROC_CHIP Attribute
If true, the chip is installed on a Dual Chip Module
Provided by the Machine Readable Workbook
non-volatile
ATTR_PROC_DCM_INSTALLED
DIRECT
X_EREPAIR_THRESHOLD_FIELD
This attribute represents the eRepair threshold value of X-Bus used
in the field.
creator: platform (generated based on MRW data)
See defintion in erepair_thresholds.xml for more information.
non-volatile
ATTR_X_EREPAIR_THRESHOLD_FIELD
DIRECT
A_EREPAIR_THRESHOLD_FIELD
This attribute represents the eRepair threshold value of A-Bus used
in the field.
creator: platform (generated based on MRW data)
See defintion in erepair_thresholds.xml for more information.
non-volatile
ATTR_A_EREPAIR_THRESHOLD_FIELD
DIRECT
DMI_EREPAIR_THRESHOLD_FIELD
This attribute represents the eRepair threshold value of DMI-Bus used
in the field.
creator: platform (generated based on MRW data)
See defintion in erepair_thresholds.xml for more information.
non-volatile
ATTR_DMI_EREPAIR_THRESHOLD_FIELD
DIRECT
X_EREPAIR_THRESHOLD_MNFG
This attribute represents the eRepair threshold value of X-Bus used
by Manufacturing.
creator: platform (generated based on MRW data)
See defintion in erepair_thresholds.xml for more information.
non-volatile
ATTR_X_EREPAIR_THRESHOLD_MNFG
DIRECT
A_EREPAIR_THRESHOLD_MNFG
This attribute represents the eRepair threshold value of A-Bus used
by Manufacturing.
creator: platform (generated based on MRW data)
See defintion in erepair_thresholds.xml for more information.
non-volatile
ATTR_A_EREPAIR_THRESHOLD_MNFG
DIRECT
DMI_EREPAIR_THRESHOLD_MNFG
This attribute represents the eRepair threshold value of DMI-Bus used
by Manufacturing.
creator: platform (generated based on MRW data)
See defintion in erepair_thresholds.xml for more information.
non-volatile
ATTR_DMI_EREPAIR_THRESHOLD_MNFG
DIRECT
MEMB_TP_BNDY_PLL_SCAN_SELECT
Scan select for ring image for Centaur tp_bndy_pll ring
creator: platform
firmware notes:
0x00100008
non-volatile
ATTR_MEMB_TP_BNDY_PLL_SCAN_SELECT
DIRECT
MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA
Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_mba
non-volatile
ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA
DIRECT
MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR
Machine Readable Workbook safe mode throttle value for denominator cfg_nm_m
non-volatile
ATTR_MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR
DIRECT
MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP
Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_chip
non-volatile
ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP
DIRECT
MRW_THERMAL_MEMORY_POWER_LIMIT
Machine Readable Workbook Thermal Memory Power Limit
non-volatile
ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT
DIRECT
EFF_DRAM_LPASR
Low Power Auto Self-Refresh. This is for DDR4 MRS2. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_DRAM_LPASR
DIRECT
EFF_MPR_PAGE
MPR Page Selection This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_MPR_PAGE
DIRECT
EFF_GEARDOWN_MODE
Gear Down Mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_GEARDOWN_MODE
DIRECT
EFF_PER_DRAM_ACCESS
Per DRAM accessibility. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_PER_DRAM_ACCESS
DIRECT
EFF_TEMP_READOUT
Temperature sensor readout. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_TEMP_READOUT
DIRECT
EFF_FINE_REFRESH_MODE
Fine refresh mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_FINE_REFRESH_MODE
DIRECT
EFF_CRC_WR_LATENCY
write latency for CRC and DM. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_CRC_WR_LATENCY
DIRECT
EFF_MPR_RD_FORMAT
MPR READ FORMAT. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_MPR_RD_FORMAT
DIRECT
EFF_MAX_POWERDOWN_MODE
Max Power down mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_MAX_POWERDOWN_MODE
DIRECT
EFF_TEMP_REF_RANGE
Temp ref range. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_TEMP_REF_RANGE
DIRECT
EFF_TEMP_REF_MODE
Temp controlled ref mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_TEMP_REF_MODE
DIRECT
EFF_INT_VREF_MON
Internal Vref Monitor.. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_INT_VREF_MON
DIRECT
EFF_CS_CMD_LATENCY
CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_CS_CMD_LATENCY
DIRECT
EFF_SELF_REF_ABORT
Self Refresh Abort. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_SELF_REF_ABORT
DIRECT
EFF_RD_PREAMBLE_TRAIN
Read Pre amble Training Mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_RD_PREAMBLE_TRAIN
DIRECT
EFF_RD_PREAMBLE
Read Pre amble. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_RD_PREAMBLE
DIRECT
EFF_WR_PREAMBLE
Write Pre amble. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_WR_PREAMBLE
DIRECT
EFF_CA_PARITY_LATENCY
C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_CA_PARITY_LATENCY
DIRECT
EFF_CRC_ERROR_CLEAR
CRC Error Clear. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_CRC_ERROR_CLEAR
DIRECT
EFF_CA_PARITY_ERROR_STATUS
C/A Parity Error Status. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_CA_PARITY_ERROR_STATUS
DIRECT
EFF_ODT_INPUT_BUFF
ODT Input Buffer during power down. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_ODT_INPUT_BUFF
DIRECT
EFF_RTT_PARK
RTT_Park value. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
2, 2, 4
volatile-zeroed
ATTR_EFF_RTT_PARK
DIRECT
EFF_CA_PARITY
CA Parity Persistance Error. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_CA_PARITY
DIRECT
EFF_DATA_MASK
Data Mask. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_DATA_MASK
DIRECT
EFF_WRITE_DBI
Write DBI. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_WRITE_DBI
DIRECT
EFF_READ_DBI
Read DBI. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_READ_DBI
DIRECT
VREF_DQ_TRAIN_VALUE
vrefdq_train value. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
2,2,4
volatile-zeroed
ATTR_VREF_DQ_TRAIN_VALUE
DIRECT
VREF_DQ_TRAIN_RANGE
vrefdq_train range. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
2,2,4
volatile-zeroed
ATTR_VREF_DQ_TRAIN_RANGE
DIRECT
VREF_DQ_TRAIN_ENABLE
vrefdq_train enable. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
2,2,4
volatile-zeroed
ATTR_VREF_DQ_TRAIN_ENABLE
DIRECT
TCCD_L
tccd_l. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_TCCD_L
DIRECT
EFF_WRITE_CRC
Write CRC control for DDR4. Set in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
volatile-zeroed
ATTR_EFF_WRITE_CRC
DIRECT
EFF_DRAM_2N_MODE_ENABLED
Describes if this MBA is in 2N address mode. The DIMM attributes associated with this MBA describes if this mode is needed for SI. The MR Keyword of the VPD gives and indication of the value needed. Set by eff_config and consumed in the mba_def.initfile.
volatile-zeroed
ATTR_EFF_DRAM_2N_MODE_ENABLED
DIRECT
MSS_DIMM_POWER_TEST_REV
The power test revision number that is saved when data is saved on an ISDIMM. If the power test changes, then a difference indicates that the power test needs to be rerun. This attribute needs to stick around between IPLs
volatile-zeroed
ATTR_MSS_DIMM_POWER_TEST_REV
DIRECT
FRU_ID
FRU ID attribute for chip class
0
non-volatile
PLCK_IPL_ATTR_OVERRIDES_EXIST
Set to 1 by HWSV to indicate that attribute overrides exist in a PLCK IPL
(not an IPL by steps). This is read by Hostboot to determine if it needs
to request the attribute overrides from HWSV before starting its IPL.
0x00
non-volatile
DUMMY_PERSISTENCY
Cached value to test persistency
0
non-volatile
ATTR_DUMMY_PERSISTENCY
DIRECT
IS_INTER_ENCLOSURE_BUS
Indicate an inter-enclosure bus at this endpoint target.
0 = No, 1 = Yes
0
volatile
PEER_PATH
Entity path of the peer target of an Abus
EntityPath
non-volatile
PROC_HTM_BAR_SIZE
Desired HTM trace memory size value
creator: platform
firmware notes:
set by platform to request size of per-chip area reserved
for HTM trace memory
0
non-volatile
ATTR_PROC_HTM_BAR_SIZE
DIRECT
PROC_OCC_SANDBOX_SIZE
Desired size of OCC sandbox memory region
creator: platform
firmware notes:
set by platform to request size of per-chip area reserved
for OCC sandbox function
0
non-volatile
ATTR_PROC_OCC_SANDBOX_SIZE
DIRECT
PROC_HTM_BAR_BASE_ADDR
HTM trace memory base address allocated
volatile-zeroed
ATTR_PROC_HTM_BAR_BASE_ADDR
DIRECT
PROC_OCC_SANDBOX_BASE_ADDR
OCC sandbox base address allocated
volatile-zeroed
ATTR_PROC_OCC_SANDBOX_BASE_ADDR
DIRECT
MEM_MIRROR_PLACEMENT_POLICY
Define placement policy/scheme for non-mirrored/mirrored memory
layout
creator: platform
consumer: opt_memmap
firmware notes:
NORMAL = non-mirrored start: 0, mirrored start: 512TB
FLIPPED = mirrored start: 0, non-mirrored start: 512TB
SELECTIVE = non-mirrored/mirrored start (interleaved): 0
0
non-volatile
ATTR_MEM_MIRROR_PLACEMENT_POLICY
DIRECT
PROC_AS_MMIO_BAR_BASE_ADDR
AS MMIO BAR base address value
creator: platform
consumer: proc_setup_bars
firmware notes:
64-bit address representing BAR RA
NOTE: BAR register covers RA 14:51
0
non-volatile
ATTR_PROC_AS_MMIO_BAR_BASE_ADDR
DIRECT
PROC_AS_MMIO_BAR_ENABLE
AS MMIO BAR enable
creator: platform
consumer: proc_setup_bars
firmware notes: none
0
non-volatile
ATTR_PROC_AS_MMIO_BAR_ENABLE
DIRECT
PROC_AS_MMIO_BAR_SIZE
AS MMIO BAR size value
creator: platform
consumer: proc_setup_bars
firmware notes: none
0x0000000000200000
non-volatile
ATTR_PROC_AS_MMIO_BAR_SIZE
DIRECT
RISK_LEVEL
Defines risk level to consider for initialization values applied during IPL.
Risk level 0 should contain solutions for all known errata, and may sacrifice performance to avoid data integrity issue/error checking cases.
Risk level 0x100 may introduce data integrity/error scenarios to provide full performance or visibility to state space/coverage behind known issues.
volatile-zeroed
ATTR_RISK_LEVEL
DIRECT
MSS_FREQ_BIAS_PERCENTAGE
Percentage to increase/decrease MEM frequency. two's complement number.
Measured in 100's. So the value of 100 is one percent increase.
This frequency change comes from changing multipliers and dividers to
get the desired frequency. The supported frequencies come from
Tim Diemoz.
Creator: platform set this to 0. Users can set this to a valid value.
volatile-zeroed
ATTR_MSS_FREQ_BIAS_PERCENTAGE
DIRECT
CDIMM_SENSOR_MAP_PRIMARY
Custom DIMM Sensor Map for Primary I2C Port (1 byte of data):
0x00 No sensors attached
0x01 DIMM sensor 0 attached
0x02 DIMM sensor 1 attached
0x04 DIMM sensor 2 attached
0x08 DIMM sensor 3 attached
0x10 DIMM sensor 4 attached
0x20 DIMM sensor 5 attached
0x40 DIMM sensor 6 attached
0x80 DIMM sensor 7 attached
Comes from the VPD MW Keyword
0
non-volatile
ATTR_CDIMM_SENSOR_MAP_PRIMARY
DIRECT
CDIMM_SENSOR_MAP_SECONDARY
Custom DIMM Sensor Map for Secondary I2C Port (1 byte of data):
0x00 No sensors attached
0x01 DIMM sensor 0 attached
0x02 DIMM sensor 1 attached
0x04 DIMM sensor 2 attached
0x08 DIMM sensor 3 attached
0x10 DIMM sensor 4 attached
0x20 DIMM sensor 5 attached
0x40 DIMM sensor 6 attached
0x80 DIMM sensor 7 attached
Comes from the VPD MW Keyword
0
non-volatile
ATTR_CDIMM_SENSOR_MAP_SECONDARY
DIRECT
EFF_DRAM_ADDRESS_MIRRORING
Address mirroring on the DIMM by rank, up to 4 ranks.
0x08 means rank 0 is mirrored
0x04 means rank 1 is mirrored
0x02 means rank 2 is mirrored
0x01 means rank 3 is mirrored
Comes from EFF config reading the VPD_DRAM_ADDRESS_MIRRORING from the
AM keyword of the VPD.
2,2
volatile-zeroed
ATTR_EFF_DRAM_ADDRESS_MIRRORING
DIRECT
MSS_BLUEWATERFALL_BROKEN
Set by the platform depending on DD1.0X vs DD1.03 or newer. If true,
then draminit_train will modify dqs_clk_ps and gate to work around the
issue. Set in get ecid which determines if we are at 1.03
volatile-zeroed
ATTR_MSS_BLUEWATERFALL_BROKEN
DIRECT
CDM_POLICIES
Cec Degraded Mode Policy flags
Use the CDM_POLICIES enum to decode.
If the appropriate bit is 1 then the policy mode is enabled,
and those type of Guard records are disabled.
0x00
non-volatile
CDM_POLICIES
Enumeration of CDM_POLICIES flags
Functional_Guard policy:
Used in Field or development to prevent and disable the following:
. Storing or creation of new Guard records from diagnostics or other
faults through error logs with the error_type of Functional.
. Using an already stored System Guard record with error_type of
Functional from deconfiguring resources.
FUNCTIONAL_DISABLED
0x01
MFG_Guard policy:
Used in MFG only to prevent and disable the following:
. Storing or creation of new Guard records from Diagnostic or other
faults through error logs. This is all domains, CEC
processor/memory, VPD, FSP, etc.
. Storing or creation of Manual Guard record from user.
NOTE: this does not stop FCO.
. Using an already stored System or Manual Guard record from
deconfiguring resources. This is all domains, CEC
processor/memory, VPD, FSP, etc.
MANUFACTURING_DISABLED
0x02
Predictive_Guard policy:
Used in Field or development to prevent and disable the following:
. Storing or creation of new Guard records from diagnostics or other
faults through error logs with the error_type of Predictive.
. Using an already stored System Guard record with error_type of
Predictive from deconfiguring resources.
PREDICTIVE_DISABLED
0x04
FIELD_CORE_OVERRIDE
Field Core Override (FCO) is the override value for the
number of functional cores allowed on the system.
FCO is used when customers order a system with N cores but they only want
to enable less than N cores to lower software license costs. A field in the
anchor VPD is set by manufacturing to specify the maximum number of cores
to enable. The number is maintained, even if some cores are garded out due
to error.
A value of 0 means all cores allowed;
0
non-volatile
HOSTSVC_PLID
Value of the next PLID that host service should send
0
non-volatile
RUN_MAX_MEM_PATTERNS
Policy indicating whether to perform the maximum amount of memory
pattern testing possible or not.
Set to 0x01 to perform the maximum amount of memory pattern testing
possible.
Set to 0x00 to perform the default amount of memory pattern testing.
0
non-volatile
EFF_RLO
Gives the RLO value to use for this port. This comes from the MR Keyword of the VPD gives and indication of the value. It will be writable until it comes from VPD. The value is a positive integer number.
0
2
volatile-zeroed
ATTR_EFF_RLO
DIRECT
EFF_WLO
Read Latency Offset value that is used in the phy. This value comes from the MR keyword of the VPD
0
2
volatile-zeroed
ATTR_EFF_WLO
DIRECT
EFF_GPO
Global Phy Offset value that is used in setting up the phy. This value comes from the MR keyword of the VPD
0
2
volatile-zeroed
ATTR_EFF_GPO
DIRECT
EFF_CKE_PRI_MAP
Contains the CKE MAP for the DIMM being plugged in. It comes from the MT keyword but is not on a port basis --- meaning this Attribute may be split: with 16 bits associated with port A data and 16 bits with B. This value goes directly into the MBA01 Rank-to-primary-CKE mapping table register bits 0:31 (MBA01_MBAREF1Q) register. This attribute is writeable until it comes from the VPD
0
volatile-zeroed
ATTR_EFF_CKE_PRI_MAP
DIRECT
EFF_CKE_PWR_MAP
Contains the CKE Power Domain mapping tables for the DIMM being plugged in. It comes from the MT keyword but is not on a port basis --- meaning this Attribute may be split: with 32 bits associated with port A data and 32 bits with B. This value goes directly into the MBA01 Rank-to-CKE power domain mapping table bits 0:33 (MBA01_MBARPC1Q) register. This attribute is writeable until it comes from the VPD
0
volatile-zeroed
ATTR_EFF_CKE_PWR_MAP
DIRECT
EFF_RDTAG
Read Tag value that is used in setting up the phy. It is expected that this value will come from the VPD
0
volatile-zeroed
ATTR_EFF_RDTAG
DIRECT
EFF_TSYS_ADR
TSYS for all address blocks in the MBA pair. This value comes from the MR keyword of the VPD
0
volatile-zeroed
ATTR_EFF_TSYS_ADR
DIRECT
EFF_TSYS_DP18
TSYS for all DP18 blocks in the MBA pair. This value comes from the MR keyword of the VPD
0
volatile-zeroed
ATTR_EFF_TSYS_DP18
DIRECT
EFF_DQ_WR_OFFSET
DQ write offset value that is used in setting up the phy's phase rotators before WR_LVL, 0x40 is HW Default. It is expected that this value will come from the VPD
0
2
volatile-zeroed
ATTR_EFF_DQ_WR_OFFSET
DIRECT
EFF_BUFFER_LATENCY
Additional buffer latency in the case of RDIMMs and LRDIMMs. It is expected that this value will come from the VPD
0
volatile-zeroed
ATTR_EFF_BUFFER_LATENCY
DIRECT
LRDIMM_MR12_REG
LRDIMM MR1,2 register.
DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks. Eff config should set this up.
0
2,2
volatile-zeroed
ATTR_LRDIMM_MR12_REG
DIRECT
LRDIMM_ADDITIONAL_CNTL_WORDS
LRDIMM additional RCD control words as set by DIMM SPD:
F[3,4]RC10, F[3,4]RC11, F[5,6]RC10, F[5,6]RC11, F[7,8]RC10, F[7,8]RC11, F[9,10]RC10, F[9,10]RC11,
F[1]RC8, F[3]RC9, F[3]RC8, F[1]RC11, F[1]RC12, F[1]RC13, F[1]RC14, F[1]RC15.
Eff config should set this up
0
2,2
volatile-zeroed
ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS
DIRECT
LRDIMM_RANK_MULT_MODE
LRDIMM rank multiplication mode.
Will be set at an MBA level with one policy to be used
0
volatile-zeroed
ATTR_LRDIMM_RANK_MULT_MODE
DIRECT
PM_SPWUP_IGNORE_XSTOP_FLAG
Flag storage to have the Special Wakeup procedure ignore a checkstop condition.
volatile-zeroed
ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG
DIRECT
CPM_INFLECTION_POINTS
Structure to communicate the CPM inflection points from the CPM code to the Pstate code
Datablock consisting of:
8 Inflection Point frequency entries (binary in ATTR_FREQ_PROC_REFCLOCK_KHZ / ATTR_PROC_DPLL_DIVIDER units)
1 ValidRanges entry - the number of valid inflection points in the previous locations (unit origin)
1 pMax frequency entry - the maximum allowed boosted frequency (binary in ATTR_FREQ_PROC_REFCLOCK_KHZ / ATTR_DPLL_DIVIDER units)
6 spare entries
Producer: p8_cpm_cal_load
Consumer: p8_pstate_datablock
0
16
volatile-zeroed
ATTR_CPM_INFLECTION_POINTS
DIRECT
LAB_USE_JTAG_MODE
This attribute controls how the procedures operate in JTAG mode under an environment called cronus flex. For normal operation, this attribute should be set to FALSE. Platforms should initialize this attribute to FALSE.
0
non-volatile
ATTR_LAB_USE_JTAG_MODE
DIRECT
MSS_CONTROL_SWITCH
This attribute enables control switches in the memory code. This is a one hot vector: Bit 7 controls the Bad Bit Mask function in draminit_training. The platform should initialize this to BBM_ON except if ATTR_LAB_USE_JTAG_MODE == TRUE, then the platform should set this attribute to BBM_ OFF.
0
volatile-zeroed
ATTR_MSS_CONTROL_SWITCH
DIRECT
MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_MBA
runtime memory throttle values adjusted by the dimm power test
DIMM power test memory throttles for cfg_nm_n_per_mba
0
non-volatile
ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_MBA
DIRECT
MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_CHIP
runtime memory throttle values adjusted by the dimm power test
DIMM power test memory throttles for cfg_nm_n_per_chip
0
non-volatile
ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_CHIP
DIRECT
MSS_DIMM_POWER_TEST_MEM_THROTTLE_DENOMINATOR
runtime memory throttle values adjusted by the dimm power test
DIMM power test memory throttles for cfg_nm_m
0
non-volatile
ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_DENOMINATOR
DIRECT
MSS_THROTTLE_CONTROL_RAS_WEIGHT
RAS weight to use for memory throttle control
volatile-zeroed
ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT
DIRECT
MSS_THROTTLE_CONTROL_CAS_WEIGHT
CAS weight to use for memory throttle control
volatile-zeroed
ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT
DIRECT
PROC_MIRROR_BASES_ACK
Mirrored memory base addresses
creator: mss_setup_bars
consumer: consumer: opt_mem_map
Mem opt map uses this for the bases of the mirror ranges.
(max number based on Venice design)
4
volatile-zeroed
ATTR_PROC_MIRROR_BASES_ACK
DIRECT
PROC_MIRROR_SIZES_ACK
Size of mirrored memory region up to a power of 2
creator: mss_setup_bars
consumer: opt_mem_map
Mem opt map uses this to stack mirror ranges. The real amount of memory behind the mirror group maybe less than the number reported here if there are memory holes
4
volatile-zeroed
ATTR_PROC_MIRROR_SIZES_ACK
DIRECT
PROC_MEM_BASES_ACK
Non-mirrored memory base addresses
creator: mss_setup_bars
consumer: opt_mem_map
Mem opt map uses this for the bases of the non-mirror ranges.
(max number based on Venice design)
8
volatile-zeroed
ATTR_PROC_MEM_BASES_ACK
DIRECT
PROC_MEM_SIZES_ACK
Size of non-mirrored memory regions up to a power of 2
creator: mss_setup_bars
consumer: opt_mem_map
Mem opt map uses this to stack mirror ranges. The real amount of memory behind the mirror group maybe less than the number reported here if there are memory holes
8
volatile-zeroed
ATTR_PROC_MEM_SIZES_ACK
DIRECT
MCBIST_RANDOM_SEED_VALUE
Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.
0
volatile-zeroed
ATTR_MCBIST_RANDOM_SEED_VALUE
DIRECT
MCBIST_RANDOM_SEED_TYPE
Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.
0
volatile-zeroed
ATTR_MCBIST_RANDOM_SEED_TYPE
DIRECT
L4_BANK_DELETE_VPD
L4 Bank Delete settings in VPD.
Denotes what banks have been deleted from the L4.
Data will be pulled from CDIMM VPD if CDIMM present.
Data will be pulled from backplane VPD if IS DIMMs present.
non-volatile
ATTR_L4_BANK_DELETE_VPD
DIRECT
PROC_BOOT_VOLTAGE_VID
Proc Boot Voltage
0
non-volatile
ATTR_PROC_BOOT_VOLTAGE_VID
DIRECT
DISABLE_I2C_ACCESS
Set to skip physical access to i2c interface in SBE execution.
Consumed by SBE hooks to permit skipping of selected code when
running on a test platform (i.e., wafer) which does not have a physical
SEEPROM connected.
0
non-volatile
ATTR_DISABLE_I2C_ACCESS
DIRECT
PROC_REFCLOCK_RCVR_TERM
Defines system specific value of processor refclock receiver termination (FSI GP4 bits 8:9)
0
non-volatile
ATTR_PROC_REFCLOCK_RCVR_TERM
DIRECT
PCI_REFCLOCK_RCVR_TERM
Defines system specific value of PCI refclock receiver termination (FSI GP4 bits 10:11)
0
non-volatile
ATTR_PCI_REFCLOCK_RCVR_TERM
DIRECT
MEM_FILTER_PLL_SOURCE
Defines source of MEM filter PLL input (FSI GP4 bit 23)
0
non-volatile
ATTR_MEM_FILTER_PLL_SOURCE
DIRECT
DMI_DFE_OVERRIDE
Defines where to apply DMI bus DFE override settings for HW244323.
0
non-volatile
ATTR_DMI_DFE_OVERRIDE
DIRECT
PROC_VRM_VOFFSET_VDD
Offset voltage (binary in microvolts) to apply to the VDD VRM distribution to
the processor module. This value is applied to each processor instance.
Producer: Machine Readable Workbook (via the power subsystem design per system)
Consumer: p8_build_gpstate_table.C
non-volatile
ATTR_PROC_VRM_VOFFSET_VDD
DIRECT
PROC_VRM_VOFFSET_VCS
Offset voltage (binary in microvolts) to apply to the VCS VRM distribution to
the processor module. This value is applied to each processor instance.
Producer: Machine Readable Workbook (via the power subsystem design per system)
Consumer: p8_build_gpstate_table.C
non-volatile
ATTR_PROC_VRM_VOFFSET_VCS
DIRECT
CPM_TURBO_BOOST_PERCENT
Percent of Boost Above Turbo for CPMs - (binary in 0.1 percent steps)
Used in generating extra Pstate tables beyond those that would result from
#V data.
Producer: DEF file as this is CCIN based
Consumers: p8_build_gpstate_table.C, p8_cpm_cal_load.C
Platform default: 0
non-volatile
ATTR_CPM_TURBO_BOOST_PERCENT
DIRECT
PROC_R_LOADLINE_VDD
Impedance (binary microOhms) of the load line from a processor VDD VRM to the
Processor Module pins. This value is applied to each processor instance.
Consumers: p8_build_gpstate_table.C
Provided by the Machine Readable Workbook (via the power subsystem design
per system)
non-volatile
ATTR_PROC_R_LOADLINE_VDD
DIRECT
PROC_R_LOADLINE_VCS
Impedance (binary microOhms) of the load line from a processor VCS VRM to the
Processor Module pins. This value is applied to each processor instance.
Producer: Machine Readable Workbook (via the power subsystem design per system)
Consumer: p8_build_gpstate_table.C
non-volatile
ATTR_PROC_R_LOADLINE_VCS
DIRECT
PROC_R_DISTLOSS_VDD
Impedance (binary in microOhms) of the VDD distribution loss sense point
to the circuit. This value is applied to each processor instance.
Producer: Machine Readable Workbook (via the power subsystem design per system)
Consumer: p8_build_gpstate_table.C
non-volatile
ATTR_PROC_R_DISTLOSS_VDD
DIRECT
PROC_R_DISTLOSS_VCS
Impedance (binary in microOhms) of the VCS distribution loss sense point
to the circuit. This value is applied to each processor instance.
Producer: Machine Readable Workbook (via the power subsystem design per system)
Consumer: p8_build_gpstate_table.C
non-volatile
ATTR_PROC_R_DISTLOSS_VCS
DIRECT
FREQ_EXT_BIAS_UP
Frequency Bias - % of bias upward (binary in 0.5 percent steps) in generating
Pstate tables. Either this or FREQ_EXT_BIAS_DOWN can have non-zero value
concurrently due to the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
volatile-zeroed
ATTR_FREQ_EXT_BIAS_UP
DIRECT
FREQ_EXT_BIAS_DOWN
Frequency Bias - % of bias downward (binary in 0.5 percent steps) in generating
Pstate tables. Either this or FREQ_EXT_BIAS_UP can have non-zero value
concurrently due to the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
volatile-zeroed
ATTR_FREQ_EXT_BIAS_DOWN
DIRECT
VOLTAGE_EXT_VDD_BIAS_UP
External VDD Voltage Bias - % of bias upward (binary in 0.5 percent steps) that
is applied to each VPD point in generating the Global Pstate tables. Either
this or ATTR_VOLTAGE_EXT_VDD_BIAS_DOWN can have non-zero value concurrently due to
the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
volatile-zeroed
ATTR_VOLTAGE_EXT_VDD_BIAS_UP
DIRECT
VOLTAGE_EXT_VDD_BIAS_DOWN
External VDD Voltage Bias - % of bias downward (binary in 0.5 percent steps) that
is applied to each VPD point in generating the Global Pstate tables. Either
this or ATTR_VOLTAGE_EXT_VDD_BIAS_UP can have non-zero value concurrently due to
the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
volatile-zeroed
ATTR_VOLTAGE_EXT_VDD_BIAS_DOWN
DIRECT
VOLTAGE_EXT_VCS_BIAS_UP
External VCS Voltage Bias - % of bias upward (binary in 0.5 percent steps) that
is applied to each VPD point in generating the Global Pstate tables. Either
this or ATTR_VOLTAGE_EXT_VCS_BIAS_DOWN can have non-zero value concurrently due to
the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
volatile-zeroed
ATTR_VOLTAGE_EXT_VCS_BIAS_UP
DIRECT
VOLTAGE_EXT_VCS_BIAS_DOWN
External VCS Voltage Bias - % of bias downward (binary in 0.5 percent steps) that
is applied to each VPD point in generating the Global Pstate tables. Either
this or ATTR_VOLTAGE_EXT_VCS_BIAS_UP can have non-zero value concurrently due to
the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
volatile-zeroed
ATTR_VOLTAGE_EXT_VCS_BIAS_DOWN
DIRECT
VOLTAGE_INT_VDD_BIAS_UP
Internal VDD Voltage Bias - % of bias upward (binary in 0.5 percent steps) that
is applied to the Local Pstate Table voltage entries based on the Global Pstate Table
built *after* the ATTR_VOLTAGE_EXT_VDD_BIAS_UP/ATTR_VOLTAGE_EXT_VDD_BIAS_DOWN bias
have been applied. Either this or ATTR_VOLTAGE_INT_VDD_BIAS_DOWN can have non-zero value
concurrently due to the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
volatile-zeroed
ATTR_VOLTAGE_INT_VDD_BIAS_UP
DIRECT
VOLTAGE_INT_VDD_BIAS_DOWN
Internal VDD Voltage Bias - % of bias downward (binary in 0.5 percent steps) that
is applied to the Local Pstate Table voltage entries based on the Global Pstate Table
built *after* the ATTR_VOLTAGE_EXT_VDD_BIAS_UP/ATTR_VOLTAGE_EXT_VDD_BIAS_DOWN bias
have been applied. Either this or ATTR_VOLTAGE_INT_VDD_BIAS_UP can have non-zero value
concurrently due to the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
volatile-zeroed
ATTR_VOLTAGE_INT_VDD_BIAS_DOWN
DIRECT
VOLTAGE_INT_VCS_BIAS_UP
Internal VCS Voltage Bias - % of bias upward (binary in 0.5 percent steps) that
is applied to the Local Pstate Table voltage entries based on the Global Pstate Table
built *after* the ATTR_VOLTAGE_EXT_VCS_BIAS_UP/ATTR_VOLTAGE_EXT_VCS_BIAS_DOWN bias
have been applied. Either this or ATTR_VOLTAGE_INT_VCS_BIAS_DOWN can have non-zero value
concurrently due to the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
volatile-zeroed
ATTR_VOLTAGE_INT_VCS_BIAS_UP
DIRECT
VOLTAGE_INT_VCS_BIAS_DOWN
Internal VCS Voltage Bias - % of bias downward (binary in 0.5 percent steps) that
is applied to the Local Pstate Table voltage entries based on the Global Pstate Table
built *after* the ATTR_VOLTAGE_EXT_VCS_BIAS_UP/ATTR_VOLTAGE_EXT_VCS_BIAS_DOWN bias
have been applied. Either this or ATTR_VOLTAGE_INT_VCS_BIAS_UP can have non-zero value
concurrently due to the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
volatile-zeroed
ATTR_VOLTAGE_INT_VCS_BIAS_DOWN
DIRECT
PM_UNDERVOLTING_FRQ_MINIMUM
Override for Minimum frequency for which undervolting is allowed.
If value = 0, the value of VPD CPMin data point is passed to OCC FW via
Pstate SuperStructure.
If value != 0, this value will be passed to OCC FW via Pstate SuperStructure
as the floor frequency for enabled CPMs.
Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value.
Consumer: OCC FW; OCC Lab Tools
Provided by the Machine Readable Workbook.
non-volatile
ATTR_PM_UNDERVOLTING_FRQ_MINIMUM
DIRECT
PM_UNDERVOLTING_FREQ_MAXIMUM
Override for Maximum frequency for which undervolting is allowed.
If value = 0, the value of VPD Turbo data point is passed to OCC FW via
Pstate SuperStructure.
If value != 0, this value will be passed to OCC FW via Pstate SuperStructure
as the ceiling frequency for enabled CPMs.
Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value.
Consumer: OCC FW; OCC Lab Tools
Provided by the Machine Readable Workbook.
non-volatile
ATTR_PM_UNDERVOLTING_FREQ_MAXIMUM
DIRECT
PM_WINKLE_ENTRY
Setting depends on di/dt charateristics of the system.
Set Assisted if power off serialization is needed and WINKLE_TYPE=Fast;
Set to Hardware if the system can handle the unrelated powering off between cores.
Hardware setting decreases entry latency
Producer: MRWB
Consumer: p8_poreslw_init.C
volatile-zeroed
ATTR_PM_WINKLE_ENTRY
DIRECT
PM_WINKLE_EXIT
Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_WINKLE_TYPE.
Set to Assisted if power on serialization is needed and WINKLE_TYPE=Fast; Set to Hardware if the system
can handle the unrelated powering off between cores. Hardware setting decreases entry latency.
Must be set to Assisted if ATTR_PM_WINKLE_TYPE=Deep as this necessary for restore.
Setting to Hardware is a test mode for Fast only.
Producer: MRWB
Consumer: p8_poreslw_init.C
volatile-zeroed
ATTR_PM_WINKLE_EXIT
DIRECT
PROC_MASTER_TYPE
Enumeration indicating the role of proc as master/alt_master/not_master
ACTING_MASTER
0
MASTER_CANDIDATE
1
NOT_MASTER
2
NOT_MASTER
PROC_MASTER_TYPE
Type of Master, ACTING_MASTER or MASTER_CANDIDATE or
NOT_MASTER
PROC_MASTER_TYPE
non-volatile