Hierarchical path to the target with respect to logical affinity
AFFINITY_PATH
EntityPath
non-volatile
ALL_MCS_IN_INTERLEAVING_GROUP
System attribute.
If all MCS chiplets are in an interleaving group (1=true, 0=false).
- If true the SMP fabric is setup in normal mode and multiple MCSs
are grouped (disallowing systems with memory only under 1 MCS
(i.e. systems with a single C-DIMM))
- If false the SMP fabric is setup in checkerboard mode.
Provided by the Machine Readable Workbook.
This attribute is based on Machine-Type-Model (MTM) and is setup by
the service processor.
0x00
non-volatile
Chip which contains the FSI master logic that drives this slave when booting from the alternate master processor
ALTFSI_MASTER_CHIP
physical:sys-0
EntityPath
non-volatile
Which port is this chip hanging off of when booting from the alternate master processor
ALTFSI_MASTER_PORT
non-volatile
0xFF
ASYNC_NEST_FREQ_MHZ
The asynchronous nest frequency
2000
non-volatile
ATTN_AREA_1_ADDR
Specifies the "intended" starting memory address for PHYP's ATTN area 1.
This is written to by Hostboot and read by FSP as a means for Hostboot to
communicate its intentions of where the ATTN 1 area will be. Hostboot can
then later open up an SBE window for PHYP to dump its debugging info. An
address of 0xFFFFFFFFFFFFFFFF is considered N/A.
0xFFFFFFFFFFFFFFFF
volatile
ATTN_AREA_2_ADDR
Specifies the "intended" starting memory address for PHYP's ATTN area 2.
This is written to by Hostboot and read by FSP as a means for Hostboot to
communicate its intentions of where the ATTN 2 area will be. Hostboot can
then later open up an SBE window for PHYP to dump its debugging info. An
address of 0xFFFFFFFFFFFFFFFF is considered N/A.
0xFFFFFFFFFFFFFFFF
volatile
Memory AVDD voltage domain ID. All memory buffers in the same AVDD
voltage domain will share the same ID. IDs are arbitrarily assigned,
used for correlation between HB + HWSV, and are generated by
genHwsvMrwXml.pl
AVDD_ID
non-volatile
0
Block speculative deconfig in reconfig loop.
Flags when speculative deconfigurations should not be done for
predictive gard records on a reconfig loop IPL due to out of
hardware condition on prior IPL.
0 = Allow speculative deconfiguration
1 = Block speculative deconfiguration
BLOCK_SPEC_DECONFIG
non-volatile
0x0
BMC FRU ID attribute to report the system firmware levels
to the BMC.
BMC_FRU_ID
non-volatile
0
DEFAULT_ALL
Enumeration for the various BPM update behaviors
DEFAULT_ALL
0x0000
SKIP_ALL
0x1010
FORCE_ALL
0x1111
SKIP_FW
0x1000
FORCE_FW
0x1100
SKIP_CONFIG
0x0010
FORCE_CONFIG
0x0011
FORCE_CONFIG_SKIP_FW
0x1011
SKIP_CONFIG_FORCE_FW
0x1110
BPM_UPDATE_BEHAVIOR
BPM_UPDATE_OVERRIDE
If non-zero then use value to determine which portion of BPM updates to
skip/force/default behavior.
volatile-zeroed
BRAZOS_RX_FIFO_OVERRIDE
Defines where to apply Brazos rx_fifo_final_l2u_dly override settings for SW299500.
0
non-volatile
Specifies a target's CEC degraded mode domain. For example, all
DIMMs are part of the DIMM CEC degraded mode domain.
CDM_DOMAIN
non-volatile
CDM_DOMAIN
NONE
Enumeration specifying a target's CEC degraded mode domain
NONE
0
CPU
1
DIMM
2
FABRIC
3
MEM
4
IO
5
NODE
6
CLOCK
7
PSI
8
FSP
9
ALL
10
CDM_DOMAIN
Cec Degraded Mode Policy flags
Use the CDM_POLICIES enum to decode.
If the appropriate bit is 1 then the policy mode is enabled,
and those type of Guard records are disabled.
CDM_POLICIES
non-volatile
0x00
Enumeration of CDM_POLICIES flags
MFG_Guard policy:
Used in MFG only to prevent and disable the following:
. Storing or creation of new Guard records from Diagno`stic or other
faults through error logs. This is all domains, CEC
processor/memory, VPD, FSP, etc.
. Storing or creation of Manual Guard record from user.
NOTE: this does not stop FCO.
. Using an already stored System or Manual Guard record from
deconfiguring resources. This is all domains, CEC
processor/memory, VPD, FSP, etc.
MANUFACTURING_DISABLED
0x01
Predictive_Guard policy:
Used in Field or development to prevent and disable the following:
. Storing or creation of new Guard records from diagnostics or other
faults through error logs with the error_type of Predictive.
. Using an already stored System Guard record with error_type of
Predictive from deconfiguring resources.
PREDICTIVE_DISABLED
0x02
CDM_POLICIES
Structure which defines a they IPL types
Applicable for System target only.
1
0
Perform mainstore dump collection. Only valid for MPIPL
0b0: Do not collect mainstore dump
0b1: Perform mainstore dump collection
PostDump
uint8_t
7
0
Minor IPL Type
MinorIPLType
uint8_t
Attribute which describes optional IPL flavors
CEC_IPL_TYPE
volatile
FRU ID attribute for centaur ECID data. This fru ID is used to
report the ECID data to the BMC and make it available for systems which
have then centaur chips soldered to the backplane.
CENTAUR_ECID_FRU_ID
non-volatile
DRAM Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
CEN_MSS_VOLT_AVDD_MILLIVOLTS
volatile-zeroed
DRAM Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
CEN_MSS_VOLT_AVDD_OFFSET_MILLIVOLTS
volatile-zeroed
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
CEN_MSS_VOLT_VCS_MILLIVOLTS
volatile-zeroed
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
CEN_MSS_VOLT_VCS_OFFSET_MILLIVOLTS
volatile-zeroed
DRAM Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
CEN_MSS_VOLT_VDDR_MILLIVOLTS
volatile-zeroed
ATTR_CEN_MSS_VOLT
DIRECT
DRAM Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
CEN_MSS_VOLT_VDDR_OFFSET_MILLIVOLTS
volatile-zeroed
ATTR_CEN_MSS_VDDR_OFFSET
DIRECT
DRAM Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
CEN_MSS_VOLT_VDD_MILLIVOLTS
volatile-zeroed
DRAM Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
CEN_MSS_VOLT_VDD_OFFSET_MILLIVOLTS
volatile-zeroed
DRAM VPP Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
CEN_MSS_VOLT_VPP_MILLIVOLTS
volatile-zeroed
ATTR_CEN_MSS_VOLT_VPP
DIRECT
DRAM VPP Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
CEN_MSS_VOLT_VPP_OFFSET_MILLIVOLTS
volatile-zeroed
The address offset which each Chiplet types pervasive
address space used to represent the a chiplet.
0x00 to 0x0F => For P9 all non-core and non-cache chiplets
0x10 to 0x1F => All Cache Chiplets
0x20 to 0x37 => All Core Chiplets
0x38 to 0x3F => Multicast Operation
CHIPLET_ID
non-volatile
0xFF
CHIP_ID
attribute indicating the chip's ID
volatile-zeroed
A unit (chiplet) 's offset number within the chip.
CHIP_UNIT
non-volatile
0
ATTR_CHIP_UNIT_POS
DIRECT
Attribute indicating the target's class
CLASS
non-volatile
CLASS
NA
Enumeration indicating the target's class
NA
0
CARD
1
ENC
2
CHIP
3
UNIT
4
DEV
5
SYS
6
LOGICAL_CARD
7
BATTERY
8
LED
9
SP
10
ASIC
11
MAX
12
CLASS
CPU Attribute
CPU_ATTR
non-volatile
CVPD_MAX_SECTIONS
Max CVPD sections
32
non-volatile
CVPD_SIZE
Size of CDIMM/ISDIMM
This is the size of the centaur vpd or memory buffer vpd.
It varies based on the type of the DIMM. For ISDIMMs,
the size will be 8KB and for CDIMM, it will be 4KB.
0x2000
non-volatile
L1 Data Cache Line Size in bytes
DATA_CACHE_LINE_SIZE
non-volatile
L1 Data Cache Size in KB
DATA_CACHE_SIZE
non-volatile
DCache Associative Sets
DCACHE_ASSOC_SETS
non-volatile
DCache Line Size in bytes
DCACHE_LINE_SIZE
non-volatile
If the Target is directly deconfigurable and GARDable; target
may still be deconfigured in 'by association' processing.
DECONFIG_GARDABLE
non-volatile
0
Used to tell I2C code whether to run
I2C Engine 2 Port 0 in diag mode or not
0 = Use Diag Mode
1 = Disable Diag Mode
DISABLE_I2C_ENGINE2_PORT0_DIAG_MODE
non-volatile
1
Indicates if system should consider abus logic when deconfiguring in
_deconfigureAssocProc(), will be overwritten on multi-node system
DO_ABUS_DECONFIG
non-volatile
1
Defines a negative percentage value that is applied to
the ATTR_NOMINAL_FREQ_MHZ determined from MVPD #V. It
is used to explicitly raise the value of MIN_FREQ_MHZ above
what is specified by MVPD #V data. On FSP systems this
is sourced from the power_management def file.
Value must be between 0 and -100.
A value of zero indicates no override.
DPO_MIN_FREQ_PERCENT
non-volatile
-100
0
0
Dummy attribute on the heap with zero initialization
DUMMY_HEAP_ZERO_DEFAULT
volatile-zeroed
Dummy attribute with read-only permissions
DUMMY_RO
non-volatile
0
Dummy attribute with read/write permissions
DUMMY_RW
non-volatile
1,3,5
5
ATTR_DUMMY_SCRATCH_PLAT_INIT_UINT8
DIRECT
Dummy attribute with write-only permissions
DUMMY_WO
non-volatile
0
EC
attribute indicating the chip target's EC level
volatile-zeroed
ATTR_EC
DIRECT
Specifies a target's eeprom content type.
EEPROM_CONTENT_TYPE
non-volatile
EEPROM_CONTENT_TYPE
RAW
Enumeration indicating a target's eeprom
content type.
RAW - eeprom has no specified layout
ISDIMM - uses standard JEDEC layout for DDR memory
IBM_FRUVPD - uses ipz converged vpd layout with records/keywords for
generic FRUs
IBM_MVPD - use ipz converged vpd layout with records/keywords for
processor modules
DDIMM - uses Differential DIMM layout
RAW
0
ISDIMM
1
IBM_FRUVPD
2
IBM_MVPD
3
DDIMM
4
EEPROM_CONTENT_TYPE
EEPROM_NV_INFO
Information needed to address the NV controller on the NVDIMM
Structure to define the addressing for NV controller.
i2cMasterPath
Entity path to the chip that contains the I2C
master.
EntityPath
physical:sys-0
port
Port from the I2C Master device. This is a 6-bit
value, but then shifted 2 bits left.
uint8_t
0x80
devAddr
Device address on the I2C bus. This is a 7-bit value,
but then shifted 1 bit left.
uint8_t
0x80
engine
I2C master engine. This is a 2-bit value,
but then shifted 6 bits left.
uint8_t
0x80
byteAddrOffset
The number of bytes a device requires to set its
internal address/offset. For NV controller it's only
one byte addressing with no page select (3)
0 = Zero Byte Addressing
1 = One Byte Addressing with page select
2 = Two Byte Addressing
3 = OneByte Addressing with no page select
uint8_t
0x03
maxMemorySizeKB
The number of kilobytes a device can hold. 'Zero'
value possible for some devices.
uint64_t
0x01
chipCount
The number of chips making up an eeprom device.
uint8_t
0x01
writePageSize
The maximum number of bytes that can be written to
a device at one time. 'Zero' value means no maximum value is
expected or checked.
uint64_t
0x01
writeCycleTime
The amount of time in milliseconds a device requires
on the completion of a write command to update its internal memory.
uint64_t
0x05
0xFF
Determines which of the N selectable buses the mux
will connect to. OxFF indicates no mux present
or N/A.
i2cMuxBusSelector
uint8_t
physical:sys-0
Entity path to the I2C mux for this device.
i2cMuxPath
EntityPath
non-volatile
Structure to define the addressing for an I2C
slave device.
physical:sys-0
Entity path to the chip that contains the I2C
master
i2cMasterPath
EntityPath
0x80
Port from the I2C Master device. This is a 6-bit
value.
port
uint8_t
0x80
Device address on the I2C bus. This is a 7-bit value,
but then shifted 1 bit left.
devAddr
uint8_t
0x80
I2C master engine. This is a 2-bit
value.
engine
uint8_t
0x02
The number of bytes a device requires to set its
internal address/offset.
byteAddrOffset
uint8_t
0x100
The number of kilobytes a device can hold. 'Zero'
value possible for some devices.
maxMemorySizeKB
uint64_t
0x04
The number of chips making up an eeprom device.
chipCount
uint8_t
0x0
The maximum number of bytes that can be written to
a device at one time. 'Zero' value means no maximum
value is expected or checked.
writePageSize
uint64_t
0x0
The amount of time in milliseconds a device requires
on the completion of a write command to update its
internal memory.
writeCycleTime
uint64_t
0xFF
Determines which of the N selectable buses the mux
will connect to. OxFF indicates no mux present
or N/A.
i2cMuxBusSelector
uint8_t
physical:sys-0
Entity path to the I2C mux for this device.
i2cMuxPath
EntityPath
Information needed to address the EERPROM slaves
EEPROM_SBE_BACKUP_INFO
non-volatile
Structure to define the addressing for an I2C
slave device.
physical:sys-0
Entity path to the chip that contains the I2C
master
i2cMasterPath
EntityPath
0x80
Port from the I2C Master device. This is a 6-bit
value.
port
uint8_t
0x80
Device address on the I2C bus. This is a 7-bit value,
but then shifted 1 bit left.
devAddr
uint8_t
0x80
I2C master engine. This is a 2-bit
value.
engine
uint8_t
0x02
The number of bytes a device requires to set its
internal address/offset.
byteAddrOffset
uint8_t
0x100
The number of kilobytes a device can hold. 'Zero'
value possible for some devices.
maxMemorySizeKB
uint64_t
0x04
The number of chips making up an eeprom device.
chipCount
uint8_t
0x0
The maximum number of bytes that can be written to
a device at one time. 'Zero' value means no maximum
value is expected or checked.
writePageSize
uint64_t
0x0
The amount of time in milliseconds a device requires
on the completion of a write command to update its
internal memory.
writeCycleTime
uint64_t
0xFF
Determines which of the N selectable buses the mux
will connect to. OxFF indicates no mux present
or N/A.
i2cMuxBusSelector
uint8_t
physical:sys-0
Entity path to the I2C mux for this device.
i2cMuxPath
EntityPath
Information needed to address the EERPROM slaves
EEPROM_SBE_PRIMARY_INFO
non-volatile
Structure to define the addressing for an attached I2C
eeprom device that contains secondary VPD info.
physical:sys-0
Entity path to the chip that contains the I2C
master
i2cMasterPath
EntityPath
0xFF
Port from the I2C Master device. This is a 6-bit
value.
port
uint8_t
0xFF
Device address on the I2C bus. This is a 7-bit value,
but then shifted 1 bit left.
devAddr
uint8_t
0xFF
I2C master engine. This is a 2-bit
value.
engine
uint8_t
0xFF
The number of bytes a device requires to set its
internal address/offset.
byteAddrOffset
uint8_t
0xFFFFFFFFFFFFFFFF
The number of kilobytes a device can hold. 'Zero'
value possible for some devices.
maxMemorySizeKB
uint64_t
0xFF
The number of chips making up an eeprom device.
chipCount
uint8_t
0xFFFFFFFFFFFFFFFF
The maximum number of bytes that can be written to
a device at one time. 'Zero' value means no maximum
value is expected or checked.
writePageSize
uint64_t
0xFFFFFFFFFFFFFFFF
The amount of time in milliseconds a device requires
on the completion of a write command to update its
internal memory.
writeCycleTime
uint64_t
0xFF
Determines which of the N selectable buses the mux
will connect to. OxFF indicates no mux present
or N/A.
i2cMuxBusSelector
uint8_t
physical:sys-0
Entity path to the I2C mux for this device.
i2cMuxPath
EntityPath
0xFFFFFFFF
Indicates the target's eeprom content type
eepromContentType
uint32_t
Information needed to address the EERPROM slaves
EEPROM_VPD_BACKUP_INFO
non-volatile
Structure to define the addressing for an attached I2C
eeprom device that contains primary VPD info.
physical:sys-0
Entity path to the chip that contains the I2C
master
i2cMasterPath
EntityPath
0xFF
Port from the I2C Master device. This is a 6-bit
value.
port
uint8_t
0xFF
Device address on the I2C bus. This is a 7-bit value,
but then shifted 1 bit left.
devAddr
uint8_t
0xFF
I2C master engine. This is a 2-bit
value.
engine
uint8_t
0xFF
The number of bytes a device requires to set its
internal address/offset. DDR4 DIMMs require a special EEPROM
page switching mechanic denoted here by a value of 1
0 = Zero Byte Addressing
1 = One Byte Addressing with page select
2 = Two Byte Addressing
3 = OneByte Addressing with no page select
byteAddrOffset
uint8_t
0xFFFFFFFFFFFFFFFF
The number of kilobytes a device can hold. 'Zero'
value possible for some devices.
maxMemorySizeKB
uint64_t
0xFF
The number of chips making up an eeprom device.
chipCount
uint8_t
0xFFFFFFFFFFFFFFFF
The maximum number of bytes that can be written to
a device at one time. 'Zero' value means no maximum
value is expected or checked.
writePageSize
uint64_t
0xFFFFFFFFFFFFFFFF
The amount of time in milliseconds a device requires
on the completion of a write command to update its
internal memory.
writeCycleTime
uint64_t
0xFF
Determines which of the N selectable buses the mux
will connect to. OxFF indicates no mux present
or N/A.
i2cMuxBusSelector
uint8_t
physical:sys-0
Entity path to the I2C mux for this device.
i2cMuxPath
EntityPath
0xFFFFFFFF
Indicates the target's eeprom content type
eepromContentType
uint32_t
Information needed to address the EEPROM slaves
EEPROM_VPD_PRIMARY_INFO
non-volatile
Holds the effective EC of the system. Effective EC is the lowest EC
among all the functional procs in the system. Some cards may "downbin"
the effective ECs of their contained processors, which could lower the
effective EC of the system beyond what would occur when considering
processor ECs alone
EFFECTIVE_EC
non-volatile
0xFF
Bitmask of threads to enable for each processor,
Zero means enable all architected threads
ENABLED_THREADS
volatile-zeroed
Attribute indicating the target's engine type
ENGINE_TYPE
non-volatile
ENGINE_TYPE
NA
Enumeration indicating the target's engine type
NA
0
ENGINE_IIC
1
ENGINE_SCOM
2
ENGINE_TYPE
Chip attribute.
Logical fabric chip id for this chip (position within the fabric).
Provided by the Machine Readable Workbook.
Can vary across drawers.
FABRIC_CHIP_ID
non-volatile
0
ATTR_PROC_FABRIC_CHIP_ID
DIRECT
Chip attribute.
Logical fabric group the chip belongs to.
Provided by the Machine Readable Workbook.
Can vary across drawers.
FABRIC_GROUP_ID
non-volatile
0
ATTR_PROC_FABRIC_GROUP_ID
DIRECT
Correlate HDAT node number (physical) to the logical node
(based on the PIR) that contains the host boot image.
FABRIC_TO_PHYSICAL_NODE_MAP
volatile
8
0,255,255,255,255,255,255,255
FAPI_I2C_CONTROL_INFO
Information needed to address an I2C slave device
Structure to define addressing this I2C slave device.
physical:sys-0
Entity path to the chip that contains the I2C master
i2cMasterPath
EntityPath
0x80
I2C master engine. This is a 2-bit value.
engine
uint8_t
0x80
Port from the I2C Master device. This is a 6-bit value.
port
uint8_t
0x80
Device address on the I2C bus. This is a 7-bit value,
but then shifted 1 bit left.
devAddr
uint8_t
0xFF
Determines which of the N selectable buses the mux
will connect to. OxFF indicates no mux present
or N/A.
i2cMuxBusSelector
uint8_t
physical:sys-0
Entity path to the I2C mux for this device.
i2cMuxPath
EntityPath
non-volatile
Common name across FAPI environments
chip target -> pu:k0:n0:s0:p00
DIMM target -> dimm:k0:n0:s0:p00
chip unit target -> pu.core:k0:n0:s0:p00:c0
cage/system target -> k0
(chip type).(unit type):k(cage,always zero for us):n(node/drawer)
:s(slot,always zero for us):p(chip position):c(core/unit position)
pu = generic processor
FAPI_NAME
non-volatile
unknown
64
NA
Enumeration defining special FAPI_POS values
NA
0xFFFFFFFF
FAPI_POS
Field Core Override (FCO) is the override value for the
number of functional cores allowed on the system.
FCO is used when customers order a system with N cores but they only want
to enable less than N cores to lower software license costs. A field in the
anchor VPD is set by manufacturing to specify the maximum number of cores
to enable. The number is maintained, even if some cores are garded out due
to error.
A value of 0 means all cores allowed;
FIELD_CORE_OVERRIDE
non-volatile
0
This attribute represents the Maximum number of L2 Column Repairs allowed
in the Field.
creator: platform (generated based on MRW data)
FIELD_TH_P8EX_L2_COL_REPAIRS
non-volatile
7
This attribute represents the Maximum number of L2 Line Deletes allowed
in the Field.
creator: platform (generated based on MRW data)
FIELD_TH_P8EX_L2_LINE_DELETES
non-volatile
6
This attribute represents the Maximum number of L3 Column Repairs allowed
in the Field.
creator: platform (generated based on MRW data)
FIELD_TH_P8EX_L3_COL_REPAIRS
non-volatile
7
This attribute represents the Maximum number of L3 Line Deletes allowed
in the Field.
creator: platform (generated based on MRW data)
FIELD_TH_P8EX_L3_LINE_DELETES
non-volatile
6
Lab-only trigger to force a factory reset of the NVDIMMs.
NOTE: This will erase any saved image and encryption keys.
FORCE_NVDIMM_RESET
volatile-zeroed
0
FORCE_SRAM_MMIO_OVER_I2C
Force inband SRAM access to be over I2C instead of MMIO
This is a way to get data when the MMIO path is not working
(0x00 = use normal path, 0x01 = force i2c path)
volatile-zeroed
FREQ_CORE_CEILING_MHZ
The maximum core frequency in MHz.
This is the same for all cores in the system.
Data is provided by MVPD #V and is calculated as
the minimum of the turbo frequencies.
volatile
ATTR_FREQ_CORE_CEILING_MHZ
DIRECT
FREQ_CORE_MAX
SYSTEM Attribute
Maximum frequency (binary in MHz) that any processor in the system will
run. Used to define the top end of the PState range in the frequency space.
From this, the ATTR_PROCPM_PSTATE0_FREQUENCY is computed using
ATTR_SYSTEM_REFCLK_FREQUENCY to determine the step size.
Consumers: proc_build_gpstate_table.C (among others)
Data is is provided by MVPD #V and is calculated as the minimum
of the turbo frequencies
non-volatile
FREQ_PROC_REFCLOCK
System attribute.
The frequency of the processor refclock in MHz.
Provided by the MRW.
non-volatile
FRU ID attribute used to report FRU information to the BMC
for each fru in the system.
FRU_ID
non-volatile
0
Chip which contains the FSI master logic that drives this slave when booting from the default master processor
FSI_MASTER_CHIP
physical:sys-0
EntityPath
non-volatile
Which port is this chip hanging off of when booting from the default master processor
FSI_MASTER_PORT
non-volatile
0xFF
Type of Master FSI connection to this slave (MFSI or cMFSI)
FSI_MASTER_TYPE
non-volatile
NO_MASTER
FSI_MASTER_TYPE
NO_MASTER
Enumeration indicating the master's FSI type
MFSI
0
CMFSI
1
NO_MASTER
2
FSI_MASTER_TYPE
FSI flags
1
0
Set on FSI master chips (procs) if that chip uses slaveB
to attach to the acting master chip.
flipPort
uint16_t
15
0
Reserved for future expansion
reserved
uint16_t
Reserved for any special flags we might need to access FSI
FSI_OPTION_FLAGS
non-volatile
Slave cascade position
FSI_SLAVE_CASCADE
non-volatile
0
Size of FSP IO Region
FSP_BAR_SIZE
non-volatile
0x0000000100000000
Base Address of FSP IO Region
FSP_BASE_ADDR
non-volatile
0x0003FFE000000000
ATTR_PROC_FSP_BAR_BASE_ADDR
DIRECT
FUSED_CORE_MODE_HB
Enum for FUSED_CORE_MODE_HB
SMT4_DEFAULT
0
SMT4_ONLY
1
SMT8_ONLY
2
FUSED_CORE_MODE_HB
Stores the SMT setting used to determine fused mode.
SMT4_DEFAULT: Nimbus_DD1, boot in SMT4 but can change to SMT8
SMT4_ONLY: Nimbus_DD2/Cumulus, set based on PVR info
SMT8_ONLY: Nimbus_DD2/Cumulus, set based on PVR info
non-volatile
If not loading PHYP or OPAL, then use this to
decide whether to use FUSED cores or NOT.
FUSED_CORE_OPTION
volatile-zeroed
Enum for FUSED_CORE_OPTION
USING_DEFAULT_CORES
0
USING_NORMAL_CORES
1
USING_FUSED_CORES
2
FUSED_CORE_OPTION
Hostboot HRMOR = (HB_HRMOR_NODAL_BASE * node) + offset.
HB_HRMOR_NODAL_BASE
volatile
0x200000000000
The amount of mainstore that PHYP needs to preserve per node
during MPIPL.
HB_RSV_MEM_SIZE_MB
non-volatile
256
Structure which defines a system's HB settings.
Applicable for System target only.
1
0
Enable / Disable continuous trace.
0b0: Continuous trace is disabled.
0b1: Continuous trace is enabled.
traceContinuous
uint8_t
1
0
Override trace debug selection for SCAN component.
0b0: TRACS entries for SCAN have default behavior.
0b1: TRACS entries for SCAN are enabled.
traceScanDebug
uint8_t
1
0
Override trace debug selection for DBG component.
0b0: TRACS entries for DBG have default behavior.
0b1: TRACS entries for DBG are enabled.
traceFapiDebug
uint8_t
5
0
Reserved for future use
reserved
uint8_t
Attribute which describes how the SP has configured features in
Hostboot.
HB_SETTINGS
non-volatile
Indicates the chip's EC level, distinct from ATTR_EC to handle
non-standard mini-ECs, e.g. 1.01, separate from the real
hardware-defined EC level. By default, ATTR_HDAT_EC==ATTR_EC
unless the chip has a mini-EC.
HDAT_EC
volatile-zeroed
Number of internal data pointers we have in
the hostboot runtime data section.
HDAT_HBRT_NUM_SECTIONS
volatile-zeroed
Biggest size for any of the hostboot
runtime data sections.
HDAT_HBRT_SECTION_SIZE
volatile-zeroed
9
Pulled from the MRW, this describes the device
purpose to the HDAT. This is for I2C devices only.
CABLE_CARD_PRES
0x1
PCI_HOTPLUG_PGOOD
0x2
PCI_HOTPLUG_CONTROL
0x3
TPM
0x4
MODULE_VPD
0x5
DIMM_SPD
0x6
PROC_MODULE_VPD
0x7
SBE_SEEPROM
0x8
PLANAR_VPD
0x9
NVLINK_CABLE_TOPOLOGY_VERIFICATION
0xA
NVLINK
0xB
NVLINK_CABLE_MICRO_RESET
0xB
I2C_ASSOC_WITH_NVLINK_CABLE
0xC
WINDOW_OPEN
0xD
PHYSICAL_PRESENCE
0xE
MEX_FPGA
0xF
UNKNOWN
0xFF
HDAT_I2C_DEVICE_PURPOSE
Pulled from the MRW, this describes the device
type to the HDAT. This is for I2C devices only.
9551
0x1
955X
0x1
SEEPROM
0x2
SEEPROM_Atmel28c128
0x2
NUVOTON_TPM
0x3
MEX_FPGA
0x4
UCX90XX
0x5
NVLINK
0x6
9552
0x6
9553
0x7
9554
0x8
9555
0x9
SMP_or_OpenCAPI_Cable
0xA
SEEPROM_Atmel28c256
0xB
THERMAL_SENSOR
0x0C
SEEPROM_Atmel24c04
0x0D
SEEPROM_Atmel24c412
0x0E
SEEPROM_Atmel24c32
0x0F
SEEPROM_Atmel24c64
0x10
SEEPROM_Atmel24c16
0x11
NVDIA_GPU
0x12
NXP_LPC_Microcontroller_LPC11U35
0x13
9550
0x14
TCG_I2C_TPM
0x15
UNKNOWN
0xFF
HDAT_I2C_DEVICE_TYPE
Number of internal data pointers we have in
the hostboot reserved memory section.
HDAT_RSV_MEM_NUM_SECTIONS
volatile-zeroed
HDDW_ORDER
PCIe slot HDDW order definition
non-volatile
HOMER_PHYS_ADDR
Physical address where HOMER image is placed in mainstore.
volatile-zeroed
ATTR_HOMER_PHYS_ADDR
DIRECT
Value of the next EID that host service should send.
(Note - EID is more accurate, PLID being kept to handle legacy code.)
HOSTSVC_PLID
non-volatile
0x89000000
HOT_PLUG_POWER_CONTROLLER_INFO
Hot Plug Controller values for a specific processor.
Purpose: Holds information about the hot plug controllers so that a
Hardware procedure is able to turn them on and off.
Data Format: up to 8 Hot Plug Controllers x 7 variables of information
This data is at the processor level.
The needed information and their individual sizes are as follows:
(1) I2C Master processor engine (uint8_t)
(2) I2C Master processor port (uint8_t)
(3) Bus Speed (uint16_t value: 2 uint8_t values: MSB, LSB)
(4) Slave address (uint8_t)
(5) Device type (uint8_t: see SUPPORTED_HOT_PLUG enum)
(6) I2C Master processor node (uint8_t)
(7) I2C Master processor position (uint8_t)
Thus, the information will be 8 bytes.
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
8,8
non-volatile
Hardware Unit ID
SSSSNNNNTTTTTTTTiiiiiiiiiiiiiiii
S=System
N=Node Number
T=Target Type (matches TYPE attribute)
i=Instance/Sequence number of target, relative to node
HUID
non-volatile
0xFFFFFFFF
Enumeration indicating the services that are concerned
with target changes (ie, via HCDB change).
The values can be combined using a bitwise 'OR'.
GARD
0x00000001
MEMDIAG
0x00000002
PSIDIAG
0x00000004
DIAG_MASK
0x00000006
HOSTSVC_HBEL
0x00000008
RESRC_RECOV
0x00000010
GARD_APPLIED
0x00000020
HWAS_CHANGED_BIT
struct - 4 booleans and a PLID
0
if this target was deconfigured,
this will be a special DECONFIGURED_BY_ enum,
OR it will be the errlog EID that caused it,
either directly or by association,
deconfiguredByEid
uint32_t
1
0
0b0: Target is not powered on (is off);
0b1: Target is powered on;
poweredOn
uint8_t
1
0
0b0: Target is not present in the system;
0b1: Target is present in the system
present
uint8_t
1
0
0b0: Target is not functional;
0b1: Target is functional
functional
uint8_t
1
0
FSP Only, used by DUMP applet;
0b0: target is dump capabile;
0b1: target is not dump capabile;
dumpfunctional
uint8_t
1
0
Set for speculative deconfig;
0b0: target not speculative deconfig;
0b1: target is speculatively deconfigured;
specdeconfig
uint8_t
HardWare Availability Service State Attribute.
Keeps track of Target values poweredOn, present, functional
HWAS_STATE
volatile
HardWare Availability Service State Changed Attribute.
Keeps track of changedSinceChecked state, indicates if the
target has changed since last checked by the appropriate service.
This is a bit field of flags (see HWAS_CHANGED_BIT enumeration
that follows).
HWAS_STATE_CHANGED_FLAG
non-volatile
0x0
HardWare Availability Service State Changed Mask.
Used when a target changes (ie, via HCDB change) to set the
HWAS_STATE_CHANGED_FLAG, so that the appropriate services will
all handle the change.
This is a bit field of flags (see HWAS_CHANGED_BIT enumeration
that follows).
HWAS_STATE_CHANGED_SUBSCRIPTION_MASK
non-volatile
0x0
Designates the speed at which a given I2C bus should run.
Creator: MRW
Purpose: Used by FW to know the fastest possible bus speed that all of
the devices on a given bus are able to use.
Data Format: 4x13 array of uint16_t values. The first index indicates
the engine number of the bus. The second index indicates the port
number of the bus. The value in the array is the I2C bus speed
used for that engine/port combination in KHz.
I2C_BUS_SPEED_ARRAY
non-volatile
4,13
0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0
I2C_CONTROL_INFO
Information needed to address an I2C slave device
Structure to define addressing this I2C slave device.
physical:sys-0
Entity path to the chip that contains the I2C master
i2cMasterPath
EntityPath
0x80
I2C master engine. This is a 2-bit value.
engine
uint8_t
0x80
Port from the I2C Master device. This is a 6-bit value.
port
uint8_t
0x80
Device address on the I2C bus. This is a 7-bit value,
but then shifted 1 bit left.
devAddr
uint8_t
0xFF
Determines which of the N selectable buses the I2C mux for
this device
must enable to connect this device to its I2C master, if applicable.
0xFF indicates no I2C mux present or N/A.
i2cMuxBusSelector
uint8_t
physical:sys-0
Entity path of the I2C mux for this device, if any.
i2cMuxPath
EntityPath
non-volatile
Structure which defines which I2C access method to use at
a point in time. Only applicable if target supports one or more I2C
types. Only one bit (of the first two) can ever be set at any one time.
1
0
0b0: Do not use FSI I2C at this time. 0b1: Use FSI
I2C at this time
useFsiI2C
uint8_t
1
0
0b0: Do not use Host I2C at this time. 0b1: Use
Host I2C at this time
useHostI2C
uint8_t
6
0
Reserved for future expansion
reserved
uint8_t
Attribute storing information about which I2C method to use
I2C_SWITCHES
volatile
MCS Inband Scom base address
IBSCOM_MCS_BASE_ADDR
non-volatile
0x0003E00000000000
ATTR_MCS_INBAND_BASE_ADDRESS
DIRECT
PROC Inband Scom base address
IBSCOM_PROC_BASE_ADDR
non-volatile
0x0003E00000000000
ICache Assoc Sets
ICACHE_ASSOC_SETS
non-volatile
ICache Block Size in bytes
ICACHE_BLOCK_SIZE
non-volatile
Icache Line Size in bytes
ICACHE_LINE_SIZE
non-volatile
ICache Size in KB
ICACHE_SIZE
non-volatile
Size of IMT IO Region
Set by FSP-based tooling
IMT_BAR_SIZE
non-volatile
0x0000000000000000
Base Address of In-Memory Trace Region
Set by FSP-based tooling
IMT_BASE_ADDR
non-volatile
0xFFFFFFFFFFFFFFFF
Controls whether target discovery code should assume the target is
initially present, functional, and powered on (even though later
operations may change this). Commonly used to avoid having to do presence
detect on certain targets.
0x00: Do not assume target is initially available
0x01: Assume target is initially available
INIT_TO_AVAILABLE
non-volatile
0x00
0
1
Base Address of Interrupt Presenter
INTP_BASE_ADDR
volatile-zeroed
0xFFFFFFFFFFFFFFFF
ISTEP_MODE
If True, puts HostBoot into SPLess SingleStep mode.
0
non-volatile
ATTR_ISTEP_MODE
DIRECT
Used to configure the parameters for enabling pause/stop between
isteps. This attribute is set via attribute override.
ISTEP_PAUSE_CONFIG
volatile-zeroed
Used to enable pause/stop in between isteps. This attribute is set via
attribute override.
ISTEP_PAUSE_ENABLE
volatile-zeroed
Indicate an inter-enclosure bus at this endpoint target.
0 = No, 1 = Yes
IS_INTER_ENCLOSURE_BUS
volatile
0
KEY_CLEAR_REQUEST
Indicates types of Key Clear Requests are being made
volatile-zeroed
KEY_CLEAR_REQUEST
NONE
KEY_CLEAR_REQUEST
Enum indicating the different possible Key Clear Request values
(Default) Key clear not requested
NONE
0x0000
Clear/reset all sensitive data controlled by platform firmware
from the system
ALL
0x8000
This indicates OPAL to clear the OS platform key
OS_PK
0x4000
This indicates to OPAL/PEF to clear the System Security Officer
certificate
PEF_SSO
0x2000
This indicates to PowerVM to clear the system key to the default state
POWERVM_SYSKEY
0x1000
Clear all sensitive data for MFG processing
Only valid on development drivers
MFG
0x0100
Reserved bits
RESERVED
0x00FF
KEY_TRANSITION_STATE
Enum indicating the current Secure Boot key transition state for the
node.
Secure Boot key transition not yet requested for the node
KEY_TRANSITION_NOT_REQUESTED
0
About to write new system Secure Boot key to first SBE SEEPROM
side in the node
KEY_TRANSITION_STARTED
1
Failed to apply new system Secure Boot key to one or more functional
SBE SEEPROM sides in the node
KEY_TRANSITION_FAILED
2
Successfully applied new system Secure Boot key to every functional
SBE SEEPROM side in the node
KEY_TRANSITION_SUCCEEDED
3
Attribute indicating the status of the Secure Boot key transition for
the node
KEY_TRANSITION_STATE
volatile-zeroed
KEY_TRANSITION_STATE
KEY_TRANSITION_NOT_REQUESTED
L2 Cache Assoc Sets
L2_CACHE_ASSOC_SETS
non-volatile
L2 Cache Line Size in bytes
L2_CACHE_LINE_SIZE
non-volatile
L2 Cache Size in KB
L2_CACHE_SIZE
non-volatile
L3 Cache Line Size in bytes
L3_CACHE_LINE_SIZE
non-volatile
L3 Cache Size in KB
L3_CACHE_SIZE
non-volatile
Location code of the Fru target
LOCATION_CODE
64
non-volatile
LPC Bus address - MMIO consumed by PHYP
LPC_BUS_ADDR
volatile
System attribute.
The max chiplets per proc available in the system.
MAX_CHIPLETS_PER_PROC
non-volatile
MAX_COMPUTE_NODES_PER_SYSTEM
The max compute nodes available in the system.
Computed value based on CEC enclosures.
non-volatile
System attribute.
The max DIMMs per MBA Port available in the system.
MAX_DIMMS_PER_MBA_PORT
non-volatile
MAX_DMI_PER_PROC
System attribute.
The max DMI units per proc available in the system.
8
non-volatile
System attribute.
The max EX units per proc chip available in the system.
MAX_EXS_PER_PROC_CHIP
non-volatile
System attribute.
The max MBAS per membuf available in the system.
MAX_MBAS_PER_MEMBUF_CHIP
non-volatile
System attribute.
The max MBA ports per MBA available in the system.
MAX_MBA_PORTS_PER_MBA
non-volatile
System attribute.
The max MCS units available in the system.
MAX_MCS_PER_SYSTEM
non-volatile
4
MAX_POWER
Defines the maximum power consumption for a PCIe slot
non-volatile
System attribute.
The max proc chips per node available in the system.
MAX_PROC_CHIPS_PER_NODE
non-volatile
MAX_SBE_SEEPROM_SIZE
Defines the maximum Seeprom storage size for the fully-customized SBE image
permitted by the platform.
For platforms (FSP/HB FW) which require the image to be constrained into a
physical storage device (SEEPROM), this should reflect the maximum size of that
memory (e.g., 256KB).
For platforms (Cronus) which may use a customized image in a virtual
envrionment with no physical storage constraints, this size may be
larger than the physical SEEPROM size.
0x40000
non-volatile
ATTR_MAX_SBE_SEEPROM_SIZE
DIRECT
MBA_DIMM
MBA port DIMM number of this DIMM
(deprecated in favor of POS_ON_MEM_PORT)
0
non-volatile
MBA_PORT
MBA port this DIMM is connected to
(deprecated in favor of MEM_PORT)
0
non-volatile
MC_PLL_BUCKET
MC pll bucket selection in async mode for Cumulus
volatile-zeroed
ATTR_MC_PLL_BUCKET
DIRECT
Memory AVDD voltage domain offset in mV.
MEM_AVDD_OFFSET_MILLIVOLTS
volatile-zeroed
0
ATTR_MSS_AVDD_OFFSET
DIRECT
Base Address for all mainstore behind this processor
MEM_BASE
volatile-zeroed
ATTR_PROC_MEM_BASE
DIRECT
MEM_PORT
Memory port this DIMM is connected to
0
non-volatile
Memory VCS voltage domain offset in mV.
MEM_VCS_OFFSET_MILLIVOLTS
volatile-zeroed
0
ATTR_MSS_VCS_OFFSET
DIRECT
Memory VDDR voltage domain offset in mV.
MEM_VDDR_OFFSET_MILLIVOLTS
volatile-zeroed
0
ATTR_MSS_VDDR_OFFSET
DIRECT
Memory VDD voltage domain offset in mV.
MEM_VDD_OFFSET_MILLIVOLTS
volatile-zeroed
0
ATTR_MSS_VDD_OFFSET
DIRECT
Memory VPP voltage domain offset in mV.
MEM_VPP_OFFSET_MILLIVOLTS
volatile-zeroed
0
ATTR_MSS_VPP_OFFSET
DIRECT
MFG_TRACE_ENABLE
Override this to a non-zero value to have the FAPI manufacturing
traces output to the console or go to a fsp trace buffer when
console not enabled.
volatile-zeroed
MFG_WRAP_TEST_ABUS_LINKS_SET
Enum for MFG_WRAP_TEST_ABUS_LINKS_SET
SET_NONE
0x0
SET_1
0x1
SET_2
0x2
MFG_WRAP_TEST_ABUS_LINKS_SET
Due to fabric limitations, we can only enable 2 links
at a time during wrap testing. This attribute defines
which set this ABUS link belong to. This attribute
will live on the OBUS target. The value will come
from MRW. When the value for this attribute matches
MFG_WRAP_TEST_ABUS_LINKS_SET_ENABLE, then we leave the
OBUSes configured. Otherwise, we deconfigure them.
SET_NONE
MFG_WRAP_TEST_ABUS_LINKS_SET
non-volatile
MFG_WRAP_TEST_ABUS_LINKS_SET_ENABLE
This attribute defines which set of ABUS links to enable
during MST wrap testing. This attribute will live on
the system target. The value will be overriden during
MST testing. When the value of MFG_WRAP_TEST_ABUS_LINKS_SET
on each of the OBUS matches with this value, then we leave the
OBUSes configured. Otherwise, we deconfigure them.
0
volatile-zeroed
MGC_LOAD_SOURCE
defines MGC load source
non-volatile
System attribute.
The lowest frequency that a core can be set to in MHz.
This is the same for all cores in the system.
Data is provided by MVPD #V and is calculated as the
Maximum of the power save frequencies.
MIN_FREQ_MHZ
volatile
4800
ATTR_FREQ_CORE_FLOOR_MHZ
DIRECT
MIRROR_BASE_ADDRESS
System Mirrorable Base Address
Bits8-12 Specifies System Selects
Bits13-14 Memory select
Bits15-18 Group ID (within an SMP)
Bits19-21 Chip ID (8 Max)
Bits22-63 Chip internal address (42 bits, 4TB)
Mirroring uses memory select
0x4000000000000
non-volatile
ATTR_MIRROR_BASE_ADDRESS
DIRECT
MNFG_ABUS_MIN_EYE_HEIGHT
System attribute
8 bit rx_min_eye_height value for A bus interfaces during system
manufacturing
creator: platform
firmware notes: Attribute value is in the Machine Readable Workbook
non-volatile
MNFG_ABUS_MIN_EYE_WIDTH
System attribute
6 bit rx_min_eye_width value for A bus interfaces during system
manufacturing
creator: platform
firmware notes: Attribute value is in the Machine Readable Workbook
non-volatile
MNFG_DMI_MIN_EYE_HEIGHT
System attribute.
8 bit rx_min_eye_height value for DMI bus interfaces during system
manufacturing; used for both centaur and p8
creator: platform
firmware notes: Attribute value is in the Machine Readable Workbook
non-volatile
MNFG_DMI_MIN_EYE_WIDTH
System attribute.
6 bit rx_min_eye_width value for DMI bus interfaces during system
manufacturing; used for both centaur and p8
creator: platform
firmware notes: Attribute value is in the Machine Readable Workbook
non-volatile
MNFG_FLAG
Enumeration indicating the mnfg flags
that are set by the user. The values can be
combined using a bitwise 'OR'. The values will
need to be kept in sync with the FAPI
enumerator values. Also the enumeration type
is used by the ATTR_MNFG_FLAGS attribute. Should
note that the MNFG_FLAG values are of type uint32_t
THRESHOLDS
0x00000001
AVP_ENABLE
0x00000002
HDAT_AVP_ENABLE
0x00000004
SRC_TERM
0x00000008
IPL_MEMORY_CE_CHECKING
0x00000010
FAST_BACKGROUND_SCRUB
0x00000020
TEST_DRAM_REPAIRS
0x00000040
DISABLE_DRAM_REPAIRS
0x00000080
ENABLE_EXHAUSTIVE_PATTERN_TEST
0x00000100
ENABLE_STANDARD_PATTERN_TEST
0x00000200
ENABLE_MINIMUM_PATTERN_TEST
0x00000400
DISABLE_FABRIC_eREPAIR
0x00000800
DISABLE_MEMORY_eREPAIR
0x00001000
FABRIC_DEPLOY_LANE_SPARES
0x00002000
DMI_DEPLOY_LANE_SPARES
0x00004000
PSI_DIAGNOSTIC
0x00008000
BRAZOS_WRAP_CONFIG
0x00010000
FSP_UPDATE_SBE_IMAGE
0x00020000
UPDATE_BOTH_SIDES_OF_SBE
0x00040000
IMMEDIATE_HALT
0x00080000
This attribute represents the maximum number of L4 Cache CEs allowed.
creator: platform (generated based on MRW data)
MNFG_TH_CEN_L4_CACHE_CES
non-volatile
2
This attribute represents the Base threshold (for 2GB DRAM ) of
Memory CEs allowed during IPL.
creator: platform (generated based on MRW data)
MNFG_TH_CEN_MBA_IPL_SOFT_CE_TH_ALGO
non-volatile
2
This attribute represents the maximum number of Memory RCEs
allowed per Rank during runtime.
creator: platform (generated based on MRW data)
MNFG_TH_CEN_MBA_RT_RCE_PER_RANK
non-volatile
2
This attribute represents the Base threshold (for 2GB DRAM ) of
Memory CEs allowed during runtime.
creator: platform (generated based on MRW data)
MNFG_TH_CEN_MBA_RT_SOFT_CE_TH_ALGO
non-volatile
2
With MNFG thresholds enabled, PRD will make a predictive callout when a
memory intermittent MPE attention count is equal to this value. A value of
0 defaults to the max threshold of 0xff.
MNFG_TH_MEMORY_IMPES
non-volatile
1
With MNFG thresholds enabled, PRD will make a predictive callout when a
memory intermittent UE attention count is equal to this value. A value of
0 defaults to the max threshold of 0xff.
MNFG_TH_MEMORY_IUES
non-volatile
1
This attribute represents the Maximum number of L2 Cache CEs allowed
during Manufacturing.
creator: platform (generated based on MRW data)
MNFG_TH_P8EX_L2_CACHE_CES
non-volatile
1
This attribute represents the Maximum number of L2 Column Repairs allowed
during Manufacturing.
creator: platform (generated based on MRW data)
MNFG_TH_P8EX_L2_COL_REPAIRS
non-volatile
0
This attribute represents the Maximum number of L2 Directory CEs allowed
during Manufacturing.
creator: platform (generated based on MRW data)
MNFG_TH_P8EX_L2_DIR_CES
non-volatile
1
This attribute represents the Maximum number of L2 Line Deletes allowed
during Manufacturing.
creator: platform (generated based on MRW data)
MNFG_TH_P8EX_L2_LINE_DELETES
non-volatile
0
This attribute represents the Maximum number of L3 Cache CEs allowed
during Manufacturing.
creator: platform (generated based on MRW data)
MNFG_TH_P8EX_L3_CACHE_CES
non-volatile
3
This attribute represents the Maximum number of L3 Column Repairs allowed
during Manufacturing.
creator: platform (generated based on MRW data)
MNFG_TH_P8EX_L3_COL_REPAIRS
non-volatile
0
This attribute represents the Maximum number of L3 Directory CEs allowed
during Manufacturing.
creator: platform (generated based on MRW data)
MNFG_TH_P8EX_L3_DIR_CES
non-volatile
1
This attribute represents the Maximum number of L3 Line Deletes allowed
during Manufacturing.
creator: platform (generated based on MRW data)
MNFG_TH_P8EX_L3_LINE_DELETES
non-volatile
0
With MNFG thresholds enabled, PRD will make a predictive callout when an
RCD parity error (recovery enabled) attention count is equal to this
value. A value of 0 defaults to the max threshold of 0xff.
MNFG_TH_RCD_PARITY_ERRORS
non-volatile
1
MNFG_XBUS_MIN_EYE_WIDTH
System attribute
6 bit rx_min_eye_width value for X bus interfaces during system
manufacturing
creator: platform
firmware notes: Attribute value is in the Machine Readable Workbook
non-volatile
Attribute indicating the target's model
MODEL
non-volatile
MODEL
NA
Enumeration indicating the target's model
NA
0
RESERVED
16
VENICE
MURANO
NAPLES
NIMBUS
CUMULUS
AXONE
CENTAUR
48
OCMB
JEDEC
80
CDIMM
POWER8
112
POWER9
144
CECTPM
BMC
AST2500
PCA9847
UCD9090
UCD90120A
MODEL
MRU ID attribute for chip/unit class
MRU_ID
non-volatile
0x00
Maximum voltage limit for the dynamic VID DDR3 VDDR
voltage setpoint. In mV.
MRW_DDR3_VDDR_MAX_LIMIT
non-volatile
0
Maximum voltage limit for the dynamic VID DDR3 VDDR
voltage setpoint. In mV.
MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT
non-volatile
0
Maximum voltage limit for the dynamic VID DDR4 VDDR voltage
setpoint. In mV.
MRW_DDR4_VDDR_MAX_LIMIT
non-volatile
0
Maximum voltage limit for the dynamic VID DDR4 VDDR voltage
setpoint. In mV.
MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT
non-volatile
0
Attribute indicating the default risk level for the system. Applied if
scratch registers are not overriden
MRW_DEFAULT_RISK_LEVEL
non-volatile
0x0
MRW_MEM_THROTTLE_DENOMINATOR
Machine Readable Workbook throttle value for denominator cfg_nm_m
non-volatile
AVDD memory programming type
0 = POWERON - domain is programmed as part of regular power on sequence,
1 = STATIC - domain needs to be programmed, no special computation needed,
2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic
MSS_AVDD_PROGRAM
non-volatile
0
Units: mV
MSS_CENT_AVDD_INTERCEPT
non-volatile
0
ATTR_MSS_AVDD_SLOPE_INTERCEPT
DIRECT
Units: uV/Membuf
MSS_CENT_AVDD_SLOPE_ACTIVE
non-volatile
0
ATTR_MSS_AVDD_SLOPE_ACTIVE
DIRECT
Units: uV/Membuf
MSS_CENT_AVDD_SLOPE_INACTIVE
non-volatile
0
ATTR_MSS_AVDD_SLOPE_INACTIVE
DIRECT
Units: mV
MSS_CENT_VCS_INTERCEPT
non-volatile
0
Units: uV/Membuf
MSS_CENT_VCS_SLOPE_ACTIVE
non-volatile
0
Units: uV/Membuf
MSS_CENT_VCS_SLOPE_INACTIVE
non-volatile
0
Units: mV
MSS_CENT_VDD_INTERCEPT
non-volatile
0
Units: uV/Membuf
MSS_CENT_VDD_SLOPE_ACTIVE
non-volatile
0
Units: uV/Membuf
MSS_CENT_VDD_SLOPE_INACTIVE
non-volatile
0
MBA DRAM data bus utilization percent to use to determine cfg_nm_n_per_mba
MSS_DATABUS_UTIL_PER_MBA
volatile-zeroed
MSS_MBA_ADDR_INTERLEAVE_BIT
sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. valid values are 23 through 32.
0
non-volatile
MSS_MBA_CACHELINE_INTERLEAVE_MODE
centaur interleave mode. 1 = 256-BIT, 0 = 128-BIT.
0
non-volatile
NONE
Enumeration defining the type of power control requested
OFF
0
POWER_DOWN
1
STR
2
PD_AND_STR
3
MSS_MRW_IDLE_POWER_CONTROL_REQUESTED
OFF
Enumeration defining the type of power control requested
OFF
0
POWER_DOWN
1
STR
2
PD_AND_STR
3
MSS_MRW_POWER_CONTROL_REQUESTED
Enumeration for Temperature refresh mode
DISABLE
0
ENABLE
1
MSS_MRW_TEMP_REFRESH_MODE
MSS_PHY_SEQ_REFRESH
Controls ENABLE/DISABLE of workaround that sets
the PHY sequencer to trigger refresh after draminit.
2
volatile-zeroed
ATTR_MSS_PHY_SEQ_REFRESH
DIRECT
VCS memory programming type
0 = POWERON - domain is programmed as part of regular power on sequence,
1 = STATIC - domain needs to be programmed, no special computation needed,
2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic
MSS_VCS_PROGRAM
non-volatile
0
VDDR memory programming type
0 = POWERON - domain is programmed as part of regular power on sequence,
1 = STATIC - domain needs to be programmed, no special computation needed,
2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic,
3 = DEFAULT - domain needs to be programmed, pgm values in sys xml file
MSS_VDDR_PROGRAM
non-volatile
0
VDD memory programming type
0 = POWERON - domain is programmed as part of regular power on sequence,
1 = STATIC - domain needs to be programmed, no special computation needed,
2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic
MSS_VDD_PROGRAM
non-volatile
0
DRAM Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
MSS_VOLT_AVDD_MILLIVOLTS
volatile-zeroed
DRAM Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
MSS_VOLT_AVDD_OFFSET_MILLIVOLTS
volatile-zeroed
Units: mV
MSS_VOLT_DDR3_VDDR_INTERCEPT
non-volatile
0
Units: mV
MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT
non-volatile
0
Units: 1/Amps
MSS_VOLT_DDR3_VDDR_SLOPE
non-volatile
0
Units: 1/Amps
MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT
non-volatile
0
Units: mV
MSS_VOLT_DDR4_VDDR_INTERCEPT
non-volatile
0
Units: mV
MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT
non-volatile
0
Units: 1/Amps
MSS_VOLT_DDR4_VDDR_SLOPE
non-volatile
0
Units: 1/Amps
MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT
non-volatile
0
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
MSS_VOLT_VCS_MILLIVOLTS
volatile-zeroed
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
MSS_VOLT_VCS_OFFSET_MILLIVOLTS
volatile-zeroed
DRAM Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
MSS_VOLT_VDDR_MILLIVOLTS
volatile-zeroed
ATTR_MSS_VOLT_VDDR
DIRECT
DRAM Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
MSS_VOLT_VDDR_OFFSET_MILLIVOLTS
volatile-zeroed
DRAM Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
MSS_VOLT_VDD_MILLIVOLTS
volatile-zeroed
DRAM Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
MSS_VOLT_VDD_OFFSET_MILLIVOLTS
volatile-zeroed
Units: mV
MSS_VOLT_VPP_INTERCEPT
non-volatile
0
Units: mV
MSS_VOLT_VPP_INTERCEPT_POST_DRAM_INIT
non-volatile
0
DRAM VPP Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
MSS_VOLT_VPP_MILLIVOLTS
volatile-zeroed
ATTR_MSS_VOLT_VPP
DIRECT
DRAM VPP Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
MSS_VOLT_VPP_OFFSET_MILLIVOLTS
volatile-zeroed
Units: uV/DRAM
MSS_VOLT_VPP_SLOPE
non-volatile
0
Units: uV/DRAM
MSS_VOLT_VPP_SLOPE_POST_DRAM_INIT
non-volatile
0
VPP memory programming type
0 = POWERON - domain is programmed as part of regular power on sequence,
1 = STATIC - domain needs to be programmed, no special computation needed,
2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic
MSS_VPP_PROGRAM
non-volatile
0
Enumeration indicating the multi scome
buffer size. The values can be combined using a
bitwise 'OR'. The values will need to be kept
in sync with the FAPI enumerator values. Also
the enumeration type is used by the
ATTR_MULTI_SCOM_BUFFER_MAX_SIZE. Should
note that the MULTI_SCOM_BUFFER_MAX_SIZE values
are of type uint32_t
MULTI_SCOM_BUFFER_SIZE_1KB
0x00000400
MULTI_SCOM_BUFFER_SIZE_2KB
0x00000800
MULTI_SCOM_BUFFER_SIZE_4KB
0x00001000
MULTI_SCOM_BUFFER_SIZE_8KB
0x00002000
MULTI_SCOM_BUFFER_SIZE_16KB
0x00004000
MULTI_SCOM_BUFFER_SIZE_32KB
0x00008000
MULTI_SCOM_BUFFER_SIZE_64KB
0x00010000
MULTI_SCOM_BUFFER_SIZE_128KB
0x00020000
MULTI_SCOM_BUFFER_SIZE_256KB
0x00040000
MULTI_SCOM_BUFFER_SIZE_512KB
0x00080000
MULTI_SCOM_BUFFER_SIZE_1MB
0x00100000
MULTI_SCOM_BUFFER_MAX_SIZE_BIT
NEST_PLL_FREQ_BUCKETS
Constant defining number of NEST PLL frequency options ('buckets')
to be built into unsigned HW image.
0x05
volatile
NEST_PLL_FREQ_I2CDIV_LIST
I2C bus divisor
index is bucket number
The values in this list will be factor of 1:64 to the NEST_PLL_FREQ_LIST
25,29,31,33,37
5
volatile
NEST_PLL_FREQ_LIST
Nest PLL frequency in MHZ
index is bucket number
1600,1866,2000,2133,2400
5
volatile
Nest VCS Voltage Rail ID. The ID is an arbitrary value and is needed as
correlation token between HB and HWSV. It will be generated by the
genHwsvMrwXml.pl
NEST_VCS_ID
non-volatile
0
Nest VDDR Voltage Rail ID. The ID is an arbitrary value and is needed as
correlation token between HB and HWSV. It will be generated by the
genHwsvMrwXml.pl
NEST_VDDR_ID
non-volatile
0
Nest VDD Voltage Rail ID. The ID is an arbitrary value and is needed as
correlation token between HB and HWSV. It will be generated by the
genHwsvMrwXml.pl
NEST_VDD_ID
non-volatile
0
Nest VDN Voltage Rail ID. The ID is an arbitrary value and is needed as
correlation token between HB and HWSV. It will be generated by the
genHwsvMrwXml.pl
NEST_VDN_ID
non-volatile
0
Nest VIO Voltage Rail ID. The ID is an arbitrary value and is needed as
correlation token between HB and HWSV. It will be generated by the
genHwsvMrwXml.pl
NEST_VIO_ID
non-volatile
0
The nominal core frequency in MHz.
This is the same for all cores in the system.
Data is provided by MVPD #V.
NOMINAL_FREQ_MHZ
volatile
ATTR_FREQ_CORE_NOMINAL_MHZ
DIRECT
NPU MMIO BAR base address values
creator: platform
consumer: proc_setup_bars
firmware notes:
64-bit address representing BAR RA
NOTE: BAR register covers RA 14:51
first dimension: unit number (0:3)
second dimension: BAR number (0:1)
NPU_MMIO_BAR_BASE_ADDR
non-volatile
4,2
0
ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR
DIRECT
NPU MMIO BAR size values
creator: platform
consumer: proc_setup_bars
firmware notes: none
first dimension: unit number (0:3)
second dimension: BAR number (0:1)
NPU_MMIO_BAR_SIZE
non-volatile
4,2
0
ATTR_PROC_NPU_MMIO_BAR_SIZE
DIRECT
Enumeration indicating the BAR size
used with ATTR_PROC_NPU_MMIO_BAR_SIZE
2_MB
0x0000000000200000
1_MB
0x0000000000100000
512_KB
0x0000000000080000
256_KB
0x0000000000040000
128_KB
0x0000000000020000
64_KB
0x0000000000010000
NPU_MMIO_BAR_SIZE
Numeric POD type test structure
physical:sys-0
Entity path for testing purposes
fsiPath
EntityPath
CHIP
Class for testing purposes
className
CLASS
0xAB
Test uint8
uint8
uint8_t
0xABCD
Test uint16
uint16
uint16_t
0xABCDEF01
Test uint32
uint32
uint32_t
0xABCDEF0123456789
Test uint64
uint64
uint64_t
-124
Test int8
int8
int8_t
-32764
Test int16
int16
int16_t
-2147483644
Test int32
int32
int32_t
-9223372036854775804
Test int64
int64
int64_t
Attribute which tests numeric POD types
NUMERIC_POD_TYPE_TEST
non-volatile
NVDIMM(s) are armed for backup incase of power loss (DDR Reset_n goes low)
This keeps track of the armed state
volatile-zeroed
Armed State
1
0
Is NVDIMM armed
armed
uint8_t
1
0
Is OCC active
occ_active
uint8_t
1
0
NVDIMM controller fatal error detected
fatal_error_detected
uint8_t
1
0
NVDIMM controller risky error detected
risky_error_detected
uint8_t
1
0
NVDIMM encryption error detected
encryption_error_detected
uint8_t
3
0
Reserved for future use
reserved
uint8_t
NVDIMM_ARMED
NVDIMM_AUTO_ARM
0 - Do not automatically arm all NVDIMMS in the system at runtime
1 - Automatically arm all NVDIMMS in the system at runtime
0
non-volatile
NVDIMM_ENCRYPTION_ENABLE
0 - Encryption is not enabled on all NVDIMMS in the system
1 - Encryption is enabled on all NVDIMMS in the system
0
non-volatile
NVDIMM_ENCRYPTION_KEYS_ANCHOR
NVDIMM Encryption keys
Bytes 0..31 Random String (RS)
Bytes 32..63 Erase Key (EK)
Bytes 64..95 Access Key (AK)
Set by HWSV, stored in anchor card
Should match NVDIMM_ENCRYPTION_KEYS_FW
96
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
non-volatile
NVDIMM_ENCRYPTION_KEYS_FW
NVDIMM Encryption keys
Bytes 0..31 Random String (RS)
Bytes 32..63 Erase Key (EK)
Bytes 64..95 Access Key (AK)
Set by Hostboot, stored in FSP flash
Should match NVDIMM_ENCRYPTION_KEYS_ANCHOR
96
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
non-volatile
NV_OPS_TIMEOUT_MSEC
NVDIMM timeout value for 6 main operations
0 - CSAVE
1 - Page Switch
2 - Restore
3 - ERASE
4 - ARM
5 - CHARGE
This attribute is set to volatile because the timeout values vary
depending on the vendor and capacity. The timeout values will be
determined during init by reading the i2c registers on the NV
controller.
The indices are defined in src/usr/isteps/nvdimm.H and the attribute
is consumed in nvdimm.C
6
0,0,0,0,0,0
volatile-zeroed
NV_STATUS_FLAG
NVDIMM status flag. This is used to record the status and
later report to OPAL/PHYP. Possible values:
0x01: Unable to preserve future contents
0x02: Failed to preserve contents
0x04: Contents preserved
0x08: Contents not preserved
0x10: Contents are encrypted
0x20: Reserved
0x40: Error detected, but save/restore might work
0x80: Reserved
0xFF: Memory is invalid
NOTE: set for virtual SCM devices, does not persist across reboot
0x08
volatile
OBUS_BRICK_LANE_MASK
Lane mask for which 8 lanes belong to this brick
This is a right justified 24-bit value. Only 8 of the
24 bits will be set representing the lanes belonging to
the associated brick.
Provided by the MRW.
non-volatile
OBUS_SLOT_INDEX
Position of the obus slot that the Obus brick is connected to
(represented in decimal). There is only one slot that a given
brick connects to and there are only 6 slots per proc,
so, we just need a single uint8_t representing the position
of the slot.
Provided by the MRW.
non-volatile
This attribute is to determine whether an occ is master capable.
An OCC is master capable if it's parent processor is wired to the
APSS.
OCC_MASTER_CAPABLE
non-volatile
0
DEFAULT_ALL
Enumeration for the various OCMB Firmware update behaviors
CHECK_VERSIONS
0
FORCE_UPDATE
1
PREVENT_UPDATE
2
CHECK_BUT_NO_UPDATE
3
OCMB_FW_UPDATE_BEHAVIOR
Force specific behavior for the OCMB Firmware update function.
OCMB_FW_UPDATE_OVERRIDE
volatile
2
Physical entity path an OMI's associated OMIC parent target
OMIC_PARENT
EntityPath
non-volatile
Ordinal ID of a target
ORDINAL_ID
non-volatile
0xFFFFFFFF
Rules on how to handle a deconfigure to parent level
PARENT_DECONFIG_RULES
non-volatile
Structure which defines a target's deconfigure rules.
Structure is read-only.
1
0
Are the rule bits set correctly?
valid
uint8_t
1
0
0b0: Target should NOT be deconfigured by child rollup
0b1: Target allowed to be deconfigured by child rollup
childRollupAllowed
uint8_t
1
0
0b0: Target should NOT rollup its deconfigure to its parent
0b1: Target should deconfigure its parent if no more functioning
children of same type exist for its parent
deconfigureParent
uint8_t
5
0
Reserved for future use
reserved
uint8_t
Physical entity path of the target's associated pervasive target
PARENT_PERVASIVE
EntityPath
non-volatile
Base address (target HRMOR) of the payload. Value is in MB.
PAYLOAD_BASE
volatile
256
The offset from base address of the payload entry-point.
Current default is 0x180
PAYLOAD_ENTRY
volatile
0x180
Indicate that payload should be placed in mirrored memory.
Set by the FSP based on the value of the registry key indicating
the memory mirroring mode.
PAYLOAD_IN_MIRROR_MEM
non-volatile
0
Attribute indicating what kind of payload is to be started.
PAYLOAD_KIND
non-volatile
PAYLOAD_KIND
UNKNOWN
Enumeration indicating what kind of payload is to be started
UNKNOWN
0
PHYP
1
SAPPHIRE
2
NONE
3
PAYLOAD_KIND
PCIE_32BIT_DMA_SIZE
PCIe slot 32bit DMA size definition
non-volatile
PCIE_32BIT_MMIO_SIZE
PCIe slot 32bit MMIO size definition
non-volatile
PCIE_64BIT_DMA_SIZE
PCIe slot 64bit DMA size definition
non-volatile
PCIE_64BIT_MMIO_SIZE
PCIe slot 64bit MMIO size definition
non-volatile
PCIE_CAPABILITES
Denotes the capabilites of this pcie slot
non-volatile
Base Address of PCI 32 bit Memory Space
PCI_BASE_ADDRS_32
non-volatile
4
Base Address of PCI 64 bit Memory Space
PCI_BASE_ADDRS_64
non-volatile
4
PCI_REFCLOCK_RCVR_TERM
Defines system specific value of PCI refclock receiver termination (FSI GP4 bits 10:11)
0
non-volatile
This attribute indicates if the PEC can be bifurcated. The value is determined from the workbook.
0 - PEC is not bifurcateable
1 - PEC can be bifurcated
Note: Altering the lane map can be done using the HX keyword.
PEC_IS_BIFURCATABLE
non-volatile
0
This attribute holds the contents of the HX keyword read by the FSP
from a PCIe card. The keyword data is used to determine the PHB
bifurcation settings.
byte 0 = Keyword Version
0x00 - Keyword not used, ignore remaining data
0x01 - Data describes this enitity's logical PCIe device
to physical PCIe lane mapping as one or more
logical devices, each connected to a set of PCIe
lanes (always an integral multiple of 8 lanes)
byte 1 = Number of x8 lane set entries X (0 to 7)
Each lane set entry is a one-byte value which indicates
whether the lane set is used by any logical device, and if
used, the logical device ID to which the lane set
is assigned, if this byte is zero the remaining keyword
data should be ignored.
bytes 2+N = Lane set entry N
where N={0,1..X-1}
Each lane set entry maps a set of physical lanes
(8*N through N*8+7) to a logical device. Bit 0 indicates
whether the lane set is used by a logical device. If used,
the next three bits indicate which logical device ID
uses those lanes.
Bit0:
0b0 = Lanes not used by a logical device; ignore
0b1 = Lanes used by a logical device; logical device
id below is valid
Bit 1-3:
0b000 = reserved (when bit 0 = 0b0)
0b001 -> 0b111
Bit 4-7
reserved
Example: bifurcate PEC into 2-x8 devices PHB3 and PHB4
HX keyword data kw = { 01 02 B0 C0 xx xx xx xx xx }
kw[0] = 01 - data is valid
kw[1] = 02 - there are two lane sets defined
kw[2] = B0 - b0 = 1 lane set 0xFF00 is used
b1:3 = 011 - lane set is assigned to device ID3
kw[3] = C0 - b0 = 1 lane set 0x00FF is used
b1:3 = 100 - lane set is assigned to device ID4
kw[4:8] - remaining data is ignored
Example: un-bifurcate a slot which is by default bifurcated
HX keyword data kw = { 01 02 B0 B0 xx xx xx xx xx }
kw[0] = 01 - data is valid
kw[1] = 02 - there are two lane sets defined
kw[2] = B0 - b0 = 1 lane set 0xFF00 is used
b1:3 = 011 - lane set is assigned to device ID3
kw[3] = B0 - b0 = 1 lane set 0x00FF is used
b1:3 = 011 - lane set is assigned to device ID3
kw[4:8] - remaining data is ignored
HX keyword data must map to a valid slot configuration as defined by
the system workbook.
PEC_PCIE_HX_KEYWORD_DATA
non-volatile
9
0
Effective PCIE IOP reversal configuration
Creator: Firmware
Purpose: Holds the effective PCIE IOP reversal value after taking into
account any IOP bifurcations. If no IOP bifurcations present, this
is just the value of the PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED
attribute.
Data Format: x4 array of uint8_t values. The first uint8_t value is
for lane set 0, the second for lane set 1 and so on. The given
index in the array is a mask which specifies which bit to invert
in the lane swap settings for the given PEC/lane set.
PEC_PCIE_IOP_REVERSAL
non-volatile
4
Base PCIE IOP reversal configuration
Creator: Firmware
Purpose: Holds the PCIE IOP reversal value for cases where the IOP
is bifurcated
Data Format: x4 array of uint8_t values. The first uint8_t value is
lane set 0, the second for lane set 2 and so on. The given index in
the array is a mask which specifies which bit to invert in the lane
swap settings for the given lane set
PEC_PCIE_IOP_REVERSAL_BIFURCATED
non-volatile
4
Base PCIE IOP reversal configuration
Creator: Firmware
Purpose: Holds the base PCIE IOP reversal value without considering IOP
bifurcation.
Data Format: x4 array of uint8_t values. The first uint8_t value is
for lane set 0, the second for lane set 1 and so on. The given
index in the array is a mask which specifies which bit to invert
in the lane swap settings for the given lane set.
PEC_PCIE_IOP_REVERSAL_NON_BIFURCATED
non-volatile
4
Bifurcated PCIE IOP swap configuration value
Creator: MRW
Purpose: Holds the base IOP swap configuration value for the IOPs in the
case where they are bifurcated. The swap value controls how PCIE
lanes are recordered when the leave the IOP, to provide lane routing
flexibility.
Data Format: A uint8_t value. The value specifices for the hardware how
to swap the PCIE lanes for the given PEC.
PEC_PCIE_IOP_SWAP_BIFURCATED
non-volatile
Base PCIE IOP swap configuration value
Creator: MRW
Purpose: Holds the base IOP swap configuration value without considering
IOP bifurcation. The swap value controls how PCIE lanes are
recordered when the leave the IOP, to provide lane routing
flexibility.
Data Format: A uint8_t value. The value specifices for the hardware how
to swap the PCIE lanes for the given PEC.
PEC_PCIE_IOP_SWAP_NON_BIFURCATED
non-volatile
PCIE Lane Mask bifurcated configuration
Creator: MRW
Purpose: Holds the PCIE lane mask assuming IOPs are bifurcated.
Data Format: x4 array of uint16_t values. The first uint8_t value is
lane set 0, the second for lane set 2 and so on. A lane set mask
indicates which groups of lanes are assigned to an IOP. For
instance, lane set 0 value of 0xFF00 and lane set 1 value of 0x00FF
means the IOP is bifurcated into two x8s.
PEC_PCIE_LANE_MASK_BIFURCATED
non-volatile
4
PCIE Lane Mask base configuration
Creator: MRW
Purpose: Holds the base PCIE lane mask assuming no dynamic IOP
bifurcations.
Data Format: x4 array of uint16_t values. The first uint8_t value is
lane set 0, the second for lane set 2 and so on. A lane set mask
indicates which groups of lanes are assigned to an IOP. For
instance, lane set 0 value of 0xFFFF and lane set 1 value of 0x0000
means the PEC is a x16. Lane set 0 value of 0xFF00 and lane
set 1 value of 0x00FF, means the PEC is split into two x8s.
PEC_PCIE_LANE_MASK_NON_BIFURCATED
non-volatile
4
Entity path of the peer target of a bus target
PEER_PATH
EntityPath
physical:na
non-volatile
Peer target's address of a A/X-bus connection.
NULL means address 0 for no peer target. If a
target instance overrides the default with the
peer target's PHYS_PATH. The target compiler will
convert the valid PHYS_PATH string into the runtime
virtual address of the peer target instance.
PEER_TARGET
non-volatile
NULL
Enumeration indicating the OFF setting for the core and cache chiplet
VCS PFET controllers
NOOFF
0
ALLBUT1TO7OFF
1
ALLBUT2TO7OFF
2
ALLBUT3TO7OFF
3
ALLBUT4TO7OFF
4
ALLBUT5TO7OFF
5
ALLBUT6TO7OFF
6
ALLBUT7TO7OFF
7
ALLOFF
8
PFET_VCS_VOFF_SEL
Enumeration indicating the OFF setting for the core and cache chiplet
DD PFET controllers
NOOFF
0
ALLBUT1TO7OFF
1
ALLBUT2TO7OFF
2
ALLBUT3TO7OFF
3
ALLBUT4TO7OFF
4
ALLBUT5TO7OFF
5
ALLBUT6TO7OFF
6
ALLBUT7TO7OFF
7
ALLOFF
8
PFET_VDD_VOFF_SEL
PG
Chiplet Partial good info attribute. Provided by Ring scans
volatile-zeroed
ATTR_PG
DIRECT
Base Address of PHB Register Space
PHB_BASE_ADDRS
non-volatile
4
0xFFFFFFFFFFFFFFFF,
0xFFFFFFFFFFFFFFFF,
0xFFFFFFFFFFFFFFFF,
0xFFFFFFFFFFFFFFFF
Physical hierarchical path to the target
PHYS_PATH
EntityPath
non-volatile
PIB_I2C_NEST_PLL
i2c pll for the system
default is 0x26 (For PIB @500 MHz (2 GHz nest)) for
I2C speed = ~1Mhz per Andreas Koenig.
0x026
volatile
PIB_I2C_REFCLOCK
i2c reference clock for the system.
default is 0x4 => I2C speed = ~1Mhz per Andreas Koenig
0x4
volatile
Set to 1 by HWSV to indicate that attribute overrides exist in a PLCK IPL
(not an IPL by steps). This is read by Hostboot to determine if it needs
to request the attribute overrides from HWSV before starting its IPL.
PLCK_IPL_ATTR_OVERRIDES_EXIST
non-volatile
0x00
Save state of the sfc driver flash workarounds for runtime
PNOR_FLASH_WORKAROUNDS
volatile-zeroed
0
Position of target relative to node
POSITION
non-volatile
0
POS_ON_MEM_PORT
Position of this DIMM on its memory port
0
non-volatile
Hierarchical path to the target with respect to power
POWER_PATH
EntityPath
non-volatile
PRD_HWP_PLID
PRD will perform error isolation for certain errors that may cause a HWP
to fail. This attribute will be used by the HWP to store the PLID so that
PRD can subsequently check it for a non-zero value and link the HWP PLID
to the PRD error log.
0
volatile-zeroed
Tracks if a specific core has previously experienced a timeout during
initial activation.
0 = No previous errors reported;
1 = Core failed on the last attempt to be started
PREVIOUS_WAKEUP_FAIL
non-volatile
0
Structure which defines a target's primary capabilities.
A target can only support at most FSI SCOM and one of the other two SCOM
types. Applicable for all targets. Structure is read-only.
1
0
0b0: Target does not support FSI SCOM;
0b1: Target supports FSI SCOM
supportsFsiScom
uint8_t
1
0
0b0: Target does not support XSCOM;
0b1: Target supports FSI XSCOM
supportsXscom
uint8_t
1
0
0b0: Target does not support inband SCOM
supportsInbandScom
uint8_t
5
0
Reserved for future use
reserved
uint8_t
Attribute which describes capabilities of a target
PRIMARY_CAPABILITIES
non-volatile
Required Processor Compatibility Setting
PROC_COMPATIBILITY_REQ
non-volatile
PROC_COMPATIBILITY_REQ
ALLOW_COMPATIBILITY
Enumeration specifying the compatibility setting for Processor ECs
ALLOW_COMPATIBILITY = set RISK_LEVEL to best allowed
FORCED_COMPATIBILITY = set RISK_LEVEL to a compatible level
FORCED_NATIVE = set RISK_LEVEL to ECs native setting
ALLOW_COMPATIBILITY
0
FORCED_COMPATIBILITY
1
FORCED_NATIVE
2
PROC_COMPATIBILITY_REQ
PROC_DCM_INSTALLED
PROC_CHIP Attribute
If true, the chip is installed on a Dual Chip Module
Provided by the Machine Readable Workbook
non-volatile
Enumeration indicating the PROC_EPS_TABLE_TYPE
EPS_TYPE_LE
1
EPS_TYPE_HE
2
PROC_EPS_TABLE_TYPE
Enumeration indicating the PROC_FABRIC_A_BUS_WIDTH
2_BYTE
1
4_BYTE
2
PROC_FABRIC_A_BUS_WIDTH
Enumeration indicating the PROC_FABRIC_CAPI_MODE
OFF
0x0
ON
0x1
PROC_FABRIC_CAPI_MODE
Enumeration indicating the PROC_FABRIC_PUMP_MODE
MODE1
1
MODE2
2
PROC_FABRIC_PUMP_MODE
Enumeration indicating the PROC_FABRIC_SMP_OPTICS_MODE
OPTICS_IS_X_BUS
0x0
OPTICS_IS_A_BUS
0x1
PROC_FABRIC_SMP_OPTICS_MODE
Enumeration indicating the PROC_FABRIC_X_BUS_WIDTH
2_BYTE
1
4_BYTE
2
PROC_FABRIC_X_BUS_WIDTH
Type of Master, ACTING_MASTER or MASTER_CANDIDATE or
NOT_MASTER
PROC_MASTER_TYPE
non-volatile
NOT_MASTER
NOT_MASTER
Enumeration indicating the role of proc as master/alt_master/not_master
ACTING_MASTER
0
MASTER_CANDIDATE
1
NOT_MASTER
2
PROC_MASTER_TYPE
Enumeration indicating which _PBIEX_ASYNC_SEL should be use
SEL0
0
SEL1
1
SEL2
2
PROC_PBIEX_ASYNC_SEL
PROC_PCIE_IOP_CONFIG
PCIE IOP lane configuration
creator: platform
consumer: proc_pcie_scominit
firmware notes:
Encoded PCIE IOP lane configuration
non-volatile
ATTR_PROC_PCIE_IOP_CONFIG
DIRECT
PROC_PCIE_IOVALID_ENABLE
PCIE iovalid enable valid mask
creator: platform
consumer: p9_pcie_scominit
volatile-zeroed
ATTR_PROC_PCIE_IOVALID_ENABLE
DIRECT
Indicates whether PCIE lanes terminate at a pluggable slot
Creator: MRW
Purpose: Used by FW to know whether the given PCIE lanes terminate at a
pluggable slot or not. If this is the case, and the platform
supports bifurcation, the card's VPD should be interrogated to
determine whether to bifurcate the IOP or not.
Data Format: x4 array of uint8_t values. The first value indicates
whether lane set 0 terminates at a pluggable slot. The
next three values indicate the same for lane sets 1-3. A value of
1 at a given array index indicates the lanes terminate at a
pluggable slot, 0 otherwise.
PROC_PCIE_IS_SLOT
non-volatile
4
PCIE Lane Equalization values for each PHB
Creator: MRW
Purpose: Holds settings which are loaded into the HW to optimize the
PCIE lane signal eye between the chips + PCIE Gen3 endpoints
Data Format: 16 entries of 16 bytes of EQ data per PHB. Each PHB has an EQ
value for each of its 16 lanes. Each value is a uint16 formatted as
follows:
Bit 0:3 - up_rx_hint (bit 0 reserved)
Bit 4:7 - up_tx_preset
Bit 8:11 - dn_rx_hint (bit 0 reserved)
Bit 12:15 - dn_tx_preset
PROC_PCIE_LANE_EQUALIZATION_GEN3
non-volatile
16
0x7777,0x7777,0x7777,0x7777,
0x7777,0x7777,0x7777,0x7777,
0x7777,0x7777,0x7777,0x7777,
0x7777,0x7777,0x7777,0x7777
PCIE Lane Equalization values for each PHB
Creator: MRW
Purpose: Holds settings which are loaded into the HW to optimize the
PCIE lane signal eye between the chips + PCIE Gen4 endpoints
Data Format: 16 entries of 16 bytes of EQ data per PHB. Each PHB has an EQ
value for each of its 16 lanes. Each value is a uint16 formatted as
follows:
Bit 0:3 - up_rx_hint (bit 0 reserved)
Bit 4:7 - up_tx_preset
Bit 8:11 - dn_rx_hint (bit 0 reserved)
Bit 12:15 - dn_tx_preset
PROC_PCIE_LANE_EQUALIZATION_GEN4
non-volatile
16
0x7777,0x7777,0x7777,0x7777,
0x7777,0x7777,0x7777,0x7777,
0x7777,0x7777,0x7777,0x7777,
0x7777,0x7777,0x7777,0x7777
Effective PCIE Lane Mask
Creator: Firmware
Purpose: Holds the effective PCIE lane mask of each PEC after taking
into account any IOP bifurcations. If no IOP bifurcations present,
this is just the value of the PEC_PCIE_LANE_MASK_NON_BIFURCATED
attribute
Data Format: x4 array of uint16_t values. The uint16_t value is a
mask for lane 0, the next for lane 1 and so on until lane 3.
A lane set mask indicates which groups of lanes are assigned to an
IOP. For instance, lane set 0 value of 0xFFFF and lane set 1 value
of 0x0000 for PEC0 means PEC0 is a x16. Lane set 0 value of 0xFF00
and lane set 2 value of 0x00FF for PEC0, means the IOP is bifurcated
into two x8s.
PROC_PCIE_LANE_MASK
non-volatile
4
PROC_PCIE_NUM_PEC
creator: platform
Number of PCIe PEC units present on target
Nimbus: 3
non-volatile
PROC_PCIE_PCS_RX_LOFF_CONTROL
PCS rx loff control
creator: platform
consumer: p9_pcie_scominit
firmware notes:
The value of rx loff control for PCS.
Array index: Configuration number
index 0~3 for CONFIG0~3
4
non-volatile
PROC_PCIE_PCS_RX_PHASE_ROTATOR_CNTL
Value of PCS rx phase rotator control
creator: platform
consumer: p9_pcie_scominit
non-volatile
PROC_PCIE_PCS_RX_SIGDET_CNTL
Value of PCS rx sigdet control
creator: platform
consumer: p9_pcie_scominit
non-volatile
PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3
PCS rx vga control register3
creator: platform
consumer: p9_pcie_scominit
firmware notes:
The value of rx vga control register3.
Array index: Configuration number
index 0~3 for CONFIG0~3
4
non-volatile
PROC_PCIE_PCS_SYSTEM_CNTL
Value of PCS system control
creator: platform
consumer: p9_pcie_scominit
non-volatile
ATTR_PROC_PCIE_PCS_SYSTEM_CNTL
DIRECT
PROC_PCIE_PCS_TX_FIFO_CONFIG_OFFSET
Value of PCS tx fifo config offset
creator: platform
consumer: p9_pcie_scominit
non-volatile
PROC_PCIE_PHB_ACTIVE
PCIE PHB valid mask
creator: platform
consumer: proc_pcie_scominit
firmware notes:
Bit mask defining set of active/valid PHBs
bit0=PHB0, bit1=PHB1, bit2=PHB2, bit3=PHB3
non-volatile
PROC_PCIE_REFCLOCK_ENABLE
PCIE refclock enable valid mask
PCIE refclock enable valid mask
creator: platform
consumer: p9_pcie_scominit
volatile-zeroed
ATTR_PROC_PCIE_REFCLOCK_ENABLE
DIRECT
PROC_REFCLOCK_RCVR_TERM
Defines system specific value of processor refclock receiver termination (FSI GP4 bits 8:9)
0
non-volatile
Enumeration indicating which chip should be used as the PROC_SELECT_BOOT_MASTER
PRIMARY
1
SECONDARY
2
PROC_SELECT_BOOT_MASTER
Enumeration indicating which SEEPROM image should be used to boot a processor
FIRST
1
SECOND
2
PROC_SELECT_BOOT_SEEPROM_IMAGE
PROC_SELECT_BOOT_SEEPROM_IMAGE
Specifies which SEEPROM image should be used to boot a processor
FIRST - the first image was selected
SECOND - the second image was selected
1
volatile
ATTR_PROC_SELECT_BOOT_SEEPROM_IMAGE
DIRECT
Enumeration indicating which SEEPROM image should be used for the boot master
FIRST
1
SECOND
2
PROC_SELECT_SEEPROM_IMAGE
PROC_SELECT_SEEPROM_IMAGE
Specifies which SEEPROM image should be used for the boot master.
FIRST - the first image was selected
SECOND - the second image was selected
Platforms are expected to set this to FIRST in normal operation
1
volatile
Base Address of PSI Bridge Logic
PSI_BRIDGE_BASE_ADDR
volatile-zeroed
0xFFFFFFFFFFFFFFFF
ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR
DIRECT
PSIHB - ESB space address - MMIO consumed by PHYP
PSI_HB_ESB_ADDR
volatile-zeroed
Raw value of system MTM
RAW_MTM
volatile-zeroed
64
The number of reconfig loops allowed due to RCD parity errors when
recovery is disabled. PRD will make a predictive callout and stop issuing
reconfigs due to RCD parity errors when RCD_PARITY_RECONFIG_LOOP_COUNT is
greater than this value. A value of 0 indicates that no reconfig loops are
allowed due to RCD parity errors.
RCD_PARITY_RECONFIG_LOOPS_ALLOWED
non-volatile
1
PRD will increment this count and issue a reconfig loop each time an RCD
parity error (recovery disabled) is detected during Memory Diagnostics.
This value will be cleared at the end of Memory Diagnostics if it is able
to complete without the need to issue a reconfig loop.
RCD_PARITY_RECONFIG_LOOP_COUNT
non-volatile
0
Enumeration of RECONFIGURE_LOOP flags
Indicates HW has been deconfigured
DECONFIGURE
0x01
Indicates a bad DQ bit was set in the BadDqBitmap
BAD_DQ_BIT_SET
0x02
An RCD parity error has been detected
RCD_PARITY_ERROR
0x04
RECONFIGURE_LOOP
System attribute array that defines the reconfig loop test cases
consumer: istep dispatcher reconfigLoopTestRunner function
This array is loaded with data via attribute override. The attribute is
then read and then overlayed onto a test case structure.
RECONFIG_LOOP_TESTS
volatile-zeroed
5
Indicates whether reconfigure loop tests are enabled.
This attribute is set via attribute override
RECONFIG_LOOP_TESTS_ENABLE
volatile-zeroed
REDUNDANT_CLOCKS
1 = System has redundant clock oscillators
0 = System does not have redundant clock oscillators
From the Machine Readable Workbook
non-volatile
REL_POS
Logical position of this unit/dimm relative to its immediate parent
0xFF
non-volatile
ATTR_REL_POS
DIRECT
Used to tell if a resource is critical to perform an IPL. If this
attribute is set to 1 and the target is deconfigured, the IPL MUST
terminate.
RESOURCE_IS_CRITICAL
non-volatile
0
Where did the RISK_LEVEL setting originate?
This is used to make sure the MRW isn't setting an invalid level
for FORCED_COMPATIBILITY.
RISK_LEVEL_ORIGIN
volatile-zeroed
RISK_LEVEL_ORIGIN
USER
Enumeration specifying what was used to setup the RISK_LEVEL
USER
0
MRW
1
RISK_LEVEL_ORIGIN
Size of RNG IO Region
RNG_BAR_SIZE
non-volatile
0x000000000001000
Base Address of RNG IO Region
RNG_BASE_ADDR
non-volatile
0xFFFFFFFFFFFFFFFF
ATTR_PROC_NX_MMIO_BAR_BASE_ADDR
DIRECT
Policy indicating whether to perform the maximum amount of memory
pattern testing possible or not.
Set to 0x01 to perform the maximum amount of memory pattern testing
possible.
Set to 0x00 to perform the default amount of memory pattern testing.
RUN_MAX_MEM_PATTERNS
non-volatile
0
uint8_t attribute to be used for storing functional state of a target during
test cases.
SAVED_STATE_UINT8
volatile-zeroed
SBE_COMMIT_ID
A hexadecimal value of the commit ID associated
with the SBE.
volatile-zeroed
SBE_IS_STARTED
If 0, SBE for the processor has not been started.
Otherwise, SBE for the processor has been started.
0
volatile-zeroed
SBE_RELEASE_TAG
An ascii value of the SBE release tag
21
volatile-zeroed
SBE_UPDATE_DISABLE
Control execution of updateProcessorSbeSeeproms()
if 0, enable SBE update of processor SEEPROM
if 1, disable SBE update of processor SEEPROM
Consumer: sbe_update.C
Default: 0
0
non-volatile
SBE_VERSION_INFO
A hexadecimal value of the major and minor
version of the SBE. The major info is in the
first 16 bits followed by the minor.
0:15: Major Version
16:31: Minor Version
volatile-zeroed
Structure which defines which SCOM to use at a point in
time. Only applicable if target supports one or more SCOM types. Only
one bit (of the first three) can ever be set at any one time.
1
0
0b0: Do not use FSI SCOM at this time. 0b1: Use FSI
SCOM at this time
useFsiScom
uint8_t
1
0
0b0: Do not use XSCOM at this time. 0b1: Use XSCOM at
this time
useXscom
uint8_t
1
0
0b0: Do not use inband SCOM at this time. 0b1: Use
inband SCOM at this time
useInbandScom
uint8_t
1
0
0b0: Do not use SBE SCOM at this time. 0b1: Use
SBE SCOM at this time
useSbeScom
uint8_t
1
0
0b0: Do not use I2C SCOM at this time.
0b1: Use I2C SCOM at this time
useI2cScom
uint8_t
3
0
Reserved for future expansion
reserved
uint8_t
Attribute storing information about which SCOM path to use
SCOM_SWITCHES
volatile
SECUREBOOT_PROTECT_DECONFIGURED_TPM
To deconfigure a TPM in a secure system - 01 to set TDP bit
volatile-zeroed
ATTR_SECUREBOOT_PROTECT_DECONFIGURED_TPM
DIRECT
SLOT_INDEX
PCIe slot index definition
non-volatile
SLOT_NAME
PCIe slot name definition
non-volatile
SOCKET_POWER_NOMINAL
The socket power in nominal mode.
Controls how much power can be used.
This is the same for all cores in the system.
Data is provided by MVPD #V.
volatile-zeroed
SOCKET_POWER_TURBO
The socket power in turbo mode.
Controls how much power can be used.
This is the same for all cores in the system.
Data is provided by MVPD #V.
volatile-zeroed
Structure which defines a system's SP functions.
Applicable for System target only. Structure is read-only.
Default values match OpenBMC implementation.
1
0
If this flag is set then mailboxEnabled MUST also be set
0b0: SP does not support for VPD, payload, ATTR sync, VDDR, TOD;
0b1: SP supports VPD, payload, ATTR sync, VDDR, TOD
baseServices
uint32_t
1
0
0b0: SP does not initialize FSI slave logic, Hostboot must;
0b1: SP does initialize FSI slave logic so Hostboot should not
fsiSlaveInit
uint32_t
1
0
0b0: There is no SP mailbox support;
0b1: There is SP mailbox support
mailboxEnabled
uint32_t
1
0
0b0: SP does not initialize FSI master logic, Hostboot must;
0b1: SP does initialize FSI master logic so Hostboot should not
fsiMasterInit
uint32_t
1
0
0b0: SP does not perform hardware change detection, Hostboot must;
0b1: SP does perform hardware change detection (HCDB) so Hostboot should not
hardwareChangeDetection
uint32_t
1
0
0b0: SP does not perform Power Line Disturbance (PLD) detection, Hostboot must;
0b1: SP does perform Power Line Disturbance (PLD) detection so Hostboot should not
powerLineDisturbance
uint32_t
26
0
Reserved for future use
reserved
uint32_t
Attribute which describes what the SP is or is not doing in this system
SP_FUNCTIONS
non-volatile
START_MEM_ADDRESS_FOR_PAYLOAD_TCE_TOKEN
Specifies the starting memory address that corresponds to the TCE Token
used by the FSP to transfer the PAYLOAD into system memory.
If 0xFFFFFFFFFFFFFFFF, then invalid; otherwise, valid.
0xFFFFFFFFFFFFFFFF
volatile
STOP5_DISABLE
Control CME response to execution of PowerPC STOP instruction
if OFF, treat STOP5 as STOP5
if ON, treat STOP5 as STOP4
Producer: ???
Consumer: p8_hcode_image_build.C
Platform default: OFF
0
non-volatile
ATTR_STOP5_DISABLE
DIRECT
NA
Enumeration indication which Hot Plug Controllers are supported by
the current system.
NA
0
MAX5961
0x01
PCA9551
0x02
SUPPORTED_HOT_PLUG
STOP levels supported at runtime (sent to Host via HDAT):
Bit 0: STOP0 Supported - Quiesce thread only
Bit 1: STOP1 Supported - P8 Nap
Bit 2: STOP2 Supported - P8 Fast Sleep
Bit 3: STOP3 Supported - P8 Fast Sleep using iVRMs
Bit 4: STOP4 supported - P8 Deep Sleep
Bit 5: STOP5 Supported - WOF-friendly "Instant on"
Bit 6,7: Reserved
Bit 8: STOP8 supported - Half Quad Sleep
Bit 9: STOP9 supported - P8 Fast Winkle
Bit 10: Reserved
Bit 11: STOP11 supported - P8 Deep Winkle
Bit 12-15 : Reserved
Bits 16..31 - Reserved
SUPPORTED_STOP_STATES
non-volatile
0xEC100000
Do we support dynamically updating memory voltages?
0 = no, 1 = yes
SUPPORTS_DYNAMIC_MEM_VOLT
non-volatile
0
SYNC_BETWEEN_STEPS
Attribute to enable targetting attribute sync when in istep mode.
1 = sync will occur following each substep when ipl'ing in single step mode
0 = sync will not be done after each step
volatile-zeroed
This field is of the form "vendor,name" where the name indicates
the family of the systems. The textual portion of the string has
a maximum length of 63 characters to accommodate a terminating NULL.
Both vendor and name fields are lower case US ASCII. No special
characters other than ",", "-", and "+" as described below should
be used in the string.
SYSTEM_FAMILY
non-volatile
ibm,p9
64
This field is of the form ?vendor,type? where the type indicates
a type of system within the System Family. The textual portion of
the string has a maximum length of 63 characters to accommodate a
terminating NULL. Both vendor and name fields are lower case US
ASCII. No special characters other than ",", "-", and "+" as described
below should be used in the string. If identification of specific
models within a system type is desired, "-model" should be appended
to the end of the name. The "-model" portion is optional and could be
used to identify the packaging, specific model numbers, etc.
NOTE: No Hostboot code should ever key off of this value.
SYSTEM_TYPE
non-volatile
ibm,miscopenpower
64
TCE_START_TOKEN_FOR_HDAT
Specifies which TCE Token the FSP should start with to transfer the
HDAT section into system memory.
If 0xFFFFFFFF, then invalid; otherwise, valid.
0xFFFFFFFF
volatile
TCE_START_TOKEN_FOR_PAYLOAD
Specifies which TCE Token the FSP should start with to transfer the
PAYLOAD into system memory.
If 0xFFFFFFFF, then invalid; otherwise, valid.
0xFFFFFFFF
volatile
Structure to define the addressing for an I2C
slave device.
physical:sys-0
Entity path to the chip that contains the I2C
master
i2cMasterPath
EntityPath
0x80
I2C master engine. This is a 2-bit
value.
engine
uint8_t
0x80
Port from the I2C Master device. This is a 6-bit
value.
port
uint8_t
0x80
Device address on the I2C bus. This is a 7-bit value,
but then shifted 1 bit left.
devAddr
uint8_t
0xFF
Determines which of the N selectable buses the mux
will connect to. OxFF indicates no mux present
or N/A.
i2cMuxBusSelector
uint8_t
physical:sys-0
Entity path to the I2C mux for this device.
i2cMuxPath
EntityPath
Information needed to address an I2C slave device
TEMP_SENSOR_I2C_CONFIG
non-volatile
Test attribute; largest string possible given size
TEST_MAX_STRING
volatile
abc
4
Test attribute; smallest string possible given size
TEST_MIN_STRING
volatile
a
10
Attribute to test signed attribute
functionality in the system
TEST_NEGATIVE_FCN
non-volatile
-6
Test attribute; string with no default supplied
TEST_NO_DEFAULT_STRING
volatile
10
Test attribute; string with empty default value
TEST_NULL_STRING
volatile
10
Thread Count
THREAD_COUNT
non-volatile
0x4
Time Base frequency in MHZ
TIME_BASE
non-volatile
0x800000
TLB Data Associative Sets
TLB_DATA_ASSOC_SETS
non-volatile
TLB Data Entries
TLB_DATA_ENTRIES
non-volatile
TLB Instruction Associative Sets
TLB_INSTR_ASSOC_SETS
non-volatile
TLB Instruction Entries
TLB_INSTR_ENTRIES
non-volatile
Reserve Size in bytes
TLB_RESERVE_SIZE
non-volatile
TOD CHIP DATA for each CHIP
The size of the TOD CHIP DATA must be equal to the sizeof(TodChipData)
TOD_CPU_DATA
volatile-zeroed
44
Bitmask indicating what role this chip has in tod topology
TOD_ROLE
volatile-zeroed
NON_MASTER
Enumeration indicating what role this chip has in tod topology
NON_MASTER
0
PRIMARY
1
SECONDARY
2
TOD_ROLE
Structure to define the addressing for an I2C
TPM.
0x0
Boolean indicating whether this TPM is available
in the system
tpmEnabled
uint8_t
physical:sys-0
Entity path to the chip that contains the I2C
master
i2cMasterPath
EntityPath
0x01
Port from the I2C Master device. This is a 6-bit
value.
port
uint8_t
0xAE
Device address on the I2C bus for Locality 0.
This is a 7-bit value, but then shifted 1
bit left.
devAddrLocality0
uint8_t
0xA8
Device address on the I2C bus for Locality 1.
This is a 7-bit value, but then shifted 1
bit left.
devAddrLocality1
uint8_t
0xAA
Device address on the I2C bus for Locality 2.
This is a 7-bit value, but then shifted 1
bit left.
devAddrLocality2
uint8_t
0xA4
Device address on the I2C bus for Locality 3.
This is a 7-bit value, but then shifted 1
bit left.
devAddrLocality3
uint8_t
0xA6
Device address on the I2C bus for Locality 4.
This is a 7-bit value, but then shifted 1
bit left.
devAddrLocality4
uint8_t
0x00
I2C master engine. This is a 2-bit
value.
engine
uint8_t
0x01
The number of bytes a device requires to set its
internal address/offset.
byteAddrOffset
uint8_t
0xFF
Determines which of the N selectable buses the mux
will connect to. OxFF indicates no mux present
or N/A.
i2cMuxBusSelector
uint8_t
physical:sys-0
Entity path to the I2C mux for this device.
i2cMuxPath
EntityPath
Information needed to address the TPM slaves
TPM_INFO
non-volatile
TPM_POISONED
A flag indicating whether the TPM has been poisoned. A poisoned TPM
has a random number extended into its PCR but not mirrorred to its
log. That creates a disconnection between the TPM and its log, which
in turn makes it impossible to perform remote attestation on the TPM.
0
1
0
volatile-zeroed
Setting to require(0x1) or not require(0x0) a functional TPM to
boot the system.
TPM_REQUIRED
non-volatile
1
0
1
TPM_UNUSABLE
Indicates whether the TPM is unusable. Hostboot should not read this
value for any purpose other than tracing. This value should only be
written to when there is a certainty that the TPM is not usable.
This attribute is consumed by FSP during alignment check to determine
the optimal boot configuration. This attribute can be removed if TPM
gard is ever supported.
0
1
0
non-volatile
Attribute indicating the target's type
TYPE
non-volatile
TYPE
NA
Enumeration indicating the target's type
NA
0
SYS
1
NODE
2
DIMM
3
MEMBUF
4
PROC
5
EX
6
CORE
7
L2
8
L3
9
L4
10
MCS
11
MBA
13
XBUS
14
ABUS
15
PCI
16
DPSS
17
APSS
18
OCC
19
PSI
20
FSP
21
PNOR
22
OSC
23
TODCLK
24
CONTROL_NODE
25
OSCREFCLK
26
OSCPCICLK
27
REFCLKENDPT
28
PCICLKENDPT
29
NX
30
PORE
31
PCIESWITCH
32
CAPP
33
FSI
34
EQ
35
MCA
36
MCBIST
37
MI
38
DMI
39
OBUS
40
SBE
42
PPE
43
PERV
44
PEC
45
PHB
46
SYSREFCLKENDPT
47
MFREFCLKENDPT
48
TPM
49
SP
50
UART
51
PS
52
FAN
53
VRM
54
USB
55
ETH
56
PANEL
57
BMC
58
FLASH
59
SEEPROM
60
TMP
61
GPIO_EXPANDER
62
POWER_SEQUENCER
63
RTC
64
FANCTLR
65
OBUS_BRICK
66
NPU
67
MC
68
TEST_FAIL
69
MFREFCLK
70
SMPGROUP
71
OMI
72
MCC
73
OMIC
74
OCMB_CHIP
75
MEM_PORT
76
I2C_MUX
77
PMIC
78
LAST_IN_RANGE
79
TYPE
UCD_MFR_REVISION_OVERRIDE
If non-zero then use value as the discovered MFR_REVISION value from
the UCD device rather than the actual value from the device.
0
volatile
The ultra turbo frequency in MHz.
This is the same for all cores in the system.
Data is provided by MVPD #V and is calculated as
the minimum of the ultra turbo frequencies.
ULTRA_TURBO_FREQ_MHZ
volatile
ATTR_ULTRA_TURBO_NOMINAL
DIRECT
USE_TCES_FOR_DMAS
Specifies whether or not the FSP is ready for Hostboot to enable TCEs
for DMAs for the given IPL. This is a temporary attribute which will
be used to phase-in TCE support.
If 0, DO NOT use TCEs;
If 1, use TCEs
1
volatile
Memory VCS voltage domain ID. All memory buffers in the same VCS
voltage domain will share the same ID. IDs are arbitrarily assigned,
used for correlation between HB + HWSV, and are generated by
genHwsvMrwXml.pl
VCS_ID
non-volatile
0
Voltage Memory Rail Manager ID. Currently HB only needs
to configured the Vddr voltage rail manager during the IPL. The ID
is an arbitary value and needed as correlation token between HB and
HWSV. It will be generated by the genHwsvMrwXml.pl.
VDDR_ID
non-volatile
0
Memory VDD voltage domain ID. All memory buffers in the same VDD
voltage domain will share the same ID. IDs are arbitrarily assigned,
used for correlation between HB + HWSV, and are generated by
genHwsvMrwXml.pl
VDD_ID
non-volatile
0
Enumeration for Voltage Drop Monitor enable
OFF
0x00
ON
0x01
VDM_ENABLE
VENDOR_ID
PCIe vendor ID definition
non-volatile
Record offset for this target's VPD
VPD_REC_NUM
non-volatile
0xFFFF
Memory VPP voltage domain ID. All memory buffers in the same VPP
voltage domain will share the same ID. IDs are arbitrarily assigned,
used for correlation between HB + HWSV, and are generated by
genHwsvMrwXml.pl
VPP_ID
non-volatile
0
System control to set the power limit for Workload Optimized
Frequency (WOF) algorithms. This is used to select the
proper VFRT tables.
Producer: TMGT
Consumers: FW that selects VFRT tables
WOF_POWER_LIMIT
non-volatile
0
Enumeration to select WOF Power Limit
NOMINAL
0
TURBO
1
WOF_POWER_LIMIT
WOF_TABLE_LID_NUMBER
LID id used to load tables for Workload Optimized
Frequency (WOF) algorithms.
Producer: TMGT
Consumers: FW that selects VFRT tables
0x81E00440
non-volatile
XIVE - Controller Bar address
MMIO consumed by PHYP
XIVE_CONTROLLER_BAR_ADDR
volatile-zeroed
XIVE - Thread Management Bar address register 1
MMIO consumed by HB/PHYP
XIVE_THREAD_MGMT1_BAR_ADDR
volatile-zeroed
XSCOM base address
XSCOM_BASE_ADDRESS
volatile