ATTR_EXECUTION_PLATFORM
TARGET_TYPE_SYSTEM
Which execution platform the HW Procedure is running on
Some HWPs (e.g. special wakeup) use different registers for different
platforms to avoid arbitration problems when multiple platforms do
the same thing concurrently
uint8
HOST = 0x01, FSP = 0x02, OCC = 0x03
ATTR_IS_SIMULATION
TARGET_TYPE_SYSTEM
env: 1 = Awan/HWSimulator. 0 = Simics/RealHW.
uint8
ATTR_IS_MPIPL_HB
TARGET_TYPE_SYSTEM
1 = in Memory Preserving IPL mode. 0 = in normal IPL mode.
uint8
ATTR_MNFG_FLAGS
TARGET_TYPE_SYSTEM
The manufacturing flags.
This is a bitfield. Each bit is a flag and multiple flags can be set
uint64
MNFG_NO_FLAG = 0x0000000000000000,
MNFG_THRESHOLDS = 0x0000000000000001,
MNFG_AVP_ENABLE = 0x0000000000000002,
MNFG_HDAT_AVP_ENABLE = 0x0000000000000004,
MNFG_SRC_TERM = 0x0000000000000008,
MNFG_IPL_MEMORY_CE_CHECKINGE = 0x0000000000000010,
MNFG_FAST_BACKGROUND_SCRUB = 0x0000000000000020,
MNFG_TEST_DRAM_REPAIRS = 0x0000000000000040,
MNFG_DISABLE_DRAM_REPAIRS = 0x0000000000000080,
MNFG_ENABLE_EXHAUSTIVE_PATTERN_TEST = 0x0000000000000100,
MNFG_ENABLE_STANDARD_PATTERN_TEST = 0x0000000000000200,
MNFG_ENABLE_MINIMUM_PATTERN_TEST = 0x0000000000000400,
MNFG_DISABLE_FABRIC_eREPAIR = 0x0000000000000800,
MNFG_DISABLE_MEMORY_eREPAIR = 0x0000000000001000,
MNFG_FABRIC_DEPLOY_LANE_SPARES = 0x0000000000002000,
MNFG_DMI_DEPLOY_LANE_SPARES = 0x0000000000004000,
ATTR_PROC_EPS_TABLE_TYPE
TARGET_TYPE_SYSTEM
Processor epsilon table type. Used to calculate the processor nest
epsilon register values.
Provided by the Machine Readable Workbook.
uint8
EPS_TYPE_LE = 0x01, EPS_TYPE_HE = 0x02
ATTR_PROC_FABRIC_PUMP_MODE
TARGET_TYPE_SYSTEM
Processor SMP Fabric broadcast scope configuration.
MODE1 = default = chip/group/system/remote group/foreign.
MODE2 = group/system/remote group/foreign.
Provided by the Machine Readable Workbook.
uint8
MODE1 = 0x01, MODE2 = 0x02
ATTR_PROC_X_BUS_WIDTH
TARGET_TYPE_SYSTEM
Processor SMP X bus width.
Provided by the Machine Readable Workbook.
uint8
W4BYTE = 0x01, W8BYTE = 0x02
ATTR_ALL_MCS_IN_INTERLEAVING_GROUP
TARGET_TYPE_SYSTEM
If all MCS chiplets are in an interleaving group (1=true, 0=false).
If true the SMP fabric is setup in normal mode.
If false the SMP fabric is setup in checkerboard mode.
Provided by the Machine Readable Workbook.
uint8
ATTR_NEST_FREQ_MHZ
TARGET_TYPE_SYSTEM
Nest Freq for system in MHz
uint32
ATTR_BOOT_FREQ_MHZ
TARGET_TYPE_SYSTEM
Boot frequency in MHZ.
uint32
ATTR_EX_GARD_BITS
TARGET_TYPE_SYSTEM
Vector to communicate the guarded EX chiplets to SBE
One Guard bit per EX chiplet, bit location aligned to chiplet ID
(bit 16: EX00, bit 17: EX01, bit 18: EX02 ... bit 31: EX15)
Guarded EX chiplets are marked by a '1'.
uint32
ATTR_PIB_I2C_REFCLOCK
TARGET_TYPE_SYSTEM
i2c reference clock for the system
uint32
ATTR_PIB_I2C_NEST_PLL
TARGET_TYPE_SYSTEM
i2c pll for the system
uint32
ATTR_SBE_IMAGE_OFFSET
TARGET_TYPE_SYSTEM
HostBoot image for SBE, offset to account for ECC
uint32
ATTR_BOOT_VOLTAGE
TARGET_TYPE_SYSTEM
Boot Voltage for system
uint32
ATTR_DUMMY_PERSISTENCY
TARGET_TYPE_SYSTEM
Cached value to test persistency
uint8
ATTR_RISK_LEVEL
TARGET_TYPE_SYSTEM
Defines risk level to consider for initialization values applied during IPL.
Risk level 0 should contain solutions for all known errata, and may sacrifice performance to avoid data integrity issue/error checking cases.
Risk level 0x100 may introduce data integrity/error scenarios to provide full performance or visibility to state space/coverage behind known issues.
uint32
RL0 = 0x000,
RL100 = 0x100