ATTR_PM_EXTERNAL_VRM_STEPSIZE
TARGET_TYPE_SYSTEM
Step size (binary in microvolts) to take upon external VRM voltage
transitions. The value set here must take into account where internal
VRMs are enabled or not as, when they are enabled, the step size must
account for the tracking (eg PFET strength recalculation) for the step.
Consumer: p8_build_gpstate_tables.C, p8_pmc_init.C
Provided by the Machine Readable Workbook after system characterization.
uint8
ATTR_PM_EXTERNAL_VRM_STEPDELAY
TARGET_TYPE_SYSTEM
Step delay (binary in microseconds) after a voltage change
Consumer: p8_pmc_init
Provided by the Machine Readable Workbook after system characterization.
uint32
ATTR_PM_UNDERVOLTING_FRQ_MINIMUM
TARGET_TYPE_PROC_CHIP
Override for Minimum frequency for which undervolting is allowed.
If value = 0, the value of VPD CPMin data point is passed to OCC FW via
Pstate SuperStructure.
If value != 0, this value will be passed to OCC FW via Pstate SuperStructure
as the floor frequency for enabled CPMs.
Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value.
Consumer: OCC FW; OCC Lab Tools
Provided by the Machine Readable Workbook.
uint8
ATTR_PM_UNDERVOLTING_FREQ_MAXIMUM
TARGET_TYPE_PROC_CHIP
Override for Maximum frequency for which undervolting is allowed.
If value = 0, the value of VPD Turbo data point is passed to OCC FW via
Pstate SuperStructure.
If value != 0, this value will be passed to OCC FW via Pstate SuperStructure
as the ceiling frequency for enabled CPMs.
Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value.
Consumer: OCC FW; OCC Lab Tools
Provided by the Machine Readable Workbook.
uint8
ATTR_PM_SPIVID_FREQUENCY
TARGET_TYPE_SYSTEM
SPI Clock Frequency (binary in KHz)
Consumer: p8_pmc_init
Produces ATTR_PM_SPIVID_CLOCK_DIVIDER
Overridden by the Machine Readable Workbook.
If default of 0 is read, HWP will set SPIVID frequency to 1MHz.
uint32
ATTR_PM_SPIVID_PORT_ENABLE
TARGET_TYPE_PROC_CHIP
Defines the configuration of the SPIVID ports from the target.
- NONE means that no VRM is attached.
- PORTxNONRED means that the indicated port is used in a non-redundant
configuration.
- REDUNDANT means that all three are connected and considered redundant.
Producer: Machine Readable Workbook
uint8
NONE = 0x00, PORT0NONRED = 0x04, PORT1NONRED = 0x02, PORT2NONRED = 0x01, REDUNDANT = 0x07
ATTR_PM_SAFE_FREQUENCY
TARGET_TYPE_SYSTEM
Frequency (binary in KHz) indicating the frequency that the cores will be moved
to in the event of the loss of the OCC Heartbeat. This value needs to be the maximum
of the DpoMin frequency for proper PowerBus operation and the PowerSave value for
the present part.
Provided by the Machine Readable Workbook after system characterization.
The value is translated to the Pstate space.
Producer: Machine Readable Workbook
Consumers: p8_build_gpstate_table.C
DYNAMIC_ATTRIBUTE: ATTR_PM_SAFE_PSTATE
uint32
ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY
TARGET_TYPE_SYSTEM
Frequency (binary in KHz) for the point at which clock sector buffers
should be at full strength. This is to support Vmin operation.
Setting cannot overlap the Low or High bands.
Provided by the Machine Readable Workbook after system characterization.
uint32
ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY
TARGET_TYPE_SYSTEM
Frequency (binary in KHz)) for the lower end of the Low Frequency
Resonant band
Provided by the Machine Readable Workbook after system characterization.
uint32
ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY
TARGET_TYPE_SYSTEM
Frequency (binary in KHz) for the upper end of the Low Frequency
Resonant band
Provided by the Machine Readable Workbook after system characterization.
uint32
ATTR_PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY
TARGET_TYPE_SYSTEM
Frequency (binary in KHz) for the lower end of the High Frequency
Resonant band
Provided by the Machine Readable Workbook after system characterization.
uint32
ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY
TARGET_TYPE_SYSTEM
Frequency (binary in KHz)) for the upper end of the High Frequency
Resonant band
Provided by the Machine Readable Workbook after system characterization.
uint32
ATTR_PM_SPIPSS_FREQUENCY
TARGET_TYPE_SYSTEM
SPIPSS Clock Frequency (binary in KHz)
Valid range: 500KHz to 2500KHz
Consumer: p8_pss_init
Overridden by the Machine Readable Workbook.
If default of 0 is read, HWP will set SPIPSS frequency to 10MHz.
uint32
ATTR_PM_APSS_CHIP_SELECT
TARGET_TYPE_PROC_CHIP
Defines which of the PSS chip selects that the APSS is connected
Provided by the Machine Readable Workbook.
uint8
NONE = 0xFF, CS0 = 0x00, CS1 = 0x01
ATTR_PM_PBAX_NODEID
TARGET_TYPE_PROC_CHIP
Receive PBAX Nodeid. Value that indicates this PBA's PBAX Node affinity.
This is matched to pbax_nodeid of the PMISC Address phase.
Provided by the Machine Readable Workbook.
uint8
ATTR_PM_PBAX_CHIPID
TARGET_TYPE_PROC_CHIP
Receive PBAX Chipid. Value that indicates this PBA's PBAX Chipid within
the PBAX node. Is matched to pbax_chipid of the Address phase if
pbax_type=unicast.
Provided by the Machine Readable Workbook.
uint8
ATTR_PM_PBAX_BRDCST_ID_VECTOR
TARGET_TYPE_PROC_CHIP
Receive PBAX Broadcast Group. Vector that is indexed when decoded PMISC
pbax_type=broadcast with the decoded PMISC pbax_chipid value. If the
bit in this vector at the decoded bit location is a 1, then this receive
engine will participate in the broadcast operation.
Provided by the Machine Readable Workbook.
uint8
ATTR_PROC_R_LOADLINE_VDD
TARGET_TYPE_PROC_CHIP
Impedance (binary microOhms) of the load line from a processor VDD VRM to the
Processor Module pins. This value is applied to each processor instance.
Consumers: p8_build_gpstate_table.C
Provided by the Machine Readable Workbook (via the power subsystem design
per system)
uint32
ATTR_PROC_R_DISTLOSS_VDD
TARGET_TYPE_PROC_CHIP
Impedance (binary in microOhms) of the VDD distribution loss sense point
to the circuit. This value is applied to each processor instance.
Producer: Machine Readable Workbook (via the power subsystem design per system)
Consumer: p8_build_gpstate_table.C
uint32
ATTR_PROC_VRM_VOFFSET_VDD
TARGET_TYPE_PROC_CHIP
Offset voltage (binary in microvolts) to apply to the VDD VRM distribution to
the processor module. This value is applied to each processor instance.
Producer: Machine Readable Workbook (via the power subsystem design per system)
Consumer: p8_build_gpstate_table.C
uint32
ATTR_PROC_R_LOADLINE_VCS
TARGET_TYPE_PROC_CHIP
Impedance (binary microOhms) of the load line from a processor VCS VRM to the
Processor Module pins. This value is applied to each processor instance.
Producer: Machine Readable Workbook (via the power subsystem design per system)
Consumer: p8_build_gpstate_table.C
uint32
ATTR_PROC_R_DISTLOSS_VCS
TARGET_TYPE_PROC_CHIP
Impedance (binary in microOhms) of the VCS distribution loss sense point
to the circuit. This value is applied to each processor instance.
Producer: Machine Readable Workbook (via the power subsystem design per system)
Consumer: p8_build_gpstate_table.C
uint32
ATTR_PROC_VRM_VOFFSET_VCS
TARGET_TYPE_PROC_CHIP
Offset voltage (binary in microvolts) to apply to the VCS VRM distribution to
the processor module. This value is applied to each processor instance.
Producer: Machine Readable Workbook (via the power subsystem design per system)
Consumer: p8_build_gpstate_table.C
uint32
ATTR_FREQ_CORE_MAX
TARGET_TYPE_SYSTEM
Maximum frequency (binary in MHz) that any processor in the system will
run. Used to define the top end of the PState range in the frequency space.
From this, the ATTR_PROCPM_PSTATE0_FREQUENCY is computed using
ATTR_SYSTEM_REFCLK_FREQUENCY to determine the step size.
Producer: DEF file (per T. Rosedahl)
Consumers: p8_build_gpstate_table.C (among others)
TODO: Dean's proposal is that each platform will iterate over all chips,
reading the super-turbo frequency from MVPD #V and set this attribute
to the lowest value.
uint32
ATTR_CPM_TURBO_BOOST_PERCENT
TARGET_TYPE_SYSTEM
Percent of Boost Above Turbo for CPMs - (binary in 0.1 percent steps)
Used in generating extra Pstate tables beyond those that would result from
#V data.
Producer: DEF file as this is CCIN based
Consumers: p8_build_gpstate_table.C, p8_cpm_cal_load.C
Platform default: 0
uint32
ATTR_FREQ_EXT_BIAS_UP
TARGET_TYPE_PROC_CHIP
Frequency Bias - % of bias upward (binary in 0.5 percent steps) in generating
Pstate tables. Either this or FREQ_EXT_BIAS_DOWN can have non-zero value
concurrently due to the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
uint32
ATTR_FREQ_EXT_BIAS_DOWN
TARGET_TYPE_PROC_CHIP
Frequency Bias - % of bias downward (binary in 0.5 percent steps) in generating
Pstate tables. Either this or FREQ_EXT_BIAS_UP can have non-zero value
concurrently due to the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
uint32
ATTR_VOLTAGE_EXT_VDD_BIAS_UP
TARGET_TYPE_PROC_CHIP
External VDD Voltage Bias - % of bias upward (binary in 0.5 percent steps) that
is applied to each VPD point in generating the Global Pstate tables. Either
this or ATTR_VOLTAGE_EXT_VDD_BIAS_DOWN can have non-zero value concurrently due to
the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
uint32
ATTR_VOLTAGE_EXT_VDD_BIAS_DOWN
TARGET_TYPE_PROC_CHIP
External VDD Voltage Bias - % of bias downward (binary in 0.5 percent steps) that
is applied to each VPD point in generating the Global Pstate tables. Either
this or ATTR_VOLTAGE_EXT_VDD_BIAS_UP can have non-zero value concurrently due to
the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
uint32
ATTR_VOLTAGE_EXT_VCS_BIAS_UP
TARGET_TYPE_PROC_CHIP
External VCS Voltage Bias - % of bias upward (binary in 0.5 percent steps) that
is applied to each VPD point in generating the Global Pstate tables. Either
this or ATTR_VOLTAGE_EXT_VCS_BIAS_DOWN can have non-zero value concurrently due to
the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
uint32
ATTR_VOLTAGE_EXT_VCS_BIAS_DOWN
TARGET_TYPE_PROC_CHIP
External VCS Voltage Bias - % of bias downward (binary in 0.5 percent steps) that
is applied to each VPD point in generating the Global Pstate tables. Either
this or ATTR_VOLTAGE_EXT_VCS_BIAS_UP can have non-zero value concurrently due to
the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
uint32
ATTR_VOLTAGE_INT_VDD_BIAS_UP
TARGET_TYPE_PROC_CHIP
Internal VDD Voltage Bias - % of bias upward (binary in 0.5 percent steps) that
is applied to the Local Pstate Table voltage entries based on the Global Pstate Table
built *after* the ATTR_VOLTAGE_EXT_VDD_BIAS_UP/ATTR_VOLTAGE_EXT_VDD_BIAS_DOWN bias
have been applied. Either this or ATTR_VOLTAGE_INT_VDD_BIAS_DOWN can have non-zero value
concurrently due to the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
uint32
ATTR_VOLTAGE_INT_VDD_BIAS_DOWN
TARGET_TYPE_PROC_CHIP
Internal VDD Voltage Bias - % of bias downward (binary in 0.5 percent steps) that
is applied to the Local Pstate Table voltage entries based on the Global Pstate Table
built *after* the ATTR_VOLTAGE_EXT_VDD_BIAS_UP/ATTR_VOLTAGE_EXT_VDD_BIAS_DOWN bias
have been applied. Either this or ATTR_VOLTAGE_INT_VDD_BIAS_UP can have non-zero value
concurrently due to the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
uint32
ATTR_VOLTAGE_INT_VCS_BIAS_UP
TARGET_TYPE_PROC_CHIP
Internal VCS Voltage Bias - % of bias upward (binary in 0.5 percent steps) that
is applied to the Local Pstate Table voltage entries based on the Global Pstate Table
built *after* the ATTR_VOLTAGE_EXT_VCS_BIAS_UP/ATTR_VOLTAGE_EXT_VCS_BIAS_DOWN bias
have been applied. Either this or ATTR_VOLTAGE_INT_VCS_BIAS_DOWN can have non-zero value
concurrently due to the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
uint32
ATTR_VOLTAGE_INT_VCS_BIAS_DOWN
TARGET_TYPE_PROC_CHIP
Internal VCS Voltage Bias - % of bias downward (binary in 0.5 percent steps) that
is applied to the Local Pstate Table voltage entries based on the Global Pstate Table
built *after* the ATTR_VOLTAGE_EXT_VCS_BIAS_UP/ATTR_VOLTAGE_EXT_VCS_BIAS_DOWN bias
have been applied. Either this or ATTR_VOLTAGE_INT_VCS_BIAS_UP can have non-zero value
concurrently due to the unsigned definition of attributes.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumers: p8_build_gpstate_table.C
Platform default: 0
uint32
ATTR_PM_SLEEP_ENABLE
TARGET_TYPE_SYSTEM
Control HW response to execution of PPC sleep instruction
if OFF, treat sleep as nap
if ON, treat sleep as sleep
Producer: Hostboot
Consumer: p8_slw_build.C
uint8
OFF=0, ON=1
ATTR_PM_SLEEP_ENTRY
TARGET_TYPE_PROC_CHIP
Setting depends on di/dt charateristics of the system.
Set Assisted if power off serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency
Producer: MRWB
Consumer: p8_poreslw_init.C
uint8
HARDWARE=0, ASSISTED=1
ATTR_PM_SLEEP_EXIT
TARGET_TYPE_PROC_CHIP
Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_SLEEP_TYPE.
Set to Assisted if power on serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency
Must be set to Assisted if ATTR_PM_SLEEP_TYPE=Deep as this necessary for restore.
Setting to Hardware is a test mode for Fast only.
Producer: MRWB
Consumer: p8_poreslw_init.C
uint8
HARDWARE=0, ASSISTED=1
ATTR_PM_SLEEP_TYPE
TARGET_TYPE_PROC_CHIP
Sleep Power Off Select:
Selects which voltage level to place the Core domain PFETs upon Sleep entry. 0 = Vret (Fast Sleep Mode), 1 = Voff (Deep Sleep Mode)
Producer: MRWB
Consumer: p8_poreslw_init.C
uint8
FAST=0, DEEP=1
ATTR_PM_WINKLE_ENTRY
TARGET_TYPE_PROC_CHIP
Setting depends on di/dt charateristics of the system.
Set Assisted if power off serialization is needed and WINKLE_TYPE=Fast;
Set to Hardware if the system can handle the unrelated powering off between cores.
Hardware setting decreases entry latency
Producer: MRWB
Consumer: p8_poreslw_init.C
uint8
HARDWARE=0, ASSISTED=1
ATTR_PM_WINKLE_EXIT
TARGET_TYPE_PROC_CHIP
Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_WINKLE_TYPE.
Set to Assisted if power on serialization is needed and WINKLE_TYPE=Fast; Set to Hardware if the system
can handle the unrelated powering off between cores. Hardware setting decreases entry latency.
Must be set to Assisted if ATTR_PM_WINKLE_TYPE=Deep as this necessary for restore.
Setting to Hardware is a test mode for Fast only.
Producer: MRWB
Consumer: p8_poreslw_init.C
uint8
HARDWARE=0, ASSISTED=1
ATTR_PM_WINKLE_TYPE
TARGET_TYPE_PROC_CHIP
Winkle Power Off Select:
Selects which voltage level to place the Core and ECO domain PFETs upon Winkle entry. 0 = Vret (Fast Winkle Mode), 1 = Voff (Deep Winkle Mode)
Producer: MRWB
Consumer: p8_poreslw_init.C
uint8
FAST=0, DEEP=1
ATTR_PM_SYSTEM_IVRMS_ENABLED
TARGET_TYPE_SYSTEM
System control to allow (if all other attribute tests yield true values) or categorically disallow IVRM enablement
Producer: MRWB
Consumer: p8_build_pstate_datablock.C
uint8
FALSE=0, TRUE=1
ATTR_PM_SYSTEM_IVRM_VPD_MIN_LEVEL
TARGET_TYPE_SYSTEM
Version level of #M that represents the minimum for IVRM characterized parts.
If this value is non-zero and the #M version level is less than this value, IVRMs are disabled.
If the #M version is greater than or equal to this value, the IVRMs are allowed to be enable from a level of part perspective.
Producer: MRWB
Consumer: p8_build_pstate_datablock.C
uint8