RC_SBE_SUCCESS
This halt code does not represent an error; This is the code associated
with the normal successful completion of an IPL by an SBE istep
procedure.
RC_SBE_SUCCESS_SLAVE_CHIP
This halt code does not represent an error; This is the code associated
with the normal successful completion of an IPL by an SBE istep
procedure on a slave chip.
RC_SBE_PAUSE_WITH_SUCCESS
This halt code does not represent an error; This is the code associated
with a procedure initiated halt of the SBE code, with the expectation
that it will be resumed at a later point in time.
RC_SBE_PROC_ENTRY_HALT
This halt code does not represent an error; This is the code associated
with a HALT requested by the user prior to the execution of a procedure
by setting the PROC_CONTROL_ENTRY_HALT bit in the control word for the
procedure.
RC_SBE_PROC_EXIT_HALT
This halt code does not represent an error; This is the code associated
with a HALT requested by the user after the execution of a procedure
by setting the PROC_CONTROL_EXIT_HALT bit in the control word for the
procedure.
RC_SBE_PROC_CHECKSTOP
This halt code indicates that a checkstop was detected after executing a
procedure. Use the fields of the SBEVITAL register to identify the
procedure that failed.
proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE
CHIP
HIGH
CHIP
CHIP
RC_SBE_PROC_RECOVERABLE
This halt code indicates that a recoverable error was detected after
executing a procedure. Use the fields of the SBEVITAL register to
identify the procedure that failed.
proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE
CHIP
LOW
CODE
HIGH
RC_SBE_PROC_SPATTN
This halt code indicates that a Special Attention was detected after
executing a procedure. Use the fields of the SBEVITAL register to
identify the procedure that failed.
proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE
CHIP
HIGH
CHIP
CHIP
RC_SBE_PORE_ERROR0
This halt code indicates that an execution-phase PIB/PCB access
returned a non-0 response. The PORE PIBMS_DBG registers 0 and 1
(plus the remainder of the PORE state) contain the information required
for an initial debug of the problem.
This error should never occur for SBE/SLW, based on the fact that the
HW error handler mechanism is disabled.
CHIP
HIGH
CODE
LOW
CHIP
CHIP
RC_SBE_PORE_ERROR1
This halt code indicates that an execution-phase OCI accesss had an
error. The PORE PIBMS_DBG registers 0 and 1 (plus the remainder of the
PORE state) contain the information required for an initial debug of the
problem.
This error should never occur for SBE/SLW, based on the fact that the
HW error handler mechanism is disabled.
CHIP
HIGH
CODE
LOW
CHIP
CHIP
RC_SBE_PORE_ERROR2
This halt code indicates an instruction fetch or decode error. The PORE
specification lists several causes of this error code. The most likely
causes in a production system are:
o An I2C hang when fetching code from SEEPROM;
o A bad branch that starts executing garbage or data;
o Memory corruption
This error should never occur for SBE/SLW, based on the fact that the
HW error handler mechanism is disabled.
CHIP
HIGH
CODE
LOW
CHIP
CHIP
RC_SBE_PORE_ERROR3
This halt code indicates an internal data error during consistency
checking, e.g., a bad scan-data CRC.
This error should never occur for SBE/SLW, based on the fact that the
HW error handler mechanism is disabled.
CHIP
HIGH
CODE
LOW
CHIP
CHIP
RC_SBE_PORE_ERROR4
This halt code indicates that a second error occurred during processing
of an initial error.
This error should never occur for SBE/SLW, based on the fact that the
HW error handler mechanism is disabled.
CHIP
HIGH
CODE
LOW
CHIP
CHIP
RC_SBE_SCAN0_DONE_POLL_THRESHOLD
This error is signalled by the scan0 subroutine, indicating that the
scan0 DONE polling reached the specified threshold value. The scan0
subroutine could have been called by various procedures.
proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FLUSH_FAIL, POR_FFDC_OFFSET_USE_P1
CHIP
HIGH
CHIP
CHIP
RC_SBE_ARRAYINIT_POLL_THRESHOLD
This error is signalled by the arrayinit subroutine, indicating that the
arrayinit DONE polling reached the specified threshold value. The arrayinit
subroutine could have been called by various procedures.
proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_ARRAYINIT_FAIL, POR_FFDC_OFFSET_USE_P1
CHIP
HIGH
CHIP
CHIP