RC_SLW_UNDEFINED_SV
This error is signalled by proc_slw_base and indicates that an
invalid start vector was detected in the EXE_TRIGGER (ETR) register when
kicking off an idle transition. The start vector is in ETR(8:11).
CHIP
HIGH
CODE
LOW
CHIP
CHIP
RC_SLW_PFET_VDD_TIMEOUT_ERROR
This error is signalled by proc_slw_poweronoff and indicates that a timeout
occured waiting for the VDD PFET sequencer(s) to complete.
CHIP
HIGH
CHIP
CHIP
RC_SLW_PFET_VCS_TIMEOUT_ERROR
This error is signalled by proc_slw_poweronoff and indicates that a timeout
occured waiting for the VCS PFET sequencer(s) to complete.
CHIP
HIGH
CHIP
CHIP
RC_SLW_PFET_DECODE_ERROR
This error is signalled by proc_slw_poweronoff and indicates that an invalid
PFET decode was detected. This is an SLW firmware issue.
CHIP
LOW
CODE
HIGH
CHIP
CHIP
RC_SLW_IVRM_BS_SLEEP_ENTRY_TIMEOUT
This error is signalled by proc_slw_base and indicates that a timeout
occured waiting for the internal VRM babystepper to synchronize the idle
transition command during sleep entry.
CHIP
HIGH
CHIP
CHIP
RC_SLW_IVRM_BS_WINKLE_ENTRY_TIMEOUT
This error is signalled by proc_slw_base and indicates that a timeout
occured waiting for the internal VRM babystepper to synchronize the idle
transition command during winkle entry.
CHIP
HIGH
CHIP
CHIP
RC_SLW_IVRM_BS_EXIT_TIMEOUT
This error is signalled by proc_slw_base and indicates that a timeout
occured waiting for the internal VRM babystepper to synchronize the idle
transition command during a fast exit.
CHIP
HIGH
CHIP
CHIP
RC_SLW_IVRM_CAL_TIMEOUT
This error is signalled by proc_slw_base and indicates that a timeout
occured while polling for the iVRM calibration to complete.
CHIP
HIGH
CHIP
CHIP
RC_SLW_IVRM_CAL_BS_EXIT_TIMEOUT
This error is signalled by proc_slw_base and indicates that a timeout
occured waiting for the internal VRM babystepper to synchronize the idle
transition command during a deep exit after iVRM calibration.
CHIP
HIGH
CHIP
CHIP
RC_SLW_IVRM_FORCESM_TIMEOUT
This error is signalled by proc_slw_base and indicates that a timeout
occured waiting for the internal VRM force safe mode to take effect.
CHIP
HIGH
CHIP
CHIP
RC_SLW_RAM_THREAD_CHECK_ERROR
This error is signalled by proc_slw_ram and indicates that a timeout
occured waiting the RAM hardware to accept the instruction given to it..
CHIP
HIGH
CHIP
CHIP
RC_SLW_RAM_THREAD_QUIESCE_ERROR
This error is signalled by proc_slw_ram and indicates that a timeout
occured waiting the RAM hardware to quiesce.
CHIP
HIGH
CHIP
CHIP
RC_SLW_RAM_CONTROL_EXCEPTION_ERROR
This error is signalled by proc_slw_ram and indicates that RAM controller
indicates recovery is inprogress or an exception has occured..
CHIP
HIGH
CHIP
CHIP
RC_SLW_RAM_STATUS_TIMEOUT_ERROR
This error is signalled by proc_slw_ram and indicates that a timeout occured
looking for good status from the RAM Controller.
CHIP
HIGH
CHIP
CHIP
RC_SLW_GOTO_TIMEOUT_ERROR
This error is signalled by proc_slw_base and indicates that a timeout occured
looking for the proper PCBS-PM state before issuing a PCBS-PM "GOTO" command.
CHIP
HIGH
CHIP
CHIP
RC_SLW_ERRINJ_NEVER_REACH_HALT
This error is signalled by proc_slw_pro_epi_log and indicates that the image
updated the PMC status reg but never reached the subsequent halt op. PMC SLW
Timeouts will be indicated without further FIR bits.
CHIP
HIGH
CHIP
CHIP
RC_SLW_ERRINJ_SIMPLE_HALT
This error is signalled by proc_slw_pro_epi_log and indicates that the image
executed the simple halt error injection. PMC SLW Timeouts will be indicated
without further FIR bits.
CHIP
HIGH
RC_SLW_ERRINJ_INVALID_INSTR
This error is signalled by proc_slw_pro_epi_log and indicates that the image
enabled invalid instruction error injection occured.
CHIP
HIGH
RC_SLW_ERRINJ_INVALID_OCI_ADDRESS
This error is signalled by proc_slw_pro_epi_log and indicates that the image
enabled invalid OCI address error injection occured.
CHIP
HIGH
RC_SLW_ERRINJ_INVALID_PIB_ADDRESS
This error is signalled by proc_slw_pro_epi_log and indicates that the image
enabled invalid PIB address error injection occured.
CHIP
HIGH
RC_SLW_ERRINJ_PC_UNDERFLOW
This error is signalled by proc_slw_pro_epi_log and indicates that the image
enabled PC underflow error injection occured.
CHIP
HIGH
RC_SLW_ERRINJ_PC_OVERRFLOW
This error is signalled by proc_slw_pro_epi_log and indicates that the image
enabled PC overflow error injection occured.
CHIP
HIGH
RC_SLW_ERRINJ_TIMEOUT_ERROR
This error is signalled by proc_slw_pro_epi_log and indicates that the image
enabled timeout error injection occured.
CHIP
HIGH
RC_SLW_EH_PIB_ERROR
This error is signalled by proc_slw_error_handler upon a detected error 0
event (non-masked PIB error code).
CHIP
HIGH
CHIP
CHIP
RC_SLW_EH_OCI_ERROR
This error is signalled by proc_slw_error_handler upon a detected error 1
event (non-masked OCI error code).
CHIP
HIGH
CHIP
CHIP
RC_SLW_EH_INSTRUCTION_ERROR
This error is signalled by proc_slw_error_handler upon a detected error 2
event (instruction fetch or decode).
CHIP
HIGH
CHIP
CHIP
RC_SLW_EH_INTERNAL_DATA_ERROR
This error is signalled by proc_slw_error_handler upon a detected error 3
event (internal data error).
CHIP
HIGH
CHIP
CHIP
RC_SLW_EH_ERROR_ON_ERROR
This error is signalled by proc_slw_error_handler upon a detected error 4
event (an error was detected upon an error).
CHIP
HIGH
CHIP
CHIP
RC_SLW_PMGP1_ENABLE_CONFIG_ERROR
This error is signalled by proc_slw_base code when the multicast read AND
and the multicast read OR of the PMGP1 register for the chiplets
represented in the EXE Trigger register do not match. This could be caused
by a configuration error with the Deep Sleep power up and/or down bits or
Deep Winkle power up bit. If these bits match, then a hardware fault is
the next most probable.
CHIP
HIGH
CODE
LOW
CHIP
CHIP
SLW_RC_ILLEGAL_WINKLE_ENTRY_POWER_DOWN
This error is signalled by proc_slw_base code (poweronoff portion) and indicates
that the PMGP1 bit for WINKLE_POWER_DOWN when WINKLE_POWER_OFF_SEL is set to 1
(eg a Deep Winkle) has been detected. This is an illegal configuration as it
causes the loss of the High Availability Log Write pointer in the L3 before it
could be saved for restoration upon Deep Winkle Exit.
CHIP
LOW
CODE
HIGH
CHIP
CHIP
SLW_RC_OHA_SPWUP_TIMEOUT
This error is signalled by proc_slw_base code when the polling for OHA AISS
achieving the special wake-up state after hitting the PCBS GOTO operation to
complete deep sleep exit.
CHIP
HIGH
CHIP
CHIP
RC_SLW_CPM_SPWKUP_NOT_SET
This error is signalled by proc_slw_occ_cpm code when it is detected that
special wake-up override isnt enabled which it must be prior to calling
any of the CPM install or enable routines.
CHIP
LOW
CODE
HIGH
CHIP
CHIP