#-- $Id: p8.xbus.scom.initfile,v 1.11 2013/05/02 21:30:11 jgrell Exp $ #################################################################### ## ## Auto-genrated by fig2scominit.pl ## Based on SETUP_ID_MODE X_BUS_8B_TR_HW ## from ../../logic/mesa_sim/fusion/run/IOEPC_XBUS_WRAP.IOEPC_XBUS_WRAP.figdb ## ## Created on Thu May 2 15:52:51 CDT 2013, by jgrell #################################################################### ## -- CHANGE HISTORY: ## -------------------------------------------------------------------------------- ## -- Version:|Author: | Date: | Comment: ## -- --------|---------|--------|------------------------------------------------- ## -- 13050200| jgr |05-02-13| Added rx_dll_vreg_dac_pullup=1 and changed rx_dll1/2_vreg_drvcon to 111 ## -- 13042400| jgr |04-24-13| Added rx_max_ber_check_count=3 setting ## -- 13041300| jgr |04-13-13| Made rx dll1/dll2 vreg drv changes ## -- smr13032500| SMR |03-25-13| Changed rx_sls_timeout_sel init to 0b110 ## -- jgr13031300| jgr |03-13-13| Added missing entries from rel 0128 ## -- 13030500| thomsen |03-05-13| Added DLL settings for HW241376 ## -- 13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) ## -- 12112700| SMR |11-27-12| HW20806: Added rx_sls_extend_sel default of 0b101 (slave side only!) ## -- 12111300| berger |11-13-12| Updated with HW eyeopt and recal settings ## -- 12062500| SMR |06-25-12| HW210654: Added rx_sls_timeout_sel default of 1 ## -- 12011800| RJR |01-18-12| Added RX_CTL2_REGS FILE REFERENCES Issue HW164277 ## -- 12010300| berger |01-03-12| HW184227: Added SETUP_ID_MODE dials ## -- 11122000| berger |12-20-11| HW186823: removed timer settings, set in regs ## -- 11121500| thomsen |12-15-11| Added Per-Pack GCR SCOM Addresses for Regchk (HW188381,HW182867) ## -- | | | Removed 0x0000040000000000 from TX address definitions since it is in the lower level figtree files (HW187781,HW187893) ## -- 11122000| berger |12-20-11| HW186823: removed timer settings, set in regs ## -- 11121500| thomsen |12-15-11| Added Per-Pack GCR SCOM Addresses for Regchk (HW188381,HW182867) ## -- | | | Removed 0x0000040000000000 from TX address definitions since it is in the lower level figtree files (HW187781,HW187893) ## -- 11102100| SMR |10-21-11| HW181193: Added rx_dyn_rpr_enc_bad_data_lane_width register ## -- 11092900| SMR |09-29-11| HW171978: Added dyn rpr error tallying defaults ## -- 11052300| berger |05-23-11| Added ds_timeout_sel and servo timeouts ## -- 11050300| SMR |05-02-11| Added tx_max_bad_lanes ## -- 11041900| smc |04-19-11| Per Mike, commented out BUSCTL.BUS_CTL_REGS.base_addr (SCOM) += 0x0000000000000000; ## -- 11022400| thomsen |02-24-11| Fixed 4-byte mode settings ## -- 11021600| thomsen |02-16-11| Added Per-Bus, Per-Lane and Per-Group GCR SCOM addresses so Regchk would pass ## -- 11020200| thomsen |02-02-11| Added 4 Byte Mode settings (disable all RXTX0 lanes and parts of RXTX1) and simplified RX_TX_SCRAMBLER_TAP_ID ## -- 11020200| thomsen |02-02-11| Added RX & TX scramble/descramble tap ID settings ## -- 11012500| berger |01-25-11| added TX lane disable and rx_bus_width fields, added missing SETUP_ID fields ## -- 11011800| mbs |01-18-11| Added "*_GEN." to group hierarchy ## -- 11010700| berger |01-07-11| added lane disable and max bad lane ## -- 10121600| thomsen |12-16-10| Added RX_FENCE ## -- 10120800| thomsen |12-08-10| Added TX_BUS_WIDTH ## -- 10120100| thomsen |12-01-10| Fixed typo ## -- 10112900| thomsen |11-29-10| Fixed BUS_ID's and GROUP_ID's for TX ## -- 10102600| thomsen |10-26-10| Initial version ## -------------------------------------------------------------------------------- ## -- TODO: These need to be modified for Z SyntaxVersion = 1 #################################################################### # Define File #################################################################### include ei4.io.define define def_IS_HW = SYS.ATTR_IS_SIMULATION == 0; define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1; define def_bus_id0 = (ATTR_CHIP_UNIT_POS == 0); define def_bus_id1 = (ATTR_CHIP_UNIT_POS == 1); define def_bus_id2 = (ATTR_CHIP_UNIT_POS == 2); define def_bus_id3 = (ATTR_CHIP_UNIT_POS == 3); define prim_id = (TGT1.ATTR_FABRIC_NODE_ID*100) + TGT1.ATTR_POS; define conn_id = (TGT3.ATTR_FABRIC_NODE_ID*100) + TGT3.ATTR_POS; define def_is_master = (prim_id < conn_id); define def_is_slave = (prim_id > conn_id); define xbus_base_addr = xbus0_gcr_addr; #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG scom 0x800AF000(xbus_base_addr) { bits, scom_data, expr; rx_max_ber_check_count, 0b00000011 , def_IS_HW; rx_max_ber_check_count, 0b00000000 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_DLL_ANALOG_TWEAKS_PG scom 0x800E7800(xbus_base_addr) { bits, scom_data, expr; rx_dll1_vreg_drvcon, 0b111 , def_IS_HW; rx_dll1_vreg_drvcon, 0b000 , def_IS_VBU; rx_dll2_vreg_drvcon, 0b111 , def_IS_HW; rx_dll2_vreg_drvcon, 0b000 , def_IS_VBU; rx_dll_vreg_compcon, 0b101 , def_IS_HW; rx_dll_vreg_compcon, 0b000 , def_IS_VBU; rx_dll_vreg_dac_pullup, 0b1 , def_IS_HW; rx_dll_vreg_dac_pullup, 0b0 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG scom 0x8009D800(xbus_base_addr) { bits, scom_data, expr; rx_dyn_rpr_bad_lane_max, 0b0001111, any; rx_dyn_rpr_enc_bad_data_lane_width, 0b111, any; rx_dyn_rpr_err_cntr1_duration, 0b1010, any; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG scom 0x800AE000(xbus_base_addr) { bits, scom_data, expr; rx_dyn_rpr_bad_bus_max, 0b0011111, any; rx_dyn_rpr_err_cntr2_duration, 0b0111, any; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP scom 0x800B1800(xbus_base_addr) { bits, scom_data, expr; rx_ddc_use_cyc_block_lock, 0b0 , def_IS_HW; rx_ddc_use_cyc_block_lock, 0b1 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP scom 0x800B3000(xbus_base_addr) { bits, scom_data, expr; rx_cal_dec_val_a, 0b0111 , def_IS_HW; rx_cal_dec_val_a, 0b1000 , def_IS_VBU; rx_cal_dec_val_b, 0b0001 , def_IS_HW; rx_cal_dec_val_b, 0b0000 , def_IS_VBU; rx_cal_dec_val_c, 0b0111 , def_IS_HW; rx_cal_dec_val_c, 0b0000 , def_IS_VBU; rx_cal_dec_val_d, 0b0111 , def_IS_HW; rx_cal_dec_val_d, 0b0110 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP scom 0x800B3800(xbus_base_addr) { bits, scom_data, expr; rx_cal_dec_val_e, 0b0111 , def_IS_HW; rx_cal_dec_val_e, 0b0110 , def_IS_VBU; rx_cal_dec_val_f, 0b0111 , def_IS_HW; rx_cal_dec_val_f, 0b0000 , def_IS_VBU; rx_cal_dec_val_g, 0b0111 , def_IS_HW; rx_cal_dec_val_g, 0b0000 , def_IS_VBU; rx_cal_dec_val_h, 0b0111 , def_IS_HW; rx_cal_dec_val_h, 0b0000 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP scom 0x800B2000(xbus_base_addr) { bits, scom_data, expr; rx_cal_inc_val_a, 0b0111 , def_IS_HW; rx_cal_inc_val_a, 0b1000 , def_IS_VBU; rx_cal_inc_val_b, 0b0001 , def_IS_HW; rx_cal_inc_val_b, 0b0000 , def_IS_VBU; rx_cal_inc_val_c, 0b0111 , def_IS_HW; rx_cal_inc_val_c, 0b0000 , def_IS_VBU; rx_cal_inc_val_d, 0b0111 , def_IS_HW; rx_cal_inc_val_d, 0b0110 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP scom 0x800B2800(xbus_base_addr) { bits, scom_data, expr; rx_cal_inc_val_e, 0b0111 , def_IS_HW; rx_cal_inc_val_e, 0b0110 , def_IS_VBU; rx_cal_inc_val_f, 0b0111 , def_IS_HW; rx_cal_inc_val_f, 0b0000 , def_IS_VBU; rx_cal_inc_val_g, 0b0111 , def_IS_HW; rx_cal_inc_val_g, 0b0000 , def_IS_VBU; rx_cal_inc_val_h, 0b0111 , def_IS_HW; rx_cal_inc_val_h, 0b0000 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG scom 0x800A3800(xbus_base_addr) { bits, scom_data, expr; rx_eo_enable_ber_test, 0b1 , def_IS_HW; rx_eo_enable_ber_test, 0b0 , def_IS_VBU; rx_eo_enable_ctle_cal, 0b1 , def_IS_HW; rx_eo_enable_ctle_cal, 0b0 , def_IS_VBU; rx_eo_enable_dcd_cal, 0b1 , def_IS_HW; rx_eo_enable_dcd_cal, 0b0 , def_IS_VBU; rx_eo_enable_final_l2u_adj, 0b1, any; rx_eo_enable_latch_offset_cal, 0b1 , def_IS_HW; rx_eo_enable_latch_offset_cal, 0b0 , def_IS_VBU; rx_eo_enable_measure_eye_width, 0b1 , def_IS_HW; rx_eo_enable_measure_eye_width, 0b0 , def_IS_VBU; rx_eo_enable_result_check, 0b1 , def_IS_HW; rx_eo_enable_result_check, 0b0 , def_IS_VBU; rx_eo_enable_vref_cal, 0b1 , def_IS_HW; rx_eo_enable_vref_cal, 0b0 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG scom 0x8009A800(xbus_base_addr) { bits, scom_data, expr; rx_fence, 0b1, any; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG scom 0x80085000(xbus_base_addr) { bits, scom_data, expr; rx_bus_id, 0b000000, any; rx_group_id, 0b000000, any; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_ID2_PG scom 0x80085800(xbus_base_addr) { bits, scom_data, expr; rx_last_group_id, 0b000011, any; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_ID3_PG scom 0x80086000(xbus_base_addr) { bits, scom_data, expr; rx_end_lane_id, 0b0010011, any; rx_start_lane_id, 0b0000000, any; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG scom 0x80092800(xbus_base_addr) { bits, scom_data, expr; rx_lane_disabled_vec_0_15, 0b0000000000000000, any; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG scom 0x80093000(xbus_base_addr) { bits, scom_data, expr; rx_lane_disabled_vec_16_31, 0b0000111111111111, any; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_MODE1_PP scom 0x800B0800(xbus_base_addr) { bits, scom_data, expr; rx_bit_lock_timeout_sel, 0b110 , def_IS_HW; rx_bit_lock_timeout_sel, 0b101 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG scom 0x80081800(xbus_base_addr) { bits, scom_data, expr; rx_master_mode, 0b1, def_is_master; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG scom 0x800AB800(xbus_base_addr) { bits, scom_data, expr; rx_rc_enable_dll_update, 0b1 , def_IS_HW; rx_rc_enable_dll_update, 0b0 , def_IS_VBU; rx_rc_enable_edge_track, 0b1 , def_IS_HW; rx_rc_enable_edge_track, 0b0 , def_IS_VBU; rx_rc_enable_measure_eye_width, 0b1 , def_IS_HW; rx_rc_enable_measure_eye_width, 0b0 , def_IS_VBU; rx_rc_enable_result_check, 0b1 , def_IS_HW; rx_rc_enable_result_check, 0b0 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP scom 0x800B6000(xbus_base_addr) { bits, scom_data, expr; rx_servo_timeout_sel_a, 0b0101 , def_IS_HW; rx_servo_timeout_sel_a, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_b, 0b1010 , def_IS_HW; rx_servo_timeout_sel_b, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_c, 0b0101 , def_IS_HW; rx_servo_timeout_sel_c, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_d, 0b1001 , def_IS_HW; rx_servo_timeout_sel_d, 0b0101 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP scom 0x800B6800(xbus_base_addr) { bits, scom_data, expr; rx_servo_timeout_sel_f, 0b1000 , def_IS_HW; rx_servo_timeout_sel_f, 0b0110 , def_IS_VBU; rx_servo_timeout_sel_h, 0b1110 , def_IS_HW; rx_servo_timeout_sel_h, 0b1000 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG scom 0x80080800(xbus_base_addr) { bits, scom_data, expr; rx_sls_extend_sel, 0b101, def_is_slave; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG scom 0x80091000(xbus_base_addr) { bits, scom_data, expr; rx_eo_ctle_timeout_sel, 0b111 , def_IS_HW; rx_eo_ctle_timeout_sel, 0b110 , def_IS_VBU; rx_eo_offset_timeout_sel, 0b111 , def_IS_HW; rx_eo_offset_timeout_sel, 0b110 , def_IS_VBU; rx_eo_vref_timeout_sel, 0b111 , def_IS_HW; rx_eo_vref_timeout_sel, 0b110 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG scom 0x80089800(xbus_base_addr) { bits, scom_data, expr; rx_ds_bl_timeout_sel, 0b101 , def_IS_HW; rx_ds_bl_timeout_sel, 0b001 , def_IS_VBU; rx_ds_timeout_sel, 0b110 , def_IS_HW; rx_ds_timeout_sel, 0b010 , def_IS_VBU; rx_sls_timeout_sel, 0b110, any; rx_wt_timeout_sel, 0b111 , def_IS_HW; rx_wt_timeout_sel, 0b011 , def_IS_VBU; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG scom 0x80099800(xbus_base_addr) { bits, scom_data, expr; rx_rx_bus_width, 0b1010000, any; rx_tx_bus_width, 0b1010000, any; } #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG scom 0x80095800(xbus_base_addr) { bits, scom_data, expr; rx_wtr_max_bad_lanes, 0b00010, any; } #RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B000(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B001(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B002(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b010, any; } #RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B003(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b011, any; } #RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B004(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b100, any; } #RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B005(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b101, any; } #RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B006(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b110, any; } #RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B007(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b111, any; } #RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B008(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B009(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00A(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00B(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00C(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b111, any; } #RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00D(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b110, any; } #RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00E(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b101, any; } #RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00F(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b100, any; } #RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B010(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b011, any; } #RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B011(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b010, any; } #RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B012(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B013(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG scom 0x800AF020(xbus_base_addr) { bits, scom_data, expr; rx_max_ber_check_count, 0b00000011 , def_IS_HW; rx_max_ber_check_count, 0b00000000 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_DLL_ANALOG_TWEAKS_PG scom 0x800E7820(xbus_base_addr) { bits, scom_data, expr; rx_dll1_vreg_drvcon, 0b111 , def_IS_HW; rx_dll1_vreg_drvcon, 0b000 , def_IS_VBU; rx_dll2_vreg_drvcon, 0b111 , def_IS_HW; rx_dll2_vreg_drvcon, 0b000 , def_IS_VBU; rx_dll_vreg_compcon, 0b101 , def_IS_HW; rx_dll_vreg_compcon, 0b000 , def_IS_VBU; rx_dll_vreg_dac_pullup, 0b1 , def_IS_HW; rx_dll_vreg_dac_pullup, 0b0 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG scom 0x8009D820(xbus_base_addr) { bits, scom_data, expr; rx_dyn_rpr_bad_lane_max, 0b0001111, any; rx_dyn_rpr_enc_bad_data_lane_width, 0b111, any; rx_dyn_rpr_err_cntr1_duration, 0b1010, any; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG scom 0x800AE020(xbus_base_addr) { bits, scom_data, expr; rx_dyn_rpr_bad_bus_max, 0b0011111, any; rx_dyn_rpr_err_cntr2_duration, 0b0111, any; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP scom 0x800B1820(xbus_base_addr) { bits, scom_data, expr; rx_ddc_use_cyc_block_lock, 0b0 , def_IS_HW; rx_ddc_use_cyc_block_lock, 0b1 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP scom 0x800B3020(xbus_base_addr) { bits, scom_data, expr; rx_cal_dec_val_a, 0b0111 , def_IS_HW; rx_cal_dec_val_a, 0b1000 , def_IS_VBU; rx_cal_dec_val_b, 0b0001 , def_IS_HW; rx_cal_dec_val_b, 0b0000 , def_IS_VBU; rx_cal_dec_val_c, 0b0111 , def_IS_HW; rx_cal_dec_val_c, 0b0000 , def_IS_VBU; rx_cal_dec_val_d, 0b0111 , def_IS_HW; rx_cal_dec_val_d, 0b0110 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP scom 0x800B3820(xbus_base_addr) { bits, scom_data, expr; rx_cal_dec_val_e, 0b0111 , def_IS_HW; rx_cal_dec_val_e, 0b0110 , def_IS_VBU; rx_cal_dec_val_f, 0b0111 , def_IS_HW; rx_cal_dec_val_f, 0b0000 , def_IS_VBU; rx_cal_dec_val_g, 0b0111 , def_IS_HW; rx_cal_dec_val_g, 0b0000 , def_IS_VBU; rx_cal_dec_val_h, 0b0111 , def_IS_HW; rx_cal_dec_val_h, 0b0000 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP scom 0x800B2020(xbus_base_addr) { bits, scom_data, expr; rx_cal_inc_val_a, 0b0111 , def_IS_HW; rx_cal_inc_val_a, 0b1000 , def_IS_VBU; rx_cal_inc_val_b, 0b0001 , def_IS_HW; rx_cal_inc_val_b, 0b0000 , def_IS_VBU; rx_cal_inc_val_c, 0b0111 , def_IS_HW; rx_cal_inc_val_c, 0b0000 , def_IS_VBU; rx_cal_inc_val_d, 0b0111 , def_IS_HW; rx_cal_inc_val_d, 0b0110 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP scom 0x800B2820(xbus_base_addr) { bits, scom_data, expr; rx_cal_inc_val_e, 0b0111 , def_IS_HW; rx_cal_inc_val_e, 0b0110 , def_IS_VBU; rx_cal_inc_val_f, 0b0111 , def_IS_HW; rx_cal_inc_val_f, 0b0000 , def_IS_VBU; rx_cal_inc_val_g, 0b0111 , def_IS_HW; rx_cal_inc_val_g, 0b0000 , def_IS_VBU; rx_cal_inc_val_h, 0b0111 , def_IS_HW; rx_cal_inc_val_h, 0b0000 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG scom 0x800A3820(xbus_base_addr) { bits, scom_data, expr; rx_eo_enable_ber_test, 0b1 , def_IS_HW; rx_eo_enable_ber_test, 0b0 , def_IS_VBU; rx_eo_enable_ctle_cal, 0b1 , def_IS_HW; rx_eo_enable_ctle_cal, 0b0 , def_IS_VBU; rx_eo_enable_dcd_cal, 0b1 , def_IS_HW; rx_eo_enable_dcd_cal, 0b0 , def_IS_VBU; rx_eo_enable_final_l2u_adj, 0b1, any; rx_eo_enable_latch_offset_cal, 0b1 , def_IS_HW; rx_eo_enable_latch_offset_cal, 0b0 , def_IS_VBU; rx_eo_enable_measure_eye_width, 0b1 , def_IS_HW; rx_eo_enable_measure_eye_width, 0b0 , def_IS_VBU; rx_eo_enable_result_check, 0b1 , def_IS_HW; rx_eo_enable_result_check, 0b0 , def_IS_VBU; rx_eo_enable_vref_cal, 0b1 , def_IS_HW; rx_eo_enable_vref_cal, 0b0 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_FENCE_PG scom 0x8009A820(xbus_base_addr) { bits, scom_data, expr; rx_fence, 0b1, any; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG scom 0x80085020(xbus_base_addr) { bits, scom_data, expr; rx_bus_id, 0b000000, any; rx_group_id, 0b000001, any; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_ID2_PG scom 0x80085820(xbus_base_addr) { bits, scom_data, expr; rx_last_group_id, 0b000011, any; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_ID3_PG scom 0x80086020(xbus_base_addr) { bits, scom_data, expr; rx_end_lane_id, 0b0100111, any; rx_start_lane_id, 0b0010100, any; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG scom 0x80092820(xbus_base_addr) { bits, scom_data, expr; rx_lane_disabled_vec_0_15, 0b0000000000000000, any; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG scom 0x80093020(xbus_base_addr) { bits, scom_data, expr; rx_lane_disabled_vec_16_31, 0b0000111111111111, any; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_MODE1_PP scom 0x800B0820(xbus_base_addr) { bits, scom_data, expr; rx_bit_lock_timeout_sel, 0b110 , def_IS_HW; rx_bit_lock_timeout_sel, 0b101 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_MODE_PG scom 0x80081820(xbus_base_addr) { bits, scom_data, expr; rx_master_mode, 0b1, def_is_master; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG scom 0x800AB820(xbus_base_addr) { bits, scom_data, expr; rx_rc_enable_dll_update, 0b1 , def_IS_HW; rx_rc_enable_dll_update, 0b0 , def_IS_VBU; rx_rc_enable_edge_track, 0b1 , def_IS_HW; rx_rc_enable_edge_track, 0b0 , def_IS_VBU; rx_rc_enable_measure_eye_width, 0b1 , def_IS_HW; rx_rc_enable_measure_eye_width, 0b0 , def_IS_VBU; rx_rc_enable_result_check, 0b1 , def_IS_HW; rx_rc_enable_result_check, 0b0 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP scom 0x800B6020(xbus_base_addr) { bits, scom_data, expr; rx_servo_timeout_sel_a, 0b0101 , def_IS_HW; rx_servo_timeout_sel_a, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_b, 0b1010 , def_IS_HW; rx_servo_timeout_sel_b, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_c, 0b0101 , def_IS_HW; rx_servo_timeout_sel_c, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_d, 0b1001 , def_IS_HW; rx_servo_timeout_sel_d, 0b0101 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP scom 0x800B6820(xbus_base_addr) { bits, scom_data, expr; rx_servo_timeout_sel_f, 0b1000 , def_IS_HW; rx_servo_timeout_sel_f, 0b0110 , def_IS_VBU; rx_servo_timeout_sel_h, 0b1110 , def_IS_HW; rx_servo_timeout_sel_h, 0b1000 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG scom 0x80080820(xbus_base_addr) { bits, scom_data, expr; rx_sls_extend_sel, 0b101, def_is_slave; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG scom 0x80091020(xbus_base_addr) { bits, scom_data, expr; rx_eo_ctle_timeout_sel, 0b111 , def_IS_HW; rx_eo_ctle_timeout_sel, 0b110 , def_IS_VBU; rx_eo_offset_timeout_sel, 0b111 , def_IS_HW; rx_eo_offset_timeout_sel, 0b110 , def_IS_VBU; rx_eo_vref_timeout_sel, 0b111 , def_IS_HW; rx_eo_vref_timeout_sel, 0b110 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG scom 0x80089820(xbus_base_addr) { bits, scom_data, expr; rx_ds_bl_timeout_sel, 0b101 , def_IS_HW; rx_ds_bl_timeout_sel, 0b001 , def_IS_VBU; rx_ds_timeout_sel, 0b110 , def_IS_HW; rx_ds_timeout_sel, 0b010 , def_IS_VBU; rx_sls_timeout_sel, 0b110, any; rx_wt_timeout_sel, 0b111 , def_IS_HW; rx_wt_timeout_sel, 0b011 , def_IS_VBU; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG scom 0x80099820(xbus_base_addr) { bits, scom_data, expr; rx_rx_bus_width, 0b1010000, any; rx_tx_bus_width, 0b1010000, any; } #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG scom 0x80095820(xbus_base_addr) { bits, scom_data, expr; rx_wtr_max_bad_lanes, 0b00010, any; } #RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B020(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B021(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B022(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b010, any; } #RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B023(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b011, any; } #RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B024(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b100, any; } #RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B025(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b101, any; } #RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B026(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b110, any; } #RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B027(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b111, any; } #RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B028(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B029(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B02A(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B02B(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B02C(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b111, any; } #RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B02D(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b110, any; } #RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B02E(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b101, any; } #RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B02F(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b100, any; } #RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B030(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b011, any; } #RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B031(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b010, any; } #RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B032(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B033(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG scom 0x800AF040(xbus_base_addr) { bits, scom_data, expr; rx_max_ber_check_count, 0b00000011 , def_IS_HW; rx_max_ber_check_count, 0b00000000 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_DLL_ANALOG_TWEAKS_PG scom 0x800E7840(xbus_base_addr) { bits, scom_data, expr; rx_dll1_vreg_drvcon, 0b111 , def_IS_HW; rx_dll1_vreg_drvcon, 0b000 , def_IS_VBU; rx_dll2_vreg_drvcon, 0b111 , def_IS_HW; rx_dll2_vreg_drvcon, 0b000 , def_IS_VBU; rx_dll_vreg_compcon, 0b101 , def_IS_HW; rx_dll_vreg_compcon, 0b000 , def_IS_VBU; rx_dll_vreg_dac_pullup, 0b1 , def_IS_HW; rx_dll_vreg_dac_pullup, 0b0 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG scom 0x8009D840(xbus_base_addr) { bits, scom_data, expr; rx_dyn_rpr_bad_lane_max, 0b0001111, any; rx_dyn_rpr_enc_bad_data_lane_width, 0b111, any; rx_dyn_rpr_err_cntr1_duration, 0b1010, any; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG scom 0x800AE040(xbus_base_addr) { bits, scom_data, expr; rx_dyn_rpr_bad_bus_max, 0b0011111, any; rx_dyn_rpr_err_cntr2_duration, 0b0111, any; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP scom 0x800B1840(xbus_base_addr) { bits, scom_data, expr; rx_ddc_use_cyc_block_lock, 0b0 , def_IS_HW; rx_ddc_use_cyc_block_lock, 0b1 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP scom 0x800B3040(xbus_base_addr) { bits, scom_data, expr; rx_cal_dec_val_a, 0b0111 , def_IS_HW; rx_cal_dec_val_a, 0b1000 , def_IS_VBU; rx_cal_dec_val_b, 0b0001 , def_IS_HW; rx_cal_dec_val_b, 0b0000 , def_IS_VBU; rx_cal_dec_val_c, 0b0111 , def_IS_HW; rx_cal_dec_val_c, 0b0000 , def_IS_VBU; rx_cal_dec_val_d, 0b0111 , def_IS_HW; rx_cal_dec_val_d, 0b0110 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP scom 0x800B3840(xbus_base_addr) { bits, scom_data, expr; rx_cal_dec_val_e, 0b0111 , def_IS_HW; rx_cal_dec_val_e, 0b0110 , def_IS_VBU; rx_cal_dec_val_f, 0b0111 , def_IS_HW; rx_cal_dec_val_f, 0b0000 , def_IS_VBU; rx_cal_dec_val_g, 0b0111 , def_IS_HW; rx_cal_dec_val_g, 0b0000 , def_IS_VBU; rx_cal_dec_val_h, 0b0111 , def_IS_HW; rx_cal_dec_val_h, 0b0000 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP scom 0x800B2040(xbus_base_addr) { bits, scom_data, expr; rx_cal_inc_val_a, 0b0111 , def_IS_HW; rx_cal_inc_val_a, 0b1000 , def_IS_VBU; rx_cal_inc_val_b, 0b0001 , def_IS_HW; rx_cal_inc_val_b, 0b0000 , def_IS_VBU; rx_cal_inc_val_c, 0b0111 , def_IS_HW; rx_cal_inc_val_c, 0b0000 , def_IS_VBU; rx_cal_inc_val_d, 0b0111 , def_IS_HW; rx_cal_inc_val_d, 0b0110 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP scom 0x800B2840(xbus_base_addr) { bits, scom_data, expr; rx_cal_inc_val_e, 0b0111 , def_IS_HW; rx_cal_inc_val_e, 0b0110 , def_IS_VBU; rx_cal_inc_val_f, 0b0111 , def_IS_HW; rx_cal_inc_val_f, 0b0000 , def_IS_VBU; rx_cal_inc_val_g, 0b0111 , def_IS_HW; rx_cal_inc_val_g, 0b0000 , def_IS_VBU; rx_cal_inc_val_h, 0b0111 , def_IS_HW; rx_cal_inc_val_h, 0b0000 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG scom 0x800A3840(xbus_base_addr) { bits, scom_data, expr; rx_eo_enable_ber_test, 0b1 , def_IS_HW; rx_eo_enable_ber_test, 0b0 , def_IS_VBU; rx_eo_enable_ctle_cal, 0b1 , def_IS_HW; rx_eo_enable_ctle_cal, 0b0 , def_IS_VBU; rx_eo_enable_dcd_cal, 0b1 , def_IS_HW; rx_eo_enable_dcd_cal, 0b0 , def_IS_VBU; rx_eo_enable_final_l2u_adj, 0b1, any; rx_eo_enable_latch_offset_cal, 0b1 , def_IS_HW; rx_eo_enable_latch_offset_cal, 0b0 , def_IS_VBU; rx_eo_enable_measure_eye_width, 0b1 , def_IS_HW; rx_eo_enable_measure_eye_width, 0b0 , def_IS_VBU; rx_eo_enable_result_check, 0b1 , def_IS_HW; rx_eo_enable_result_check, 0b0 , def_IS_VBU; rx_eo_enable_vref_cal, 0b1 , def_IS_HW; rx_eo_enable_vref_cal, 0b0 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG scom 0x8009A840(xbus_base_addr) { bits, scom_data, expr; rx_fence, 0b1, any; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG scom 0x80085040(xbus_base_addr) { bits, scom_data, expr; rx_bus_id, 0b000000, any; rx_group_id, 0b000010, any; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_ID2_PG scom 0x80085840(xbus_base_addr) { bits, scom_data, expr; rx_last_group_id, 0b000011, any; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_ID3_PG scom 0x80086040(xbus_base_addr) { bits, scom_data, expr; rx_end_lane_id, 0b0111011, any; rx_start_lane_id, 0b0101000, any; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG scom 0x80092840(xbus_base_addr) { bits, scom_data, expr; rx_lane_disabled_vec_0_15, 0b0000000000000000, any; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG scom 0x80093040(xbus_base_addr) { bits, scom_data, expr; rx_lane_disabled_vec_16_31, 0b0000111111111111, any; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_MODE1_PP scom 0x800B0840(xbus_base_addr) { bits, scom_data, expr; rx_bit_lock_timeout_sel, 0b110 , def_IS_HW; rx_bit_lock_timeout_sel, 0b101 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG scom 0x80081840(xbus_base_addr) { bits, scom_data, expr; rx_master_mode, 0b1, def_is_master; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG scom 0x800AB840(xbus_base_addr) { bits, scom_data, expr; rx_rc_enable_dll_update, 0b1 , def_IS_HW; rx_rc_enable_dll_update, 0b0 , def_IS_VBU; rx_rc_enable_edge_track, 0b1 , def_IS_HW; rx_rc_enable_edge_track, 0b0 , def_IS_VBU; rx_rc_enable_measure_eye_width, 0b1 , def_IS_HW; rx_rc_enable_measure_eye_width, 0b0 , def_IS_VBU; rx_rc_enable_result_check, 0b1 , def_IS_HW; rx_rc_enable_result_check, 0b0 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP scom 0x800B6040(xbus_base_addr) { bits, scom_data, expr; rx_servo_timeout_sel_a, 0b0101 , def_IS_HW; rx_servo_timeout_sel_a, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_b, 0b1010 , def_IS_HW; rx_servo_timeout_sel_b, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_c, 0b0101 , def_IS_HW; rx_servo_timeout_sel_c, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_d, 0b1001 , def_IS_HW; rx_servo_timeout_sel_d, 0b0101 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP scom 0x800B6840(xbus_base_addr) { bits, scom_data, expr; rx_servo_timeout_sel_f, 0b1000 , def_IS_HW; rx_servo_timeout_sel_f, 0b0110 , def_IS_VBU; rx_servo_timeout_sel_h, 0b1110 , def_IS_HW; rx_servo_timeout_sel_h, 0b1000 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG scom 0x80080840(xbus_base_addr) { bits, scom_data, expr; rx_sls_extend_sel, 0b101, def_is_slave; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG scom 0x80091040(xbus_base_addr) { bits, scom_data, expr; rx_eo_ctle_timeout_sel, 0b111 , def_IS_HW; rx_eo_ctle_timeout_sel, 0b110 , def_IS_VBU; rx_eo_offset_timeout_sel, 0b111 , def_IS_HW; rx_eo_offset_timeout_sel, 0b110 , def_IS_VBU; rx_eo_vref_timeout_sel, 0b111 , def_IS_HW; rx_eo_vref_timeout_sel, 0b110 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG scom 0x80089840(xbus_base_addr) { bits, scom_data, expr; rx_ds_bl_timeout_sel, 0b101 , def_IS_HW; rx_ds_bl_timeout_sel, 0b001 , def_IS_VBU; rx_ds_timeout_sel, 0b110 , def_IS_HW; rx_ds_timeout_sel, 0b010 , def_IS_VBU; rx_sls_timeout_sel, 0b110, any; rx_wt_timeout_sel, 0b111 , def_IS_HW; rx_wt_timeout_sel, 0b011 , def_IS_VBU; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG scom 0x80099840(xbus_base_addr) { bits, scom_data, expr; rx_rx_bus_width, 0b1010000, any; rx_tx_bus_width, 0b1010000, any; } #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG scom 0x80095840(xbus_base_addr) { bits, scom_data, expr; rx_wtr_max_bad_lanes, 0b00010, any; } #RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B040(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B041(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B042(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b010, any; } #RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B043(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b011, any; } #RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B044(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b100, any; } #RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B045(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b101, any; } #RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B046(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b110, any; } #RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B047(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b111, any; } #RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B048(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B049(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B04A(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B04B(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B04C(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b111, any; } #RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B04D(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b110, any; } #RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B04E(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b101, any; } #RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B04F(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b100, any; } #RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B050(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b011, any; } #RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B051(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b010, any; } #RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B052(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B053(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG scom 0x800AF060(xbus_base_addr) { bits, scom_data, expr; rx_max_ber_check_count, 0b00000011 , def_IS_HW; rx_max_ber_check_count, 0b00000000 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_DLL_ANALOG_TWEAKS_PG scom 0x800E7860(xbus_base_addr) { bits, scom_data, expr; rx_dll1_vreg_drvcon, 0b111 , def_IS_HW; rx_dll1_vreg_drvcon, 0b000 , def_IS_VBU; rx_dll2_vreg_drvcon, 0b111 , def_IS_HW; rx_dll2_vreg_drvcon, 0b000 , def_IS_VBU; rx_dll_vreg_compcon, 0b101 , def_IS_HW; rx_dll_vreg_compcon, 0b000 , def_IS_VBU; rx_dll_vreg_dac_pullup, 0b1 , def_IS_HW; rx_dll_vreg_dac_pullup, 0b0 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG scom 0x8009D860(xbus_base_addr) { bits, scom_data, expr; rx_dyn_rpr_bad_lane_max, 0b0001111, any; rx_dyn_rpr_enc_bad_data_lane_width, 0b111, any; rx_dyn_rpr_err_cntr1_duration, 0b1010, any; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG scom 0x800AE060(xbus_base_addr) { bits, scom_data, expr; rx_dyn_rpr_bad_bus_max, 0b0011111, any; rx_dyn_rpr_err_cntr2_duration, 0b0111, any; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP scom 0x800B1860(xbus_base_addr) { bits, scom_data, expr; rx_ddc_use_cyc_block_lock, 0b0 , def_IS_HW; rx_ddc_use_cyc_block_lock, 0b1 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP scom 0x800B3060(xbus_base_addr) { bits, scom_data, expr; rx_cal_dec_val_a, 0b0111 , def_IS_HW; rx_cal_dec_val_a, 0b1000 , def_IS_VBU; rx_cal_dec_val_b, 0b0001 , def_IS_HW; rx_cal_dec_val_b, 0b0000 , def_IS_VBU; rx_cal_dec_val_c, 0b0111 , def_IS_HW; rx_cal_dec_val_c, 0b0000 , def_IS_VBU; rx_cal_dec_val_d, 0b0111 , def_IS_HW; rx_cal_dec_val_d, 0b0110 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP scom 0x800B3860(xbus_base_addr) { bits, scom_data, expr; rx_cal_dec_val_e, 0b0111 , def_IS_HW; rx_cal_dec_val_e, 0b0110 , def_IS_VBU; rx_cal_dec_val_f, 0b0111 , def_IS_HW; rx_cal_dec_val_f, 0b0000 , def_IS_VBU; rx_cal_dec_val_g, 0b0111 , def_IS_HW; rx_cal_dec_val_g, 0b0000 , def_IS_VBU; rx_cal_dec_val_h, 0b0111 , def_IS_HW; rx_cal_dec_val_h, 0b0000 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP scom 0x800B2060(xbus_base_addr) { bits, scom_data, expr; rx_cal_inc_val_a, 0b0111 , def_IS_HW; rx_cal_inc_val_a, 0b1000 , def_IS_VBU; rx_cal_inc_val_b, 0b0001 , def_IS_HW; rx_cal_inc_val_b, 0b0000 , def_IS_VBU; rx_cal_inc_val_c, 0b0111 , def_IS_HW; rx_cal_inc_val_c, 0b0000 , def_IS_VBU; rx_cal_inc_val_d, 0b0111 , def_IS_HW; rx_cal_inc_val_d, 0b0110 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP scom 0x800B2860(xbus_base_addr) { bits, scom_data, expr; rx_cal_inc_val_e, 0b0111 , def_IS_HW; rx_cal_inc_val_e, 0b0110 , def_IS_VBU; rx_cal_inc_val_f, 0b0111 , def_IS_HW; rx_cal_inc_val_f, 0b0000 , def_IS_VBU; rx_cal_inc_val_g, 0b0111 , def_IS_HW; rx_cal_inc_val_g, 0b0000 , def_IS_VBU; rx_cal_inc_val_h, 0b0111 , def_IS_HW; rx_cal_inc_val_h, 0b0000 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG scom 0x800A3860(xbus_base_addr) { bits, scom_data, expr; rx_eo_enable_ber_test, 0b1 , def_IS_HW; rx_eo_enable_ber_test, 0b0 , def_IS_VBU; rx_eo_enable_ctle_cal, 0b1 , def_IS_HW; rx_eo_enable_ctle_cal, 0b0 , def_IS_VBU; rx_eo_enable_dcd_cal, 0b1 , def_IS_HW; rx_eo_enable_dcd_cal, 0b0 , def_IS_VBU; rx_eo_enable_final_l2u_adj, 0b1, any; rx_eo_enable_latch_offset_cal, 0b1 , def_IS_HW; rx_eo_enable_latch_offset_cal, 0b0 , def_IS_VBU; rx_eo_enable_measure_eye_width, 0b1 , def_IS_HW; rx_eo_enable_measure_eye_width, 0b0 , def_IS_VBU; rx_eo_enable_result_check, 0b1 , def_IS_HW; rx_eo_enable_result_check, 0b0 , def_IS_VBU; rx_eo_enable_vref_cal, 0b1 , def_IS_HW; rx_eo_enable_vref_cal, 0b0 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_FENCE_PG scom 0x8009A860(xbus_base_addr) { bits, scom_data, expr; rx_fence, 0b1, any; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG scom 0x80085060(xbus_base_addr) { bits, scom_data, expr; rx_bus_id, 0b000000, any; rx_group_id, 0b000011, any; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_ID2_PG scom 0x80085860(xbus_base_addr) { bits, scom_data, expr; rx_last_group_id, 0b000011, any; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_ID3_PG scom 0x80086060(xbus_base_addr) { bits, scom_data, expr; rx_end_lane_id, 0b1001111, any; rx_start_lane_id, 0b0111100, any; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG scom 0x80092860(xbus_base_addr) { bits, scom_data, expr; rx_lane_disabled_vec_0_15, 0b0000000000000000, any; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG scom 0x80093060(xbus_base_addr) { bits, scom_data, expr; rx_lane_disabled_vec_16_31, 0b0000111111111111, any; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_MODE1_PP scom 0x800B0860(xbus_base_addr) { bits, scom_data, expr; rx_bit_lock_timeout_sel, 0b110 , def_IS_HW; rx_bit_lock_timeout_sel, 0b101 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_MODE_PG scom 0x80081860(xbus_base_addr) { bits, scom_data, expr; rx_master_mode, 0b1, def_is_master; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG scom 0x800AB860(xbus_base_addr) { bits, scom_data, expr; rx_rc_enable_dll_update, 0b1 , def_IS_HW; rx_rc_enable_dll_update, 0b0 , def_IS_VBU; rx_rc_enable_edge_track, 0b1 , def_IS_HW; rx_rc_enable_edge_track, 0b0 , def_IS_VBU; rx_rc_enable_measure_eye_width, 0b1 , def_IS_HW; rx_rc_enable_measure_eye_width, 0b0 , def_IS_VBU; rx_rc_enable_result_check, 0b1 , def_IS_HW; rx_rc_enable_result_check, 0b0 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP scom 0x800B6060(xbus_base_addr) { bits, scom_data, expr; rx_servo_timeout_sel_a, 0b0101 , def_IS_HW; rx_servo_timeout_sel_a, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_b, 0b1010 , def_IS_HW; rx_servo_timeout_sel_b, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_c, 0b0101 , def_IS_HW; rx_servo_timeout_sel_c, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_d, 0b1001 , def_IS_HW; rx_servo_timeout_sel_d, 0b0101 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP scom 0x800B6860(xbus_base_addr) { bits, scom_data, expr; rx_servo_timeout_sel_f, 0b1000 , def_IS_HW; rx_servo_timeout_sel_f, 0b0110 , def_IS_VBU; rx_servo_timeout_sel_h, 0b1110 , def_IS_HW; rx_servo_timeout_sel_h, 0b1000 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG scom 0x80080860(xbus_base_addr) { bits, scom_data, expr; rx_sls_extend_sel, 0b101, def_is_slave; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG scom 0x80091060(xbus_base_addr) { bits, scom_data, expr; rx_eo_ctle_timeout_sel, 0b111 , def_IS_HW; rx_eo_ctle_timeout_sel, 0b110 , def_IS_VBU; rx_eo_offset_timeout_sel, 0b111 , def_IS_HW; rx_eo_offset_timeout_sel, 0b110 , def_IS_VBU; rx_eo_vref_timeout_sel, 0b111 , def_IS_HW; rx_eo_vref_timeout_sel, 0b110 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG scom 0x80089860(xbus_base_addr) { bits, scom_data, expr; rx_ds_bl_timeout_sel, 0b101 , def_IS_HW; rx_ds_bl_timeout_sel, 0b001 , def_IS_VBU; rx_ds_timeout_sel, 0b110 , def_IS_HW; rx_ds_timeout_sel, 0b010 , def_IS_VBU; rx_sls_timeout_sel, 0b110, any; rx_wt_timeout_sel, 0b111 , def_IS_HW; rx_wt_timeout_sel, 0b011 , def_IS_VBU; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG scom 0x80099860(xbus_base_addr) { bits, scom_data, expr; rx_rx_bus_width, 0b1010000, any; rx_tx_bus_width, 0b1010000, any; } #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG scom 0x80095860(xbus_base_addr) { bits, scom_data, expr; rx_wtr_max_bad_lanes, 0b00010, any; } #RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B060(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B061(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B062(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b010, any; } #RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B063(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b011, any; } #RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B064(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b100, any; } #RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B065(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b101, any; } #RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B066(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b110, any; } #RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B067(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b111, any; } #RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B068(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B069(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06A(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06B(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06C(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b111, any; } #RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06D(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b110, any; } #RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06E(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b101, any; } #RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06F(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b100, any; } #RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B070(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b011, any; } #RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B071(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b010, any; } #RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B072(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B073(xbus_base_addr) { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG scom 0x800CC400(xbus_base_addr) { bits, scom_data, expr; tx_drv_clk_pattern_gcrmsg, 0b00, any; } #TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG scom 0x800C9400(xbus_base_addr) { bits, scom_data, expr; tx_bus_id, 0b000000, any; tx_group_id, 0b100000, any; } #TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_ID2_PG scom 0x800C9C00(xbus_base_addr) { bits, scom_data, expr; tx_last_group_id, 0b100011, any; } #TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_ID3_PG scom 0x800CA400(xbus_base_addr) { bits, scom_data, expr; tx_end_lane_id, 0b0010011, any; tx_start_lane_id, 0b0000000, any; } #TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG scom 0x800D1C00(xbus_base_addr) { bits, scom_data, expr; tx_lane_disabled_vec_0_15, 0b0000000000000000, any; } #TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG scom 0x800D2400(xbus_base_addr) { bits, scom_data, expr; tx_lane_disabled_vec_16_31, 0b0000111111111111, any; } #TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_MODE_PG scom 0x800C1C00(xbus_base_addr) { bits, scom_data, expr; tx_max_bad_lanes, 0b00010, any; } #TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043400(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043401(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043402(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b010, any; } #TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043403(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b011, any; } #TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043404(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b100, any; } #TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043405(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b101, any; } #TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043406(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b110, any; } #TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043407(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b111, any; } #TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043408(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043409(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340A(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340B(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340C(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b111, any; } #TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340D(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b110, any; } #TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340E(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b101, any; } #TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340F(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b100, any; } #TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043410(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b011, any; } #TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043411(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b010, any; } #TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043412(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043413(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG scom 0x800CC420(xbus_base_addr) { bits, scom_data, expr; tx_drv_clk_pattern_gcrmsg, 0b00, any; } #TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG scom 0x800C9420(xbus_base_addr) { bits, scom_data, expr; tx_bus_id, 0b000000, any; tx_group_id, 0b100001, any; } #TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_ID2_PG scom 0x800C9C20(xbus_base_addr) { bits, scom_data, expr; tx_last_group_id, 0b100011, any; } #TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_ID3_PG scom 0x800CA420(xbus_base_addr) { bits, scom_data, expr; tx_end_lane_id, 0b0100111, any; tx_start_lane_id, 0b0010100, any; } #TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG scom 0x800D1C20(xbus_base_addr) { bits, scom_data, expr; tx_lane_disabled_vec_0_15, 0b0000000000000000, any; } #TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG scom 0x800D2420(xbus_base_addr) { bits, scom_data, expr; tx_lane_disabled_vec_16_31, 0b0000111111111111, any; } #TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_MODE_PG scom 0x800C1C20(xbus_base_addr) { bits, scom_data, expr; tx_max_bad_lanes, 0b00010, any; } #TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043420(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043421(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043422(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b010, any; } #TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043423(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b011, any; } #TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043424(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b100, any; } #TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043425(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b101, any; } #TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043426(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b110, any; } #TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043427(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b111, any; } #TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043428(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043429(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004342A(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004342B(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004342C(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b111, any; } #TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004342D(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b110, any; } #TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004342E(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b101, any; } #TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004342F(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b100, any; } #TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043430(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b011, any; } #TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043431(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b010, any; } #TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043432(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043433(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG scom 0x800CC440(xbus_base_addr) { bits, scom_data, expr; tx_drv_clk_pattern_gcrmsg, 0b00, any; } #TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG scom 0x800C9440(xbus_base_addr) { bits, scom_data, expr; tx_bus_id, 0b000000, any; tx_group_id, 0b100010, any; } #TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_ID2_PG scom 0x800C9C40(xbus_base_addr) { bits, scom_data, expr; tx_last_group_id, 0b100011, any; } #TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_ID3_PG scom 0x800CA440(xbus_base_addr) { bits, scom_data, expr; tx_end_lane_id, 0b0111011, any; tx_start_lane_id, 0b0101000, any; } #TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG scom 0x800D1C40(xbus_base_addr) { bits, scom_data, expr; tx_lane_disabled_vec_0_15, 0b0000000000000000, any; } #TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG scom 0x800D2440(xbus_base_addr) { bits, scom_data, expr; tx_lane_disabled_vec_16_31, 0b0000111111111111, any; } #TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_MODE_PG scom 0x800C1C40(xbus_base_addr) { bits, scom_data, expr; tx_max_bad_lanes, 0b00010, any; } #TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043440(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043441(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043442(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b010, any; } #TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043443(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b011, any; } #TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043444(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b100, any; } #TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043445(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b101, any; } #TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043446(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b110, any; } #TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043447(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b111, any; } #TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043448(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043449(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004344A(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004344B(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004344C(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b111, any; } #TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004344D(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b110, any; } #TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004344E(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b101, any; } #TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004344F(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b100, any; } #TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043450(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b011, any; } #TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043451(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b010, any; } #TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043452(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043453(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG scom 0x800CC460(xbus_base_addr) { bits, scom_data, expr; tx_drv_clk_pattern_gcrmsg, 0b00, any; } #TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG scom 0x800C9460(xbus_base_addr) { bits, scom_data, expr; tx_bus_id, 0b000000, any; tx_group_id, 0b100011, any; } #TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_ID2_PG scom 0x800C9C60(xbus_base_addr) { bits, scom_data, expr; tx_last_group_id, 0b100011, any; } #TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_ID3_PG scom 0x800CA460(xbus_base_addr) { bits, scom_data, expr; tx_end_lane_id, 0b1001111, any; tx_start_lane_id, 0b0111100, any; } #TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG scom 0x800D1C60(xbus_base_addr) { bits, scom_data, expr; tx_lane_disabled_vec_0_15, 0b0000000000000000, any; } #TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG scom 0x800D2460(xbus_base_addr) { bits, scom_data, expr; tx_lane_disabled_vec_16_31, 0b0000111111111111, any; } #TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_MODE_PG scom 0x800C1C60(xbus_base_addr) { bits, scom_data, expr; tx_max_bad_lanes, 0b00010, any; } #TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043460(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043461(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043462(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b010, any; } #TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043463(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b011, any; } #TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043464(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b100, any; } #TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043465(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b101, any; } #TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043466(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b110, any; } #TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043467(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b111, any; } #TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043468(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043469(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346A(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346B(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346C(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b111, any; } #TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346D(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b110, any; } #TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346E(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b101, any; } #TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346F(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b100, any; } #TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043470(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b011, any; } #TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043471(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b010, any; } #TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043472(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x80043473(xbus_base_addr) { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } ###################################### ## END OF FILE #######################################