#-- $Id: p8.xbus.custom.scom.initfile,v 1.11 2015/04/13 16:17:02 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- #-- 1.11|jgrell |04/25/15|Updated attribute to system type at Thi's request so it can be applied to Brazos only. (SW299500) #-- 1.10|jmcgill |03/24/15|remove l2u delay settings,given filter bypass soln (SW299659) #-- 1.9 |jgrell |02/25/15|Added rx_fifo_final_l2u_dly for Venice only (SW296793) #-- 1.8 |garyp |02/19/14|Added rx_min_eye_width for manufacturing and lab thresholding #-- 1.7 |jgrell |12/03/13|Set rx_sls_extend_sel to 001 for DD2 #-- 1.5 |jgrell |09/17/13|Added DD2 specific inits #-- 1.3 |jgrell |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab. #-- 1.2 |thomsen |02/13/13|Cleaned up and Added Commented-out Lane Power Ups #-- | | |Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab. #-- 1.1 |thomsen |01/29/13|Created initial version #-- --------|--------|--------|-------------------------------------------------- #-------------------------------------------------------------------------------- # End of revision history #-------------------------------------------------------------------------------- #-- TARGETS: #-- SYS. Chiplet target #-- TGT1. Proc target #-- TGT2. Connected Chiplet target #-- TGT3. Connected Proc target #--Master list of variables that can be used in this file is at: #-- SyntaxVersion = 1 #-- ----------------------------------------------------------------------------- #--****************************************************************************** #-- ----------------------------------------------------------------------------- #-- #-- Includes #-- Note: Must include the path to the .define file. #-- ----------------------------------------------------------------------------- #--****************************************************************************** #-- ----------------------------------------------------------------------------- include ei4.io.define #-- ----------------------------------------------------------------------------- #--****************************************************************************** #-- ----------------------------------------------------------------------------- #-- #-- Defines #-- #-- ----------------------------------------------------------------------------- #--****************************************************************************** #-- ----------------------------------------------------------------------------- define def_IS_HW = (SYS.ATTR_IS_SIMULATION == 0); define def_IS_VBU = (SYS.ATTR_IS_SIMULATION == 1); define def_all_lanes=11111; #--*********************************************************************************** #------------------------------------------------------------------------------------- #-- Overrides #------------------------------------------------------------------------------------- #--*********************************************************************************** #--***************** #-- set rx_min_eye_width if in manufacturing mode #--***************** scom 0x800.0b(rx_result_chk_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_min_eye_width, SYS.ATTR_MNFG_XBUS_MIN_EYE_WIDTH, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); } scom 0x800.0b(rx_result_chk_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_min_eye_width, SYS.ATTR_MNFG_XBUS_MIN_EYE_WIDTH, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); } scom 0x800.0b(rx_result_chk_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_min_eye_width, SYS.ATTR_MNFG_XBUS_MIN_EYE_WIDTH, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); } scom 0x800.0b(rx_result_chk_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_min_eye_width, SYS.ATTR_MNFG_XBUS_MIN_EYE_WIDTH, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); } #--*********************************************************************************** #------------------------------------------------------------------------------------- # __ ____ __ __ # / / ____ _____ ___ / __ \____ _ _____ _____ / / / /___ # / / / __ `/ __ \/ _ \ / /_/ / __ \ | /| / / _ \/ ___/ / / / / __ \ # / /___/ /_/ / / / / __/ / ____/ /_/ / |/ |/ / __/ / / /_/ / /_/ / # /_____/\__,_/_/ /_/\___/ /_/ \____/|__/|__/\___/_/ \____/ .___/ # /_/ #------------------------------------------------------------------------------------- #--*********************************************************************************** ## rx_lane_pdwn #scom 0x800.0b(rx_mode_pl)(rx_grp0)(def_all_lanes).0x(xbus0_gcr_addr){ # bits, scom_data; # rx_lane_pdwn, 0b0; #} # ## tx_lane_pdwn #scom 0x800.0b(tx_mode_pl)(tx_grp0)(def_all_lanes).0x(xbus0_gcr_addr){ # bits, scom_data; # tx_lane_pdwn, 0b0; #} #--************************************************************************************************************** #---------------------------------------------------------------------------------------------------------------- # Brazos Specific Inits #---------------------------------------------------------------------------------------------------------------- #--************************************************************************************************************** scom 0x800.0b(rx_fifo_mode_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_fifo_final_l2u_dly, 0b0100, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; } scom 0x800.0b(rx_fifo_mode_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_fifo_final_l2u_dly, 0b0100, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; } scom 0x800.0b(rx_fifo_mode_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_fifo_final_l2u_dly, 0b0100, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; } scom 0x800.0b(rx_fifo_mode_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_fifo_final_l2u_dly, 0b0100, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; } #--*********************************************************************************** #------------------------------------------------------------------------------------- #-- DD2+ Murano & Venice #------------------------------------------------------------------------------------- #--*********************************************************************************** scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_sls_timeout_sel_dd2, 0b1010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_ds_timeout_sel_dd2, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; } scom 0x800.0b(rx_timeout_sel_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_sls_timeout_sel_dd2, 0b1010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_ds_timeout_sel_dd2, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; } scom 0x800.0b(rx_timeout_sel_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_sls_timeout_sel_dd2, 0b1010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_ds_timeout_sel_dd2, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; } scom 0x800.0b(rx_timeout_sel_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_sls_timeout_sel_dd2, 0b1010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_ds_timeout_sel_dd2, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; } scom 0x800.0b(rx_spare_mode_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_sls_extend_sel, 0b001, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; } scom 0x800.0b(rx_spare_mode_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_sls_extend_sel, 0b001, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; } scom 0x800.0b(rx_spare_mode_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_sls_extend_sel, 0b001, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; } scom 0x800.0b(rx_spare_mode_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; rx_sls_extend_sel, 0b001, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; } ############################################################################################ # END OF FILE ############################################################################################