#-- $Id: p8.pe.phase2.scom.initfile,v 1.8 2015/06/11 20:32:23 ricmata Exp $
#-------------------------------------------------------------------------------
#--
#-- (C) Copyright International Business Machines Corp. 2011
#-- All Rights Reserved -- Property of IBM
#-- ***  ***
#--
#-- TITLE       : p8.pcie.phase2.scom.initfile
#-- DESCRIPTION : Perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-17)
#--
#-- OWNER NAME  : Joe McDonald            Email: joemc@us.ibm.com
#-- OWNER NAME  : Rick Mata               Email: ricmata@us.ibm.com
#--
#--------------------------------------------------------------------------------

SyntaxVersion = 1

#--------------------------------------------------------------------------------
#-- Includes
#--------------------------------------------------------------------------------

#--------------------------------------------------------------------------------
#-- Defines
#--------------------------------------------------------------------------------

define phb0 = (ATTR_PROC_PCIE_NUM_PHB >= 1);
define phb1 = (ATTR_PROC_PCIE_NUM_PHB >= 2);
define phb2 = (ATTR_PROC_PCIE_NUM_PHB >= 3);
define phb3 = (ATTR_PROC_PCIE_NUM_PHB >= 4);

define def_nest_freq_r0 = (SYS.ATTR_FREQ_PB >= 2200);
define def_nest_freq_r1 = ((SYS.ATTR_FREQ_PB <= 1700) && (SYS.ATTR_FREQ_PB < 2200));
define def_nest_freq_r2 = (SYS.ATTR_FREQ_PB < 1700);

define enable_enh_ive_ordering = (ATTR_CHIP_EC_FEATURE_ENABLE_IVE_PERFORMANCE_ORDERING != 0);
define enable_dmar_ooo         = (ATTR_CHIP_EC_FEATURE_ENABLE_PCI_DMAR_OOO != 0);


#--------------------------------------------------------------------------------
#-- SCOM initializations
#--------------------------------------------------------------------------------

#-- PBCQ Mode Control Register
scom 0x0201200B {
    bits,    scom_data,    expr;
    6:7,     0b00,	   (phb0);				    #-- disable wr-cache-inject mode for TCPIP performance (SW275459)
    12,      0b1,          (phb0);                                  #-- disable group scope on TCE read requests
    26,      0b1,          (phb0 && enable_enh_ive_ordering);       #-- enable enhanced IVE performance ordering only where supported (HW226407)
    27,      0b1,          (phb0);                                  #-- force IVE write operations to system scope
}

scom 0x0201240B {
    bits,    scom_data,    expr;
    6:7,     0b00,	   (phb1);
    12,      0b1,          (phb1);
    26,      0b1,          (phb1 && enable_enh_ive_ordering);
    27,      0b1,          (phb1);
}

scom 0x0201280B {
    bits,    scom_data,    expr;
    6:7,     0b00,	   (phb2);
    12,      0b1,          (phb2);
    26,      0b1,          (phb2 && enable_enh_ive_ordering);
    27,      0b1,          (phb2);
}

scom 0x02012C0B {
    bits,    scom_data,    expr;
    6:7,     0b00,	   (phb3);
    12,      0b1,          (phb3);                             
    26,      0b1,          (phb3 && enable_enh_ive_ordering);
    27,      0b1,          (phb3);
}

#-- PCI Hardware Configuration 0 Register
scom 0x02012018 {
    bits,    scom_data,    expr;  
    0:3,     0b0001,       (phb0);                                  #-- hang poll scale (reg=1, value of 6)
    4:7,     0b0010,       (phb0);                                  #-- data poll scale (reg=2, value of 9)
    8:11,    0b0001,       (phb0);                                  #-- data poll scale (PE) (reg=1, value of 6)
    17,      0b1,          (phb0);                                  #-- disable out-of-order store behavior
}

scom 0x02012418 {
    bits,    scom_data,    expr;  
    0:3,     0b0001,       (phb1);
    4:7,     0b0010,       (phb1);
    8:11,    0b0001,       (phb1);
    17,      0b1,          (phb1);
}

scom 0x02012818 {
    bits,    scom_data,    expr;  
    0:3,     0b0001,       (phb2);
    4:7,     0b0010,       (phb2);
    8:11,    0b0001,       (phb2);
    17,      0b1,          (phb2);
}

scom 0x02012C18 {
    bits,    scom_data,    expr;
    0:3,     0b0001,       (phb3);
    4:7,     0b0010,       (phb3);
    8:11,    0b0001,       (phb3);
    17,      0b1,          (phb3);
}

#-- PCI Hardware Configuration 1 Register
scom 0x02012019 {
    bits,    scom_data,    expr;
    22,      0b0,          (phb0);                                  #-- diable OOO DMA read
}

scom 0x02012419 {
    bits,    scom_data,    expr;
    22,      0b0,          (phb1);
}

scom 0x02012819 {
    bits,    scom_data,    expr;
    22,      0b0,          (phb2);
}

scom 0x02012C19 {
    bits,    scom_data,    expr;
    22,      0b0,          (phb3);
}

#-- PCI Nest Clock Trace Control Register
scom 0x0201200D {
    bits,    scom_data,    expr;
    0:3,     0b1001,       (phb0);                                  #-- enable trace, select inbound + address info
}

scom 0x0201240D {
    bits,    scom_data,    expr;
    0:3,     0b1001,       (phb1);
}

scom 0x0201280D {
    bits,    scom_data,    expr;
    0:3,     0b1001,       (phb2);
}

scom 0x02012C0D {
    bits,    scom_data,    expr;
    0:3,     0b1001,       (phb3);
}

#-- PB AIB Control/Status Register
scom 0x0901200F {
    bits,    scom_data,    expr;
    0:2,     0b011,        (phb0 && def_nest_freq_r0);              #-- Maximum Ch0 command credit given to ETU
    0:2,     0b010,        (phb0 && def_nest_freq_r1);
    0:2,     0b001,        (phb0 && def_nest_freq_r2);
    3:5,     0b001,        (phb0);                                  #-- Maximum Ch1 command credit given to ETU
    6:8,     0b011,        (phb0 && def_nest_freq_r0);              #-- Maximum Ch2 command credit given to ETU
    6:8,     0b010,        (phb0 && (def_nest_freq_r1 || def_nest_freq_r2));
    9:11,    0b000,        (phb0);                                  #-- Maximum Ch3 command credit given to ETU
    12:13,   0b11,         (phb0);                                  #-- Overcommit of inbound speed matching buffer (HW245629)
    30:31,   0b11,         (phb0);                                  #-- enable PCI clock tracing w/ ETU as default
}

scom 0x0901240F {
    bits,    scom_data,    expr;
    0:2,     0b011,        (phb1 && def_nest_freq_r0);
    0:2,     0b010,        (phb1 && def_nest_freq_r1);
    0:2,     0b001,        (phb1 && def_nest_freq_r2);
    3:5,     0b001,        (phb1);
    6:8,     0b011,        (phb1 && def_nest_freq_r0);
    6:8,     0b010,        (phb1 && (def_nest_freq_r1 || def_nest_freq_r2));
    9:11,    0b000,        (phb1);
    12:13,   0b11,         (phb1);
    30:31,   0b11,         (phb1);
}

scom 0x0901280F {
    bits,    scom_data,    expr;
    0:2,     0b011,        (phb2 && def_nest_freq_r0);
    0:2,     0b010,        (phb2 && def_nest_freq_r1);
    0:2,     0b001,        (phb2 && def_nest_freq_r2);
    3:5,     0b001,        (phb2);
    6:8,     0b011,        (phb2 && def_nest_freq_r0);
    6:8,     0b010,        (phb2 && (def_nest_freq_r1 || def_nest_freq_r2));
    9:11,    0b000,        (phb2);
    12:13,   0b11,         (phb2);
    30:31,   0b11,         (phb2);
}

scom 0x09012C0F {
    bits,    scom_data,    expr;
    0:2,     0b011,        (phb3 && def_nest_freq_r0);
    0:2,     0b010,        (phb3 && def_nest_freq_r1);
    0:2,     0b001,        (phb3 && def_nest_freq_r2);
    3:5,     0b001,        (phb3);
    6:8,     0b011,        (phb3 && def_nest_freq_r0);
    6:8,     0b010,        (phb3 && (def_nest_freq_r1 || def_nest_freq_r2));
    9:11,    0b000,        (phb3);
    12:13,   0b11,         (phb3);
    30:31,   0b11,         (phb3);
}