#-- $Id: p8.mcs.scom.initfile,v 1.21 2014/11/17 21:13:37 baysah Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- #-- | | | #-- 1.21|baysah |11/17/14|- FW630892 : Disable MCS Read Data OctoWord Gathering to prevent dcbz starvation #-- | | |- Don't attempt to enable this workaround for MurDD1.x, because it doesn't exist. #-- | | | #-- 1.20|baysah |11/14/14|- FW630892 : Disable MCS Read Data OctoWord Gathering to prevent dcbz starvation #-- | | | #-- 1.19|baysah |10/22/14|- SW281364 : Remove ATTR_PM_SLEEP_ENABLE condition so MCS workaround for L4-CAPI Deadlock is for all systems types #-- | | |- per Kevin Reick #-- | | | #-- 1.18|baysah |10/20/14|- SW281364 : Use ATTR_PM_SLEEP_ENABLE to enable MCS workaround for L4-CAPI Deadlock for Saphire systems #-- | | |- The workaround disables speculation for dma_pr_w, pte_updt, ci_pr_w and reserves 1 CL machine for reads. #-- | | | #-- 1.17|baysah |09/12/14|- SW277283 : MCS FCI Register is not in Murano DD1.x ... Qualify scom 201181c #-- | | | #-- 1.16|baysah |09/03/14|- SW275492 : MCS Command List Timer Needs to be Extended #-- | | | #-- 1.15|baysah |06/21/14|- SW274463 : Shut down mirror on first mirrored memory UE #-- | | | #-- 1.14|baysah |06/12/14|- SW265488 : enable channel checkstop for MCIFIR[40]: channel timeout error #-- | | | #-- 1.13|baysah |05/20/14|- Added Best MCS Spec filter setting to MODE2 reg (2011809 16 20 9007F) for power and perf improvement #-- | | | #-- 1.12|baysah |01/08/14|- Moved ECC bypass qualifier from MCMODE1(63) TO MCMODE1(62), bit 63 is perfmon. #-- | | | #-- 1.10|jmcgill |05/07/13|- Qualify ECC bypass disable by risk level #-- | | | #-- 1.9|baysah |05/05/13|- Disabled MCMODE1Q_DISABLE_FASTPATH_CRC_ECC_BYPASS and MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL. #-- | | | #-- 1.7|baysah |04/26/13|- Disabled MCMODE0Q_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP per firmware request for MPIPL. #-- | | | #-- 1.6|baysah |04/25/13|- Fix problem with incorrectly setting mcmode0 bit 1 which is marked as reserved, but its actually used to #-- | | |- reset MCS channel fail. #-- | | | #-- 1.4|baysah |04/23/13|- Disable MCS bypass for dd1 less than 2.0 for defect HW247907 #-- | | | #-- 1.3|baysah |04/04/13|- Set MCI Replay timeout value to 2ms. #-- | | |- Disable MCS arbiter blocking after checkstop. #-- | | | #-- --------|--------|--------|-------------------------------------------------- #-- 1.0|baysah |08/12/12|Created MCS init file #-- --------|--------|--------|-------------------------------------------------- #-------------------------------------------------------------------------------- # End of revision history #-------------------------------------------------------------------------------- #--Master list of variables that can be used in this file is at: #-- SyntaxVersion = 1 #-------------------------------------------------------------------------------- #-- Defines #-------------------------------------------------------------------------------- # disable ECC bypass if instructed to by EC feature attribute AND # running risk level 0 define ecc_bypass_disable = ((TGT1.ATTR_CHIP_EC_FEATURE_MCS_ECC_BYPASS_DISABLE != 0x0) && (SYS.ATTR_RISK_LEVEL == ENUM_ATTR_RISK_LEVEL_RL0)); #--****************************************************************************** #-- MCS Mode0 Register #--****************************************************************************** scom 0x0000000002011807 { bits , scom_data , expr ; 0 , 0b1 , any ; # MCMODE0Q_ENABLE_CMD_BYP_STUTTER 1 , 0b0 , any ; # MCMODE0Q_RESERVED Reserved 2 , 0b1 , any ; # MCMODE0Q_ENABLE_NS_RD_AO_SFU_FOR_DCBZ 3 , 0b1 , any ; # MCMODE0Q_ENABLE_CENTAUR_LOCAL_CHECKSTOP_COMMAND 4:7 , 0xF , any ; # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD # 8:11 , 0x0 , any ; # MCMODE0Q_Number_of_CL_Entries_Reserved_for_Read # 8:11 , 0x1 , (SYS.ATTR_PM_SLEEP_ENABLE == 1) ; # CAPI Deadlock workaround 8:11 , 0x1 , any ; # CAPI Deadlock workaround 12:15, 0x1 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_MIRRORED_OPS 16:19, 0x0 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_WRITES 20:23, 0x1 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_CP_WRITES 24:27, 0x1 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_CP_IG 28:31, 0x0 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HTM_OPS 32:35, 0x0 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HA_ASSIST 36 , 0b1 , any ; # MCMODE0Q_MCFGRP_19_IS_HO_BIT 37 , 0b1 , any ; # MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL 38 , 0b0 , any ; # MCMODE0Q_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP 39:43, 0b00000 , any ; # MCMODE0Q_RESERVED_39_43 Reserved 44:52, 0b001100010 , any ; # MCMODE0Q_ADDRESS_COLLISION_MODES 53 , 0b0 , any ; # MCMODE0Q_INCLUDE_CP_IG_IN_CP_WRITE_FULLNESS_GROUP 54 , 0b1 , any ; # MCMODE0Q_ENABLE_DMAWR_CMD_BIT 55 , 0b0 , any ; # MCMODE0Q_ENABLE_READ_LFSR_DATA 56 , 0b0 , any ; # MCMODE0Q_FORCE_CHANNEL_FAIL 57 , 0b0 , any ; # MCMODE0Q_DISABLE_READ_CRC_ECC_BYPASS_TAKEN 58 , 0b0 , any ; # MCMODE0Q_DISABLE_CL_AO_QUEUES 59:60, 0b00 , any ; # MCMODE0Q_ADDRESS_SELECT_LFSR_VALUE (4k) 61 , 0b0 , any ; # MCMODE0Q_ENABLE_CENTAUR_SYNC 62 , 0b0 , any ; # MCMODE0Q_WRITE_DATA_BUFFER_ECC_CHECK_DISABLE 63 , 0b0 , any ; # MCMODE0Q_WRITE_DATA_BUFFER_ECC_CORRECT_DISABLE } #--****************************************************************************** #-- MCS Mode1 Register #--****************************************************************************** scom 0x0000000002011808 { bits , scom_data , expr ; 0 , 0b0 , any ; # MCMODE1Q_DISABLE_ADDRESS_SELECT_LFSR_MODE 1 , 0b0 , any ; # MCMODE1Q_NODAL_SCOPE_MCD_VALID 2:6 , 0b00000 , any ; # MCMODE1Q_DISABLE_HIGH_PRIORITY 7:9 , 0b111 , (ecc_bypass_disable) ; # MCMODE1Q_DISABLE_CRC_ECC_BYPASS 10:15, 0b000000 , any ; # MCMODE1Q_DISABLE_READ_ALLOCATION_TO_CACHE 16 , 0b0 , any ; # MCMODE1Q_DISABLE_READ_ALLOCATION_TO_CACHE_FOR_FASTPATH_OP 17 , 0b0 , any ; # MCMODE1Q_ENABLE_CRC_ECC_BYPASS_NODAL_SCOPE_ONLY 18:26, 0b000000000 , any ; # MCMODE1Q_DISABLE_SPEC_OPS_BY_SOURCE_AND_OR_SCOPE 27:30, 0b0000 , any ; # MCMODE1Q_DISABLE_PREFETCH 31 , 0b0 , any ; # MCMODE1Q_DISABLE_ALL_SPEC_OPS # 32:48, 0b00000000000000000 , any ; # MCMODE1Q_DISABLE_SPEC_OPS 32:40, 0b000000000 , any ; # MCMODE1Q_DISABLE_SPEC_OPS # 41 , 0b1 , (SYS.ATTR_PM_SLEEP_ENABLE == 1) ; #CAPI Deadlock workaround 41 , 0b1 , any ; #CAPI Deadlock workaround 42 , 0b0 , any ; # MCMODE1Q_DISABLE_SPEC_OPS # 43 , 0b1 , (SYS.ATTR_PM_SLEEP_ENABLE == 1) ; #CAPI Deadlock workaround 43 , 0b1 , any ; #CAPI Deadlock workaround 44 , 0b0 , any ; # MCMODE1Q_DISABLE_SPEC_OPS 45 , 0b0 , any ; # MCMODE1Q_DISABLE_SPEC_OPS # 46 , 0b1 , (SYS.ATTR_PM_SLEEP_ENABLE == 1) ; #CAPI Deadlock workaround 46 , 0b1 , any ; #CAPI Deadlock workaround 47:48, 0b00 , any ; # MCMODE1Q_DISABLE_SPEC_OPS 49 , 0b0 , any ; # MCMODE1Q_DISABLE_OP_SOURCE_AND_SCOPE 50:51, 0b00 , any ; # MCMODE1Q_DISABLE_CACHE_INHIBITED 52 , 0b0 , any ; # MCMODE1Q_DISABLE_ALL_MCS_COMMAND_BYPASS 53:59, 0b0000000 , any ; # MCMODE1Q_DISABLE_MCS_COMMAND_BYPASS 60 , 0b0 , any ; # MCMODE1Q_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ 61 , 0b0 , any ; # MCMODE1Q_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ 62 , 0b1 , (ecc_bypass_disable) ; # MCMODE1Q_DISABLE_FASTPATH_MCS_COMMAND_BYPASS 63 , 0b1 , any ; # MCMODE1Q_DISABLE_FASTPATH_CRC_ECC_BYPASS } #--****************************************************************************** #-- MCS Mode2 Register #--****************************************************************************** scom 0x0000000002011809 { bits , scom_data ; 0 , 0b0 ; # MCMODE2Q_FORCE_SFSTAT_GLOBAL 1:13 , 0b0000000000000 ; # MCMODE2Q_DISABLE_WRITE_MDI_TO_ZERO 14 , 0b0 ; # MCMODE2Q_DISABLE_SFU_OPERATIONS 15 , 0b0 ; # MCMODE2Q_DISABLE_FASTPATH_QOS # 16 , 0b0 ; # MCMODE2Q_ENABLE_2K_SPEC_READ_DISABLE_COUNTERS 16 , 0b1 ; # MCMODE2Q_ENABLE_2K_SPEC_READ_DISABLE_COUNTERS 17 , 0b0 ; # MCMODE2Q_ENABLE_ZERO_SPEC_HASH_ADDR_48_TO_50 18 , 0b0 ; # MCMODE2Q_DISABLE_SPEC_DISABLE_HINT_BIT # 19 , 0b0 ; # MCMODE2Q_ENABLE_RESET_2K_COUNT_IF_HINT_BIT_SET 19 , 0b1 ; # MCMODE2Q_ENABLE_RESET_2K_COUNT_IF_HINT_BIT_SET 20:23, 0x0 ; # MCMODE2Q_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT 24:27, 0x0 ; # MCMODE2Q_D2K_SPEC_FILTER_COUNTER_LFSR_DEC__SELECT 28 , 0b0 ; # MCMODE2Q_SPEC_READ_FILTER_NO_HASH_MODE 29 , 0b1 ; # MCMODE2Q_ENABLE_CHANNEL_HANG 30:35, 0b111111 ; # MCMODE2Q_READ_SPECULATION_DISABLE_THRESHOLD 36:38, 0b010 ; # MCMODE2Q_CHANNEL_ARB_WRITE_HP_THRESHOLD 39 , 0b0 ; # MCMODE2Q_DISABLE_BAD_CRESP_TO_CENTAUR 40 , 0b1 ; # MCMODE2Q_ENABLE_CRC_BYPASS_ALWAYS 41:43, 0b011 ; # MCMODE2Q_CHANNEL_HANG_VALUE 44 , 0b1 ; # MCMODE2Q_ENABLE_RD_HANG 45 , 0b1 ; # MCMODE2Q_ENABLE_WR_HANG 46 , 0b1 ; # MCMODE2Q_ENABLE_MIRROR_RD_HANG 47 , 0b1 ; # MCMODE2Q_ENABLE_MIRROR_WR_HANG 48 , 0b1 ; # MCMODE2Q_ENABLE_AO_HANG 49 , 0b1 ; # MCMODE2Q_ENABLE_INBAND_HANG 50:52, 0b100 ; # MCMODE2Q_NONMIRROR_HANG_VALUE 53:55, 0b111 ; # MCMODE2Q_MIRROR_HANG_VALUE 56 , 0b1 ; # MCMODE2Q_ENABLE_EMER_THROTTLE 57 , 0b0 ; # MCMODE2Q_DRIVE_SHARED_PRESP_WITH_LOST_CLAIM 58 , 0b0 ; # MCMODE2Q_DISABLE_SHARED_PRESP_ABORT 59 , 0b0 ; # MCMODE2Q_DISABLE_RTY_LOST_CLAIM_PRESP 60 , 0b0 ; # MCMODE2Q_DRIVE_BC4_WRITE_COMMAND 61 , 0b1 ; # MCMODE2Q_ENABLE_CENTAUR_CHECKSTOP_COMMAND 62 , 0b1 ; # MCMODE2Q_ENABLE_CENTAUR_TRACESTOP_COMMAND 63 , 0b0 ; # MCMODE2Q_ENABLE_EVENT_BUS_B } #--****************************************************************************** #-- MCS Mode3 Register #--****************************************************************************** scom 0x000000000201180A { bits , scom_data , expr ; 24 , 0b1 , any ; # MCMODE3Q_ENABLE_LOCAL_TIMEOUT_TIMEBASE 25:30, 0b000001 , any ; # MCMODE3Q_LOCAL_TIMEOUT_TIMEBASE_THRESHOLD 48:52, 0b11111 , (ATTR_CHIP_EC_FEATURE_MCS_MURDD1_FIR_CONTROL == 0) ; # MCMODE3Q_READ_RAMP_PERF_TRESHOLD } #--****************************************************************************** #-- MCS Mode4 Register #--****************************************************************************** scom 0x000000000201181A { bits , scom_data ; 1:3, 0b111 ; # DISABLE INTERFACE AND ARBITER BLOCKING DURING INTERNAL MCS CHECKSTOP 17:18, 0b00 ; # MCMODE4Q_SELECT_RPTHANG_DECODE 19 , 0b1 ; # MCMODE4Q_LOCAL_TIMEBASE_SELECT 21 , 0b1 ; # MCMODE4Q_DISABLE_POWERBUS_READ_AND_WRITE_RAMPS_DURING_CHECKSTOP } #--****************************************************************************** #-- MC Busy Control Register #--****************************************************************************** scom 0x0000000002011818 { bits , scom_data ; 0 , 0b0 ; # MCBUSYQ_ENABLE_BUSY_COUNTERS 1:3 , 0b100 ; # MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT (256 Cycles) 4:13 , 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD0 14:23, 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD1 24:33, 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD2 34:43, 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD3 } #--****************************************************************************** #-- MCS Hardware Force Mirror Read (MCHWFM) #--****************************************************************************** scom 0x000000000201181C { bits , scom_data , expr ; 0 , 0b1 , (ATTR_CHIP_EC_FEATURE_MCS_MURDD1_FIR_CONTROL == 0) ; # ENABLE FORCED CHANNEL INACTIVE FOR MIRROR UE/SUE FUNCTION 4 , 0b0 , (ATTR_CHIP_EC_FEATURE_MCS_MURDD1_FIR_CONTROL == 0) ; # DON'T SHUT DOWN MIRROR FOR INTERNAL CENTAUR UES, OR PASSED IN SUES 5 , 0b1 , (ATTR_CHIP_EC_FEATURE_MCS_MURDD1_FIR_CONTROL == 0) ; # SHUT DOWN MIRROR FOR MIRRORED MEMORY UE ONLY } #--****************************************************************************** #-- MCI Configuration Register #--****************************************************************************** scom 0x000000000201184A { bits , scom_data ; 0 , 0b0 ; # MCICFGQ_FORCE_CHANNEL_FAIL 1 , 0b0 ; # MCICFGQ_REPLAY_CRC_DISABLE 2 , 0b0 ; # MCICFGQ_REPLAY_NOACK_DISABLE 3 , 0b0 ; # MCICFGQ_REPLAY_OUTOFORDER_DISABLE 4 , 0b0 ; # MCICFGQ_FORCE_LFSR_REPLAY 5 , 0b0 ; # MCICFGQ_CRC_CHECK_DISABLE 6 , 0b0 ; # MCICFGQ_ECC_CHECK_DISABLE 7 , 0b0 ; # MCICFGQ_START_FRAME_LOCK 8 , 0b0 ; # MCICFGQ_START_FRTL 9 , 0b0 ; # MCICFGQ_AUTO_FRTL_DISABLE 10:16, 0b0000000 ; # MCICFGQ_MANUAL_FRTL_VALUE 17 , 0x0 ; # MCICFGQ_MANUAL_FRTL_DONE 18 , 0b0 ; # MCICFGQ_ECC_CORRECT_DISABLE 19 , 0b0 ; # MCICFGQ_SPARE1 20 , 0b0 ; # MCICFGQ_LANE_VOTING_BYPASS 21:25, 0b00000 ; # MCICFGQ_BAD_LANE_VALUE 26 , 0b0 ; # MCICFGQ_BAD_LANE_VOTING_DISABLE 27:32, 0b001001 ; # MCICFGQ_NO_FORWARD_PROGRESS_TIMEOUT_VALUE (0x09 = 9 => 1ms) 33:34, 0b00 ; # MCICFGQ_PERFORMANCE_DEGRADATION_PERCENT_SELECT 35:36, 0b00 ; # MCICFGQ_CHANNEL_INITIALIZATION_STATE_MACHINE_TIMEOUT_VALUE 37 , 0b0 ; # MCICFGQ_RESET_KEEPER 38:41, 0b0001 ; # MCICFGQ_REPLAY_DELAY_VALUE (set to 1 for pSeries, which is default value) 42:43, 0b00 ; # MCICFGQ_RESERVED }