#-- $Id: p8.fbc.scom.initfile,v 1.13 2013/08/28 22:03:30 jmcgill Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 #-- All Rights Reserved -- Property of IBM #-- *** IBM Confidential *** #-- #-- TITLE : p8.fbc.scom.initfile #-- DESCRIPTION : Perform fabric configuration #-- #-- OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com #-- #-------------------------------------------------------------------------------- SyntaxVersion = 1 #-------------------------------------------------------------------------------- #-- Includes #-------------------------------------------------------------------------------- include p8.fbc.define #-------------------------------------------------------------------------------- #-- Defines #-------------------------------------------------------------------------------- define def_x_is_4b = (SYS.ATTR_PROC_X_BUS_WIDTH == ENUM_ATTR_PROC_X_BUS_WIDTH_W4BYTE); define xbus_enabled = (ATTR_PROC_X_ENABLE == ENUM_ATTR_PROC_X_ENABLE_ENABLE); define abus_enabled = (ATTR_PROC_A_ENABLE == ENUM_ATTR_PROC_A_ENABLE_ENABLE); define pcie_enabled = (ATTR_PROC_PCIE_ENABLE == ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE); define mcd_hang_poll_bug = (ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG != 0); #-------------------------------------------------------------------------------- #-- SCOM initializations #-------------------------------------------------------------------------------- #-- PB Mode Register (PB_MODE / 0x02010C[048]A) scom 0x02010C(0,4,8)A { bits, scom_data; chip_is_system, 0b1; #-- single chip avp_mode, 0b0; #-- AVP mode (TODO: link to attribute) sw_ab_wait, 0x0; #-- no delay sp_hw_mark, 0x20; #-- 32 gp_hw_mark, 0x20; #-- 32 lcl_hw_mark, 0x20; #-- 32 e2e_hw_mark, 0x3B; #-- 59 fp_hw_mark, 0x20; #-- 32 switch_option_ab, 0b0; #-- no switch CD on switch AB cpu_ratio_override, 0b000; #-- rcmd queue depth = 16 } #-- PB Trace Array Select Configuration Register (PB_EVENT_TRACE / 0x02010C4F) scom 0x02010C4F { bits, scom_data; sn0_select, 0b10; #-- rcmd 0 sn1_select, 0b10; #-- rcmd 1 cr0_select, 0b10; #-- cresp 0 / presp 0 cr1_select, 0b10; #-- cresp 1 / presp 1 rt0_select, 0b10; #-- rtag NW rt1_select, 0b001; #-- MCD dat_select, 0b000000; #-- none } #-- PB Node Master Power Management Counter Register (PB_NMPM_COUNTER / 0x2010C50) scom 0x02010C50 { bits, scom_data; apm_en, 0b0; #-- set shared counters to PMU mode pmucnt_en, 0b1; #-- set shared counters to PMU mode pmucnt_sel, 0b11; #-- PMU counter select = rcmd 0 OR rcmd 1 } #-- FBC EXTFIR #-- NOTE: init to all bits masked, proc_fab_iovalid will unmask bits for active links #-- PB EXTFIR Mask Register (EXTFIR_MASK_REG / 0x02010C71) scom 0x02010C71 { bits, scom_data; 0:63, 0xFF00000000000000; } #-- PB EXTFIR Action0 Register (EXTFIR_ACTION0_REG / 0x02010C74) scom 0x02010C74 { bits, scom_data; 0:63, 0x0000000000000000; } #-- PB EXTFIR Action1 Register (EXTFIR_ACTION1_REG / 0x02010C75) scom 0x02010C75 { bits, scom_data; 0:63, 0x0000000000000000; } #-- MCD FIR Mask Register (MCDCTL.FIR_MASK_REG / 0x02013403) #-- NOTE: init to all bits masked, proc_setup_bars will unmask if MCD is enabled on this chip scom 0x02013403 { bits, scom_data; 0:63, 0xFFC0000000000000; } #-- MCD FIR Action0 Register (MCDCTL.FIR_ACTION0_REG / 0x02013406) scom 0x02013406 { bits, scom_data; 0:63, 0x0000000000000000; } #-- MCD FIR Action1 Register (MCDCTL.FIR_ACTION1_REG / 0x02013407) scom 0x02013407 { bits, scom_data, expr; 0:3, 0xC, any; 4, 0b1, (!mcd_hang_poll_bug); 4, 0b0, (mcd_hang_poll_bug); 5:7, 0b000, any; 8:63, 0x00000000000000, any; } #-- MCD Even/Odd Recovery Control Registers (MCD_REC_[EVEN_ODD] / 0x0201341[01]) #-- NOTE: set base configuration, proc_setup_bars will enable recovery for #-- valid configuration registers based on memory configuration of this chip scom 0x0201341(0,1) { bits, scom_data; mcd_recov_continuous, 0b1; #-- enable continuous recovery mcd_recov_pace_delay, 0x040; #-- 1024 cycle wait between probes mcd_recov_recov_all, 0b0; #-- disable recover all function mcd_recov_granule_count, 0x3FFFF; #-- set granule count } #-- MCD Recovery Pre Epsilon Configuration Register (MCD_PRE / 0x0201340B) scom 0x0201340B { bits, scom_data; mcd_retry_count, 0b1111; #-- retry count of 15 } #-- MCD Debug Configuration Register (MCD_DBG / 0x02013416) scom 0x02013416 { bits, scom_data; mcd_debug_enable, 0b1; #-- enable debug clocks mcd_debug_select, 0b1000; #-- default debug bus select } #-- PB X Link Mode Register (PB_X_MODE / 0x04010C0A) scom 0x04010C0A { bits, scom_data, expr; x_avp_mode, 0b0, (xbus_enabled); #-- X AVP mode (TODO: link to attribute) x_4b_mode, 0b1, (xbus_enabled) && (def_x_is_4b); #-- X bus 4/8B switch x_tod_wait_limit, 0b0100, (xbus_enabled); #-- X bus TOD wait limit } #-- PB A Link Mode Register (PB_IOA_MODE / 0x0801080A) scom 0x0801080A { bits, scom_data, expr; a_avp_mode, 0b0, (abus_enabled); #-- A AVP mode (TODO: link to attribute) } #-- PB A Link Framer Configuration Register (PB_IOA_FMR_CFG / 0x08010813) scom 0x08010813 { bits, scom_data, expr; a_tod_wait_limit, 0b0001, (abus_enabled); #-- A bus TOD wait limit a_prsp_wait_limit, 0b1000, (abus_enabled); #-- A bus presp wait limit a_cc_wait_limit, 0b1100, (abus_enabled); #-- A bus cresp credit wait limit a0_dc_wait_limit, 0b1100, (abus_enabled); #-- A0 bus data credit wait limit a1_dc_wait_limit, 0b1100, (abus_enabled); #-- A1 bus data credit wait limit a2_dc_wait_limit, 0b1100, (abus_enabled); #-- A2 bus data credit wait limit a_ow_pack, 0b0, (abus_enabled); #-- OW pack disabled a_ow_pack_priority, 0b0, (abus_enabled); #-- low priority } #-- PB F Link Mode Register (PB_IOF_MODE / 0x0901080A) scom 0x0901080A { bits, scom_data, expr; f_avp_mode, 0b0, (pcie_enabled); #-- F AVP mode (TODO: link to attribute) } #-- PB F Link Framer Configuration Register (PB_IOF_FMR_CFG / 0x09010813) scom 0x09010813 { bits, scom_data, expr; f_ow_pack, 0b0, (pcie_enabled); #-- OW pack disabled f_ow_pack_priority, 0b0, (pcie_enabled); #-- low priority }