#-- $Id: p8.dmi.scom.initfile,v 1.26 2014/02/04 19:06:24 jgrell Exp $ #################################################################### ## ## Auto-genrated by fig2scominit.pl ## Based on SETUP_ID_MODE DMI_BUS_TR_HW ## from ../../logic/mesa_sim/fusion/run/IODPV_MC_WRAP.IODPV_MC_WRAP.figdb ## ## Created on Tue Nov 26 11:33:54 CST 2013, by jgrell #################################################################### ## -- CHANGE HISTORY: ## -------------------------------------------------------------------------------- ## -- VersionID: |Author: | Date: | Comment: ## -- -----------|---------|--------|------------------------------------------------- ## -- jgr14020400| jgr |02-04-14| Bus ID change for FIRs ## -- jgr13112600| jgr |11-26-13| CYC rx_ds_timeout_sel setting changed to 111 ## -- jgr13102800| jgr |10-28-13| rx_ds_timeout_sel change (110 -> 111) ## -- jgr13082100| jgr |08-21-13| Added tx_zcal inits so they can be removed from scan ## -- jfg13072400| jfg |07-24-13| HW253558: change pgooddly to MAX from lab feedback ## -- mbs13071200| mbs |07-12-13| Updates for HW239870 and HW258990 ## -- | | | Disable recal adjustment for allv1 (DFE bug) ## -- jgr13041800| jgr |04-18-13| Added rx_max_ber_check_count setting to 0x03 ## -- smr13032500| SMR |03-25-13| Changed rx_dyn_recal_overall_timeout_sel init to 0b100 & rx_sls_timeout_sel init to 0b110 ## -- jgr13031300| jgr |03-13-13| Added missing entries from rel 0128 ## -- mbs13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) ## -- mbs12121100| mbs |12-11-12| Added rx_prot_speed_slct and rx_c4_sel ## -- smr12112700| SMR |11-27-12| Added rx_dyn_recal_overall_timeout_sel init to 0b001 ## -- jfg12112101| jfg |11-21-12| Added Zcal inits ## -- jfg12112100| jfg |11-21-12| Added CU pll modes ## -- 12111300| berger |11-13-12| Updated with HW eyeopt and recal settings ## -- 12062500| SMR |06-25-12| HW210654: Added rx_sls_timeout_sel default of 1 ## -- 11012500| mbs |01-25-12| Swizzle and typo fixes for HW191494, HW191518, HW188304 ## -- 11011912| RJR |01-17-12| Added RX_CTL2_REGS FILE REFERENCES ## -- 12011800| berger |01-19-12| Added SETUP_ID_MODE dials ## -- 11121500| thomsen |12-15-11| Added Per-Pack GCR SCOM Addresses for Regchk (HW188381,HW182867) ## -- | | | Removed 0x0000040000000000 from TX address definitions since it is in the lower level figtree files (HW187781,HW187893) ## -- 11102100| SMR |10-21-11| HW181193: Added rx_dyn_rpr_enc_bad_data_lane_width register ## -- 11102500| jfg |10-25-11| HW181485,HW181791: swizzle updates for scramble ## -- 11092900| SMR |09-29-11| HW171978: Added dyn rpr error tallying defaults ## -- 11050300| SMR |05-02-11| Added tx_max_bad_lanes ## -- 11032200| jg |02-17-11| Added RX PLLREG register offsets ## -- 11022800| thomsen |02-28-11| Fixed RX/TX scramble tap pattern match problem between driver and receiver. Also fixed in iodnc_mb_top.fig. ## -- 11021700| thomsen |02-17-11| Fixed RX_BUS_WIDTH from 17 to 24 ## -- 11021600| thomsen |02-16-11| Added Per-Bus, Per-Lane and Per-Group GCR SCOM addresses so Regchk would pass ## -- 11020200| thomsen |02-02-11| Added RX & TX scramble/descramble tap ID settings ## -- 11012500| berger |01-25-11| added TX lane disable and rx_bus_width fields, added missing SETUP_ID fields ## -- 11010600| smc |01-06-11| changed prefix (generic vhdl only) to iodpv to match post generic ## -- 11010600| berger |01-06-11| added lane disable and max bad lane ## -- 10121600| thomsen |12-16-10| Added RX_FENCE ## -- 10121300| thomsen |12-13-10| Fixed END_LANE_ID values per HW133020 ## -- 10120800| thomsen |12-08-10| Added TX_BUS_WIDTH ## -- 10102601| thomsen |10-26-10| Renamed gdial enum names from MC_BUS to DMI_BUS ## -- 10102600| thomsen |10-26-10| Initial version ## -------------------------------------------------------------------------------- ## -- TODO: These need to be modified for Z ## -- TODO: Not sure how to handle gdials since Z has extra the extra group, ie. P won't acknowledge RX4.RXCTL.RX_CTL_REGS.RX_* dials exist. SyntaxVersion = 1 #################################################################### # Define File #################################################################### include edi.io.define define def_IS_HW = SYS.ATTR_IS_SIMULATION == 0; define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1; define def_bus_id3 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 7)); define def_bus_id2 = ((ATTR_CHIP_UNIT_POS == 2) || (ATTR_CHIP_UNIT_POS == 6)); define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 1) || (ATTR_CHIP_UNIT_POS == 5)); define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 0) || (ATTR_CHIP_UNIT_POS == 4)); #define def_bus_id3 = ((ATTR_CHIP_UNIT_POS == 0) || (ATTR_CHIP_UNIT_POS == 4)); #define def_bus_id2 = ((ATTR_CHIP_UNIT_POS == 1) || (ATTR_CHIP_UNIT_POS == 5)); #define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 7)); #define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 2) || (ATTR_CHIP_UNIT_POS == 6)); #BUSCTL.BUS_CTL_REGS.TX_IMPCAL_P_4X_PB scom 0x800F1C6002011A3F { bits, scom_data, expr; tx_zcal_p_4x, 0b00100, any; } #BUSCTL.BUS_CTL_REGS.TX_IMPCAL_SWO2_PB scom 0x800F2C6002011A3F { bits, scom_data, expr; tx_zcal_sm_max_val, 0b1000110, any; tx_zcal_sm_min_val, 0b0010101 , def_IS_HW; tx_zcal_sm_min_val, 0b0010110 , def_IS_VBU; } #RX3.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG scom 0x800AF06002011A3F { bits, scom_data, expr; rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id3; rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id0; rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id0; rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id1; rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id1; rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id2; rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id2; rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id3; rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id0; rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id0; rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id1; rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id1; rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id2; rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP scom 0x800B786002011A3F { bits, scom_data, expr; rx_amin_cfg, 0b111, def_IS_HW && def_bus_id3; rx_amin_cfg, 0b111, def_IS_HW && def_bus_id0; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id0; rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id3; rx_amin_cfg, 0b111, def_IS_HW && def_bus_id0; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id0; rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id3; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id0; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id1; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id3; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id0; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id1; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_h1_cfg, 0b01, def_IS_HW && def_bus_id3; rx_h1_cfg, 0b01, def_IS_HW && def_bus_id0; rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id3; rx_h1_cfg, 0b01, def_IS_HW && def_bus_id0; rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id3; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id0; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id1; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id2; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id3; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id0; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id1; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id2; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP scom 0x800B806002011A3F { bits, scom_data, expr; rx_ber_cfg, 0b100, def_IS_HW && def_bus_id3; rx_ber_cfg, 0b100, def_IS_HW && def_bus_id0; rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id0; rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id3; rx_ber_cfg, 0b100, def_IS_HW && def_bus_id0; rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id0; rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id3; rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id0; rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id0; rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id3; rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id0; rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id0; rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id3; rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id0; rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id3; rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id0; rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id3; rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id0; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id0; rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id3; rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id0; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id0; rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id3; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id0; rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id1; rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id2; rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id3; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id0; rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id1; rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id2; rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG scom 0x800A186002011A3F { bits, scom_data, expr; rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id3; rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id0; rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id1; rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_TIMEOUTS_PP scom 0x800B406002011A3F { bits, scom_data, expr; rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id3; rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG scom 0x8009D86002011A3F { bits, scom_data, expr; rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id3; rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id0; rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id1; rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id2; rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id3; rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id0; rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id1; rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id2; rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id3; rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id0; rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id1; rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG scom 0x800AE06002011A3F { bits, scom_data, expr; rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id3; rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id0; rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id1; rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id2; rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id3; rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id0; rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id1; rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_EO_CONVERGENCE_PG scom 0x800A806002011A3F { bits, scom_data, expr; rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id3; rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id0; rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id0; rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id1; rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id1; rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id2; rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id2; rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id3; rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id0; rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id0; rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id1; rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id1; rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id2; rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG scom 0x800A386002011A3F { bits, scom_data, expr; rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id3; rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id3; rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id3; rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id3; rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id3; rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id3; rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id3; rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id3; rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_final_l2u_adj, 0b1, def_bus_id3; rx_eo_enable_final_l2u_adj, 0b1, def_bus_id0; rx_eo_enable_final_l2u_adj, 0b1, def_bus_id1; rx_eo_enable_final_l2u_adj, 0b1, def_bus_id2; rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id3; rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id3; rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id3; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id3; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id3; rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id3; rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id3; rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id3; rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_FENCE_PG scom 0x8009A86002011A3F { bits, scom_data, expr; rx_fence, 0b1, def_bus_id3; rx_fence, 0b1, def_bus_id0; rx_fence, 0b1, def_bus_id1; rx_fence, 0b1, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_ID1_PG scom 0x8008506002011A3F { bits, scom_data, expr; rx_bus_id, 0b000011, def_bus_id3; rx_bus_id, 0b000000, def_bus_id0; rx_bus_id, 0b000001, def_bus_id1; rx_bus_id, 0b000010, def_bus_id2; rx_group_id, 0b000000, def_bus_id3; rx_group_id, 0b000000, def_bus_id0; rx_group_id, 0b000000, def_bus_id1; rx_group_id, 0b000000, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_ID2_PG scom 0x8008586002011A3F { bits, scom_data, expr; rx_last_group_id, 0b000000, def_bus_id3; rx_last_group_id, 0b000000, def_bus_id0; rx_last_group_id, 0b000000, def_bus_id1; rx_last_group_id, 0b000000, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_ID3_PG scom 0x8008606002011A3F { bits, scom_data, expr; rx_end_lane_id, 0b0010111, def_bus_id3; rx_end_lane_id, 0b0010111, def_bus_id0; rx_end_lane_id, 0b0010111, def_bus_id1; rx_end_lane_id, 0b0010111, def_bus_id2; rx_start_lane_id, 0b0000000, def_bus_id3; rx_start_lane_id, 0b0000000, def_bus_id0; rx_start_lane_id, 0b0000000, def_bus_id1; rx_start_lane_id, 0b0000000, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG scom 0x8009286002011A3F { bits, scom_data, expr; rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id3; rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0; rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1; rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG scom 0x8009306002011A3F { bits, scom_data, expr; rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id3; rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id0; rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id1; rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG scom 0x8009C06002011A3F { bits, scom_data, expr; rx_c4_sel, 0b00, def_IS_HW && def_bus_id3; rx_c4_sel, 0b00, def_IS_HW && def_bus_id0; rx_c4_sel, 0b11, def_IS_VBU && def_bus_id0; rx_c4_sel, 0b00, def_IS_HW && def_bus_id1; rx_c4_sel, 0b11, def_IS_VBU && def_bus_id1; rx_c4_sel, 0b00, def_IS_HW && def_bus_id2; rx_c4_sel, 0b11, def_IS_VBU && def_bus_id2; rx_c4_sel, 0b11, def_IS_VBU && def_bus_id3; rx_c4_sel, 0b00, def_IS_HW && def_bus_id0; rx_c4_sel, 0b11, def_IS_VBU && def_bus_id0; rx_c4_sel, 0b00, def_IS_HW && def_bus_id1; rx_c4_sel, 0b11, def_IS_VBU && def_bus_id1; rx_c4_sel, 0b00, def_IS_HW && def_bus_id2; rx_c4_sel, 0b11, def_IS_VBU && def_bus_id2; rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id3; rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id0; rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id0; rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id1; rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id1; rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id2; rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id2; rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id3; rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id0; rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id0; rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id1; rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id1; rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id2; rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_MODE_PG scom 0x8008186002011A3F { bits, scom_data, expr; rx_master_mode, 0b1, def_bus_id3; rx_master_mode, 0b1, def_bus_id0; rx_master_mode, 0b1, def_bus_id1; rx_master_mode, 0b1, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG scom 0x800AB86002011A3F { bits, scom_data, expr; rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id3; rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id3; rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id3; rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id3; rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id3; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id3; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id3; rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id0; rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id1; rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id2; rx_rc_enable_h1ap_tweak, 0b0, def_bus_id3; rx_rc_enable_h1ap_tweak, 0b0, def_bus_id0; rx_rc_enable_h1ap_tweak, 0b0, def_bus_id1; rx_rc_enable_h1ap_tweak, 0b0, def_bus_id2; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id3; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id3; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id3; rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id3; rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id3; rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id3; rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO1_PP scom 0x800B906002011A3F { bits, scom_data, expr; rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id3; rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id3; rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP scom 0x800B986002011A3F { bits, scom_data, expr; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id3; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id3; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id3; rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id3; rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP scom 0x800BA06002011A3F { bits, scom_data, expr; rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id3; rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id3; rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id3; rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id3; rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id3; rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id3; rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP scom 0x800B606002011A3F { bits, scom_data, expr; rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id3; rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id3; rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id3; rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id3; rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP scom 0x800B686002011A3F { bits, scom_data, expr; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id3; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id3; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id3; rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id3; rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP scom 0x800B706002011A3F { bits, scom_data, expr; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id3; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id3; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id3; rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id3; rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id3; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id3; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG scom 0x8009106002011A3F { bits, scom_data, expr; rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id3; rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id3; rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id3; rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id3; rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id3; rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id3; rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id3; rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id3; rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id3; rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id3; rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG scom 0x8008986002011A3F { bits, scom_data, expr; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id3; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id0; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id0; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id1; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id3; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id0; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id0; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id1; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2; rx_ds_timeout_sel, 0b111, def_bus_id3; rx_ds_timeout_sel, 0b111, def_bus_id0; rx_ds_timeout_sel, 0b111, def_bus_id1; rx_ds_timeout_sel, 0b111, def_bus_id2; rx_sls_timeout_sel, 0b110, def_bus_id3; rx_sls_timeout_sel, 0b110, def_bus_id0; rx_sls_timeout_sel, 0b110, def_bus_id1; rx_sls_timeout_sel, 0b110, def_bus_id2; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id3; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id0; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id1; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id2; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id3; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id0; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id1; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG scom 0x8009986002011A3F { bits, scom_data, expr; rx_rx_bus_width, 0b0011000, def_bus_id3; rx_rx_bus_width, 0b0011000, def_bus_id0; rx_rx_bus_width, 0b0011000, def_bus_id1; rx_rx_bus_width, 0b0011000, def_bus_id2; rx_tx_bus_width, 0b0010001, def_bus_id3; rx_tx_bus_width, 0b0010001, def_bus_id0; rx_tx_bus_width, 0b0010001, def_bus_id1; rx_tx_bus_width, 0b0010001, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG scom 0x8009586002011A3F { bits, scom_data, expr; rx_wtr_max_bad_lanes, 0b00010, def_bus_id3; rx_wtr_max_bad_lanes, 0b00010, def_bus_id0; rx_wtr_max_bad_lanes, 0b00010, def_bus_id1; rx_wtr_max_bad_lanes, 0b00010, def_bus_id2; } #RX3.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG scom 0x800A306002011A3F { bits, scom_data, expr; rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id3; rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id0; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id0; rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id3; rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id0; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id0; rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id3; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id0; rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id0; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id1; rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id1; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id2; rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id2; rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id3; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id0; rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id0; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id1; rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id1; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id2; rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id2; } #RX3.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06002011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b000, def_bus_id3; rx_prbs_tap_id, 0b000, def_bus_id0; rx_prbs_tap_id, 0b000, def_bus_id1; rx_prbs_tap_id, 0b000, def_bus_id2; } #RX3.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06102011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b001, def_bus_id3; rx_prbs_tap_id, 0b001, def_bus_id0; rx_prbs_tap_id, 0b001, def_bus_id1; rx_prbs_tap_id, 0b001, def_bus_id2; } #RX3.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06202011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b010, def_bus_id3; rx_prbs_tap_id, 0b010, def_bus_id0; rx_prbs_tap_id, 0b010, def_bus_id1; rx_prbs_tap_id, 0b010, def_bus_id2; } #RX3.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06302011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b011, def_bus_id3; rx_prbs_tap_id, 0b011, def_bus_id0; rx_prbs_tap_id, 0b011, def_bus_id1; rx_prbs_tap_id, 0b011, def_bus_id2; } #RX3.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06402011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b100, def_bus_id3; rx_prbs_tap_id, 0b100, def_bus_id0; rx_prbs_tap_id, 0b100, def_bus_id1; rx_prbs_tap_id, 0b100, def_bus_id2; } #RX3.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06502011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b101, def_bus_id3; rx_prbs_tap_id, 0b101, def_bus_id0; rx_prbs_tap_id, 0b101, def_bus_id1; rx_prbs_tap_id, 0b101, def_bus_id2; } #RX3.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06602011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b110, def_bus_id3; rx_prbs_tap_id, 0b110, def_bus_id0; rx_prbs_tap_id, 0b110, def_bus_id1; rx_prbs_tap_id, 0b110, def_bus_id2; } #RX3.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06702011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b111, def_bus_id3; rx_prbs_tap_id, 0b111, def_bus_id0; rx_prbs_tap_id, 0b111, def_bus_id1; rx_prbs_tap_id, 0b111, def_bus_id2; } #RX3.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B07402011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b011, def_bus_id3; rx_prbs_tap_id, 0b011, def_bus_id0; rx_prbs_tap_id, 0b011, def_bus_id1; rx_prbs_tap_id, 0b011, def_bus_id2; } #RX3.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B07502011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b010, def_bus_id3; rx_prbs_tap_id, 0b010, def_bus_id0; rx_prbs_tap_id, 0b010, def_bus_id1; rx_prbs_tap_id, 0b010, def_bus_id2; } #RX3.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B07602011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b001, def_bus_id3; rx_prbs_tap_id, 0b001, def_bus_id0; rx_prbs_tap_id, 0b001, def_bus_id1; rx_prbs_tap_id, 0b001, def_bus_id2; } #RX3.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B07702011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b000, def_bus_id3; rx_prbs_tap_id, 0b000, def_bus_id0; rx_prbs_tap_id, 0b000, def_bus_id1; rx_prbs_tap_id, 0b000, def_bus_id2; } #RX3.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B07002011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b111, def_bus_id3; rx_prbs_tap_id, 0b111, def_bus_id0; rx_prbs_tap_id, 0b111, def_bus_id1; rx_prbs_tap_id, 0b111, def_bus_id2; } #RX3.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B07102011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b110, def_bus_id3; rx_prbs_tap_id, 0b110, def_bus_id0; rx_prbs_tap_id, 0b110, def_bus_id1; rx_prbs_tap_id, 0b110, def_bus_id2; } #RX3.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B07202011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b101, def_bus_id3; rx_prbs_tap_id, 0b101, def_bus_id0; rx_prbs_tap_id, 0b101, def_bus_id1; rx_prbs_tap_id, 0b101, def_bus_id2; } #RX3.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B07302011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b100, def_bus_id3; rx_prbs_tap_id, 0b100, def_bus_id0; rx_prbs_tap_id, 0b100, def_bus_id1; rx_prbs_tap_id, 0b100, def_bus_id2; } #RX3.RXPACKS#4.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06E02011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b001, def_bus_id3; rx_prbs_tap_id, 0b001, def_bus_id0; rx_prbs_tap_id, 0b001, def_bus_id1; rx_prbs_tap_id, 0b001, def_bus_id2; } #RX3.RXPACKS#4.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06F02011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b000, def_bus_id3; rx_prbs_tap_id, 0b000, def_bus_id0; rx_prbs_tap_id, 0b000, def_bus_id1; rx_prbs_tap_id, 0b000, def_bus_id2; } #RX3.RXPACKS#4.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06C02011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b011, def_bus_id3; rx_prbs_tap_id, 0b011, def_bus_id0; rx_prbs_tap_id, 0b011, def_bus_id1; rx_prbs_tap_id, 0b011, def_bus_id2; } #RX3.RXPACKS#4.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06D02011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b010, def_bus_id3; rx_prbs_tap_id, 0b010, def_bus_id0; rx_prbs_tap_id, 0b010, def_bus_id1; rx_prbs_tap_id, 0b010, def_bus_id2; } #RX3.RXPACKS#5.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06A02011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b010, def_bus_id3; rx_prbs_tap_id, 0b010, def_bus_id0; rx_prbs_tap_id, 0b010, def_bus_id1; rx_prbs_tap_id, 0b010, def_bus_id2; } #RX3.RXPACKS#5.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06B02011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b011, def_bus_id3; rx_prbs_tap_id, 0b011, def_bus_id0; rx_prbs_tap_id, 0b011, def_bus_id1; rx_prbs_tap_id, 0b011, def_bus_id2; } #RX3.RXPACKS#5.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06802011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b000, def_bus_id3; rx_prbs_tap_id, 0b000, def_bus_id0; rx_prbs_tap_id, 0b000, def_bus_id1; rx_prbs_tap_id, 0b000, def_bus_id2; } #RX3.RXPACKS#5.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B06902011A3F { bits, scom_data, expr; rx_prbs_tap_id, 0b001, def_bus_id3; rx_prbs_tap_id, 0b001, def_bus_id0; rx_prbs_tap_id, 0b001, def_bus_id1; rx_prbs_tap_id, 0b001, def_bus_id2; } #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG scom 0x800CC46002011A3F { bits, scom_data, expr; tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id3; tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id0; tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id1; tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id2; } #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_DYN_RECAL_TIMEOUTS_PP scom 0x800EAC6002011A3F { bits, scom_data, expr; tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id3; tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; } #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID1_PG scom 0x800C946002011A3F { bits, scom_data, expr; tx_bus_id, 0b000011, def_bus_id3; tx_bus_id, 0b000000, def_bus_id0; tx_bus_id, 0b000001, def_bus_id1; tx_bus_id, 0b000010, def_bus_id2; tx_group_id, 0b100000, def_bus_id3; tx_group_id, 0b100000, def_bus_id0; tx_group_id, 0b100000, def_bus_id1; tx_group_id, 0b100000, def_bus_id2; } #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID2_PG scom 0x800C9C6002011A3F { bits, scom_data, expr; tx_last_group_id, 0b100000, def_bus_id3; tx_last_group_id, 0b100000, def_bus_id0; tx_last_group_id, 0b100000, def_bus_id1; tx_last_group_id, 0b100000, def_bus_id2; } #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID3_PG scom 0x800CA46002011A3F { bits, scom_data, expr; tx_end_lane_id, 0b0010000, def_bus_id3; tx_end_lane_id, 0b0010000, def_bus_id0; tx_end_lane_id, 0b0010000, def_bus_id1; tx_end_lane_id, 0b0010000, def_bus_id2; tx_start_lane_id, 0b0000000, def_bus_id3; tx_start_lane_id, 0b0000000, def_bus_id0; tx_start_lane_id, 0b0000000, def_bus_id1; tx_start_lane_id, 0b0000000, def_bus_id2; } #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG scom 0x800D1C6002011A3F { bits, scom_data, expr; tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id3; tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0; tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1; tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2; } #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG scom 0x800D246002011A3F { bits, scom_data, expr; tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id3; tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id0; tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id1; tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id2; } #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_MODE_PG scom 0x800C1C6002011A3F { bits, scom_data, expr; tx_max_bad_lanes, 0b00010, def_bus_id3; tx_max_bad_lanes, 0b00010, def_bus_id0; tx_max_bad_lanes, 0b00010, def_bus_id1; tx_max_bad_lanes, 0b00010, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346002011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b000, def_bus_id3; tx_prbs_tap_id, 0b000, def_bus_id0; tx_prbs_tap_id, 0b000, def_bus_id1; tx_prbs_tap_id, 0b000, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346102011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b001, def_bus_id3; tx_prbs_tap_id, 0b001, def_bus_id0; tx_prbs_tap_id, 0b001, def_bus_id1; tx_prbs_tap_id, 0b001, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346202011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b010, def_bus_id3; tx_prbs_tap_id, 0b010, def_bus_id0; tx_prbs_tap_id, 0b010, def_bus_id1; tx_prbs_tap_id, 0b010, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346302011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b011, def_bus_id3; tx_prbs_tap_id, 0b011, def_bus_id0; tx_prbs_tap_id, 0b011, def_bus_id1; tx_prbs_tap_id, 0b011, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346402011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b100, def_bus_id3; tx_prbs_tap_id, 0b100, def_bus_id0; tx_prbs_tap_id, 0b100, def_bus_id1; tx_prbs_tap_id, 0b100, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346502011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b101, def_bus_id3; tx_prbs_tap_id, 0b101, def_bus_id0; tx_prbs_tap_id, 0b101, def_bus_id1; tx_prbs_tap_id, 0b101, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346602011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b110, def_bus_id3; tx_prbs_tap_id, 0b110, def_bus_id0; tx_prbs_tap_id, 0b110, def_bus_id1; tx_prbs_tap_id, 0b110, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346702011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b111, def_bus_id3; tx_prbs_tap_id, 0b111, def_bus_id0; tx_prbs_tap_id, 0b111, def_bus_id1; tx_prbs_tap_id, 0b111, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004347002011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b000, def_bus_id3; tx_prbs_tap_id, 0b000, def_bus_id0; tx_prbs_tap_id, 0b000, def_bus_id1; tx_prbs_tap_id, 0b000, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346F02011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b001, def_bus_id3; tx_prbs_tap_id, 0b001, def_bus_id0; tx_prbs_tap_id, 0b001, def_bus_id1; tx_prbs_tap_id, 0b001, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346E02011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b010, def_bus_id3; tx_prbs_tap_id, 0b010, def_bus_id0; tx_prbs_tap_id, 0b010, def_bus_id1; tx_prbs_tap_id, 0b010, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346D02011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b011, def_bus_id3; tx_prbs_tap_id, 0b011, def_bus_id0; tx_prbs_tap_id, 0b011, def_bus_id1; tx_prbs_tap_id, 0b011, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346C02011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b100, def_bus_id3; tx_prbs_tap_id, 0b100, def_bus_id0; tx_prbs_tap_id, 0b100, def_bus_id1; tx_prbs_tap_id, 0b100, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346B02011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b101, def_bus_id3; tx_prbs_tap_id, 0b101, def_bus_id0; tx_prbs_tap_id, 0b101, def_bus_id1; tx_prbs_tap_id, 0b101, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346A02011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b110, def_bus_id3; tx_prbs_tap_id, 0b110, def_bus_id0; tx_prbs_tap_id, 0b110, def_bus_id1; tx_prbs_tap_id, 0b110, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346902011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b111, def_bus_id3; tx_prbs_tap_id, 0b111, def_bus_id0; tx_prbs_tap_id, 0b111, def_bus_id1; tx_prbs_tap_id, 0b111, def_bus_id2; } #TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004346802011A3F { bits, scom_data, expr; tx_prbs_tap_id, 0b000, def_bus_id3; tx_prbs_tap_id, 0b000, def_bus_id0; tx_prbs_tap_id, 0b000, def_bus_id1; tx_prbs_tap_id, 0b000, def_bus_id2; } ###################################### ## END OF FILE #######################################