#-- $Id: p8.dmi.custom.scom.initfile,v 1.17 2013/09/24 20:20:35 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- #-- 1.17|jgrell |09/24/13|Changed "1" expression to "any" #-- 1.15|jgrell |09/17/13|Added DD2 specific inits #-- 1.13|jgrell |09/12/13|Re-added "Override" settings #-- 1.9 |thomsen |04/30/13|Added TGT1. to ATTR_CHIP_EC* attribute instances to reference a chip target rather than a chiplet target #-- 1.8 |jgrell |04/18/13|Added EC level control of the Recal DFE, DDC, and CTLE enable bits. ('0' when EC < 20) #-- 1.7 |jgrell |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab. #-- 1.6 |thomsen |03/07/13|Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab. #-- 1.5 |thomsen |02/12/13|Added Lane Power Ups and Clock Invert #-- 1.4 |jmcgill |02/09/13|Use chiplet level targeting, reference attributes #-- 1.3 |thomsen |02/01/13|Fixed tx_msbswap for groups 1,2,3 #-- 1.2 |berger |02/01/13|Removed a handful of settings already in the base file, added sim attr for MSB swap and lane invert #-- 1.1 |thomsen |01/23/13|Created initial version #-- --------|--------|--------|-------------------------------------------------- #-------------------------------------------------------------------------------- # End of revision history #-------------------------------------------------------------------------------- #-- TARGETS: #-- SYS. Chiplet target #-- TGT1. Proc target #-- ATTR_CHIP_UNIT_POS is the MCS unit number (0-7 on Venice, 4-7 on Murano) and corresponds to the scom address translation done in #-- the p8.chipunit.scominfo file. It is used to be able to select a specific clock group number. #-- Chip UNIT_POS DMI_UNIT CLOCKGRP #-- ---- -------- -------- -------- #-- Venice: 0-3 DMI0 3-0 #-- 4-7 DMI1 3-0 #-- Murano: 4-7 DMI1 3-0 SyntaxVersion = 1 #--*********************************************************************************** #------------------------------------------------------------------------------------- #-- #-- Includes #-- Note: Must include the path to the .define file. #-- #------------------------------------------------------------------------------------- #--*********************************************************************************** include edi.io.define #--*********************************************************************************** #------------------------------------------------------------------------------------- #-- #-- Defines #-- #------------------------------------------------------------------------------------- #--*********************************************************************************** define def_IS_HW = (SYS.ATTR_IS_SIMULATION == 0); define def_IS_VBU = (SYS.ATTR_IS_SIMULATION == 1); define def_all_lanes=11111; #--*********************************************************************************** #------------------------------------------------------------------------------------- #-- Overrides #------------------------------------------------------------------------------------- #--*********************************************************************************** #--*********************************************************************************** #------------------------------------------------------------------------------------- # __ ____ __ __ # / / ____ _____ ___ / __ \____ _ _____ _____ / / / /___ # / / / __ `/ __ \/ _ \ / /_/ / __ \ | /| / / _ \/ ___/ / / / / __ \ # / /___/ /_/ / / / / __/ / ____/ /_/ / |/ |/ / __/ / / /_/ / /_/ / # /_____/\__,_/_/ /_/\___/ /_/ \____/|__/|__/\___/_/ \____/ .___/ # /_/ #------------------------------------------------------------------------------------- #--*********************************************************************************** # rx_lane_pdwn #scom 0x800.0b(rx_mode_pl)(tx_grp3)(def_all_lanes).0x(dmi0_gcr_addr){ # bits, scom_data; # rx_lane_pdwn, 0b0; #} # tx_lane_pdwn #scom 0x800.0b(tx_mode_pl)(tx_grp3)(def_all_lanes).0x(dmi0_gcr_addr){ # bits, scom_data; # tx_lane_pdwn, 0b0; #} #--*********************************************************************************** #------------------------------------------------------------------------------------- # _______ __ __ ___ _ ________ _____ ___ ____________ ______ # /_ __/ |/ / / / / | / | / / ____/ / _/ | / / | / / ____/ __ \/_ __/ # / / | / / / / /| | / |/ / __/ / // |/ /| | / / __/ / /_/ / / / # / / / | / /___/ ___ |/ /| / /___ _/ // /| / | |/ / /___/ _, _/ / / # /_/ /_/|_| /_____/_/ |_/_/ |_/_____/ /___/_/ |_/ |___/_____/_/ |_| /_/ # #------------------------------------------------------------------------------------- #--*********************************************************************************** # These only do a scom if the invert attribute is set (saves scom's). # The default scanflush value of tx_lane_invert for each lane is '0'. # Lane 0 # 0x8004040002011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_0).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x80000000) > 0); } # Lane 1 # 0x8004040102011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_1).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x40000000) > 0); } # Lane 2 # 0x8004040202011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_2).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x20000000) > 0); } # Lane 3 # 0x8004040302011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_3).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x10000000) > 0); } # Lane 4 # 0x8004040402011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_4).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x08000000) > 0); } # Lane 5 # 0x8004040502011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_5).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x04000000) > 0); } # Lane 6 # 0x8004040602011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_6).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x02000000) > 0); } # Lane 7 # 0x8004040702011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_7).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x01000000) > 0); } # Lane 8 # 0x8004040802011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_8).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00800000) > 0); } # Lane 9 # 0x8004040902011E3F { scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_9).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00400000) > 0); } # Lane 10 # 0x8004040A02011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_10).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00200000) > 0); } # Lane 11 # 0x8004040B02011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_11).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00100000) > 0); } # Lane 12 # 0x8004040C02011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_12).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00080000) > 0); } # Lane 13 # 0x8004040D02011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_13).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00040000) > 0); } # Lane 14 # 0x8004040E02011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_14).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00020000) > 0); } # Lane 15 # 0x8004040F02011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_15).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00010000) > 0); } # Lane 16 # 0x8004041002011E3F scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_16).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00008000) > 0); } #--*********************************************************************************** #------------------------------------------------------------------------------------- # _______ __ ________ __ __ ____ __ # /_ __/ |/ / / ____/ / / //_/ / _/___ _ _____ _____/ /_ # / / | / / / / / / ,< / // __ \ | / / _ \/ ___/ __/ # / / / | / /___/ /___/ /| | _/ // / / / |/ / __/ / / /_ # /_/ /_/|_| \____/_____/_/ |_| /___/_/ /_/|___/\___/_/ \__/ # figlet -fslant #------------------------------------------------------------------------------------- #--*********************************************************************************** # CLK Lane (assigned to bit 31 of TX Lane Invert Attribute) # 0x800???7008010C3F scom 0x800.0b(tx_clk_mode_pg)(tx_grp3)(lane_na).0x(dmi0_gcr_addr) { bits, scom_data, expr; tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000001) > 0; } #--*********************************************************************************** #------------------------------------------------------------------------------------- # __ ________ ____ _____ # / |/ / ___// __ ) / ___/ ______ _____ # / /|_/ /\__ \/ __ | \__ \ | /| / / __ `/ __ \ # / / / /___/ / /_/ / ___/ / |/ |/ / /_/ / /_/ / # /_/ /_//____/_____/ /____/|__/|__/\__,_/ .___/ # /_/ # #------------------------------------------------------------------------------------- #--*********************************************************************************** # 0x800C1C0002011E3F scom 0x800.0b(tx_mode_pg)(tx_grp3)(lane_na).0x(dmi0_gcr_addr) { bits, scom_data; tx_msbswap, (ATTR_EI_BUS_TX_MSBSWAP & 0x01); } #--*********************************************************************************** #------------------------------------------------------------------------------------- # Recal (and part of DMI DFE Override) #------------------------------------------------------------------------------------- #--*********************************************************************************** # HW235842 and HW244323 scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { bits, scom_data, expr; rx_rc_enable_dfe_h1_cal, 0b0, any; #temp for DD2 testing. Previously --> TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0 || ATTR_DMI_DFE_OVERRIDE==1; rx_rc_enable_ddc, 0b0, any; #temp for DD2 testing. Previously --> TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0; rx_rc_enable_ctle_cal, 0b0, any; #temp for DD2 testing. Previously --> TGT1.ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0; rx_rc_enable_h1ap_tweak, 0b0, ATTR_DMI_DFE_OVERRIDE==1; } #--*********************************************************************************** #------------------------------------------------------------------------------------- # DMI DFE Override (HW244323) #------------------------------------------------------------------------------------- #--*********************************************************************************** #scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { #bits, scom_data, expr; #rx_rc_enable_dfe_h1_cal, 0b0, ATTR_DMI_DFE_OVERRIDE==1; #rx_rc_enable_h1ap_tweak, 0b0, ATTR_DMI_DFE_OVERRIDE==1; #} scom 0x800.0b(rx_eo_step_cntl_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { bits, scom_data, expr; rx_eo_enable_dfe_h1_cal, 0b0, ATTR_DMI_DFE_OVERRIDE==1; rx_eo_enable_h1ap_tweak, 0b0, ATTR_DMI_DFE_OVERRIDE==1; } scom 0x800.0b(rx_amax_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { bits, scom_data, expr; rx_amax_high, 0b01101110, ATTR_DMI_DFE_OVERRIDE==1; rx_amax_low, 0b01010000, ATTR_DMI_DFE_OVERRIDE==1; } scom 0x800.0b(rx_amp_val_pl)(rx_grp3)(def_all_lanes).0x(dmi0_gcr_addr) { bits, scom_data, expr; rx_amp_gain, 0b1001, ATTR_DMI_DFE_OVERRIDE==1; } #--*********************************************************************************** #------------------------------------------------------------------------------------- #-- DD2 Murano #------------------------------------------------------------------------------------- #--*********************************************************************************** scom 0x800.0b(rx_timeout_sel_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { bits, scom_data, expr; rx_sls_timeout_sel_dd2, 0b1010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_ds_timeout_sel_dd2, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; } ############################################################################################ # END OF FILE ############################################################################################