#-- $Id: p8.abus.scom.initfile,v 1.18 2013/12/04 17:25:20 jgrell Exp $ #################################################################### ## ## Auto-genrated by fig2scominit.pl ## Based on SETUP_ID_MODE A_BUS_TR_HW ## from ../../logic/mesa_sim/fusion/run/IODUV_ABUS_WRAP.IODUV_ABUS_WRAP.figdb ## ## Created on Tue Nov 26 11:34:06 CST 2013, by jgrell #################################################################### ## -- CHANGE HISTORY: ## -------------------------------------------------------------------------------- ## -- VersionID: |Author: | Date: | Comment: ## -- -----------|---------|--------|------------------------------------------------- ## -- jgr13112600| jgr |11-26-13| CYC rx_ds_timeout_sel setting changed to 111 ## -- jgr13102800| jgr |10-28-13| rx_ds_timeout_sel change (110 -> 111) ## -- jgr13092400| jgr |09-24-13| Fixed tx_zcal inits scom address ## -- jgr13082100| jgr |08-21-13| Added tx_zcal inits so they can be removed from scan ## -- jfg13072400| jfg |07-24-13| HW253558: change pgooddly to MAX from lab feedback ## -- mbs13071200| mbs |07-12-13| Updates for HW239870 and HW258990 ## -- jgr13062500| jgr |06-25-13| Added DFE override settings (HW244323) ## -- jgr13041800| jgr |04-18-13| Added missing entries from rel 0128 ## -- smr13032500| SMR |03-25-13| Changed rx_dyn_recal_overall_timeout_sel init to 0b100 & rx_sls_timeout_sel init to 0b110 ## -- mbs13021100| mbs |02-11-13| Changed A bus id's to 1,2,3 from 0,1,2 (HW239245) ## -- mbs13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) ## -- mbs12121100| mbs |12-11-12| Added rx_prot_speed_slct and rx_c4_sel ## -- smr12112700| SMR |11-27-12| Added rx_dyn_recal_overall_timeout_sel init to 0b001 ## -- jfg12112101| jfg |11-21-12| Added Zcal inits ## -- jfg12112100| jfg |11-21-12| Added CU pll modes ## -- 12111300| berger |11-13-12| Updated with HW eyeopt and recal settings ## -- 12062500| SMR |06-25-12| HW210654: Added rx_sls_timeout_sel default of 1 ## -- jfg12041600 |jfg |- HW193450,HW197325,HW196562,HW197324 clkdist Layout updates ## -- 11012500| mbs |01-25-12| Swizzle and typo fixes for HW191494, HW191518, HW188304 ## -- 12011900| RJR |01-18-12| Added RX_CTL2_REGS FILE REFERENCES Issue HW164277 ## -- 12011800| berger |01-19-12| Added SETUP_ID_MODE dials ## -- 11112900| mbs |11-29-11| Fixed RX scramble mirror taps (HW186689) ## -- 11121600| mbs |12-16-11| Initial version (copied from version 11112900 of iodsh_abus_wrap.fig) ## -------------------------------------------------------------------------------- SyntaxVersion = 1 #################################################################### # Define File #################################################################### include edi.io.define define def_IS_HW = SYS.ATTR_IS_SIMULATION == 0; define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1; define def_bus_id0 = (ATTR_CHIP_UNIT_POS == 0); define def_bus_id1 = (ATTR_CHIP_UNIT_POS == 1); define def_bus_id2 = (ATTR_CHIP_UNIT_POS == 2); define prim_id = (TGT1.ATTR_FABRIC_NODE_ID*100) + TGT1.ATTR_POS; define conn_id = (TGT3.ATTR_FABRIC_NODE_ID*100) + TGT3.ATTR_POS; define def_is_master = (prim_id < conn_id); define def_is_slave = (prim_id > conn_id); #BUSCTL.BUS_CTL_REGS.TX_IMPCAL_P_4X_PB scom 0x800F1C0008010C3F { bits, scom_data, expr; tx_zcal_p_4x, 0b00100, any; } #BUSCTL.BUS_CTL_REGS.TX_IMPCAL_SWO2_PB scom 0x800F2C0008010C3F { bits, scom_data, expr; tx_zcal_sm_max_val, 0b1000110, any; tx_zcal_sm_min_val, 0b0010101 , def_IS_HW; tx_zcal_sm_min_val, 0b0010110 , def_IS_VBU; } #RX0.RXCTL.RX_CTL_REGS.RX_AMAX_PG scom 0x800A680008010C3F { bits, scom_data, expr; rx_amax_high, 0b01101110, def_IS_HW && def_bus_id0; rx_amax_high, 0b01101110, def_IS_HW && def_bus_id1; rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id1; rx_amax_high, 0b01101110, def_IS_HW && def_bus_id2; rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id2; rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id0; rx_amax_high, 0b01101110, def_IS_HW && def_bus_id1; rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id1; rx_amax_high, 0b01101110, def_IS_HW && def_bus_id2; rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id2; rx_amax_low, 0b01010000, def_IS_HW && def_bus_id0; rx_amax_low, 0b01010000, def_IS_HW && def_bus_id1; rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id1; rx_amax_low, 0b01010000, def_IS_HW && def_bus_id2; rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id2; rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id0; rx_amax_low, 0b01010000, def_IS_HW && def_bus_id1; rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id1; rx_amax_low, 0b01010000, def_IS_HW && def_bus_id2; rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG scom 0x800AF00008010C3F { bits, scom_data, expr; rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id0; rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id1; rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id1; rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id2; rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id2; rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id0; rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id1; rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id1; rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id2; rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP scom 0x800B780008010C3F { bits, scom_data, expr; rx_amin_cfg, 0b111, def_IS_HW && def_bus_id0; rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id0; rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id0; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id1; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id1; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_h1_cfg, 0b01, def_IS_HW && def_bus_id0; rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id0; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id1; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id2; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id1; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id2; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP scom 0x800B800008010C3F { bits, scom_data, expr; rx_ber_cfg, 0b100, def_IS_HW && def_bus_id0; rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id0; rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id0; rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id0; rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id0; rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id0; rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id0; rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id0; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id1; rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id2; rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id0; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id1; rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id2; rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG scom 0x800A180008010C3F { bits, scom_data, expr; rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id0; rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id1; rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_TIMEOUTS_PP scom 0x800B400008010C3F { bits, scom_data, expr; rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG scom 0x8009D80008010C3F { bits, scom_data, expr; rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id0; rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id1; rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id2; rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id0; rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id1; rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id2; rx_dyn_rpr_err_cntr1_duration, 0b1001, def_bus_id0; rx_dyn_rpr_err_cntr1_duration, 0b1001, def_bus_id1; rx_dyn_rpr_err_cntr1_duration, 0b1001, def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG scom 0x800AE00008010C3F { bits, scom_data, expr; rx_dyn_rpr_bad_bus_max, 0b0011111, def_bus_id0; rx_dyn_rpr_bad_bus_max, 0b0011111, def_bus_id1; rx_dyn_rpr_bad_bus_max, 0b0011111, def_bus_id2; rx_dyn_rpr_err_cntr2_duration, 0b0110, def_bus_id0; rx_dyn_rpr_err_cntr2_duration, 0b0110, def_bus_id1; rx_dyn_rpr_err_cntr2_duration, 0b0110, def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_EO_CONVERGENCE_PG scom 0x800A800008010C3F { bits, scom_data, expr; rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id0; rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id1; rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id1; rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id2; rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id2; rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id0; rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id1; rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id1; rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id2; rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG scom 0x800A380008010C3F { bits, scom_data, expr; rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_dfe_h1_cal, 0b0, def_bus_id0; rx_eo_enable_dfe_h1_cal, 0b0, def_bus_id1; rx_eo_enable_dfe_h1_cal, 0b0, def_bus_id2; rx_eo_enable_final_l2u_adj, 0b1, def_bus_id0; rx_eo_enable_final_l2u_adj, 0b1, def_bus_id1; rx_eo_enable_final_l2u_adj, 0b1, def_bus_id2; rx_eo_enable_h1ap_tweak, 0b0, def_bus_id0; rx_eo_enable_h1ap_tweak, 0b0, def_bus_id1; rx_eo_enable_h1ap_tweak, 0b0, def_bus_id2; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0; rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG scom 0x8009A80008010C3F { bits, scom_data, expr; rx_fence, 0b1, def_bus_id0; rx_fence, 0b1, def_bus_id1; rx_fence, 0b1, def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG scom 0x8008500008010C3F { bits, scom_data, expr; rx_bus_id, 0b000001, def_bus_id0; rx_bus_id, 0b000010, def_bus_id1; rx_bus_id, 0b000011, def_bus_id2; rx_group_id, 0b000000, def_bus_id0; rx_group_id, 0b000000, def_bus_id1; rx_group_id, 0b000000, def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_ID2_PG scom 0x8008580008010C3F { bits, scom_data, expr; rx_last_group_id, 0b000000, def_bus_id0; rx_last_group_id, 0b000000, def_bus_id1; rx_last_group_id, 0b000000, def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_ID3_PG scom 0x8008600008010C3F { bits, scom_data, expr; rx_end_lane_id, 0b0010110, def_bus_id0; rx_end_lane_id, 0b0010110, def_bus_id1; rx_end_lane_id, 0b0010110, def_bus_id2; rx_start_lane_id, 0b0000000, def_bus_id0; rx_start_lane_id, 0b0000000, def_bus_id1; rx_start_lane_id, 0b0000000, def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG scom 0x8009280008010C3F { bits, scom_data, expr; rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0; rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1; rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG scom 0x8009300008010C3F { bits, scom_data, expr; rx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id0; rx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id1; rx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG scom 0x8009C00008010C3F { bits, scom_data, expr; rx_c4_sel, 0b00, def_IS_HW && def_bus_id0; rx_c4_sel, 0b00, def_IS_HW && def_bus_id1; rx_c4_sel, 0b11, def_IS_VBU && def_bus_id1; rx_c4_sel, 0b00, def_IS_HW && def_bus_id2; rx_c4_sel, 0b11, def_IS_VBU && def_bus_id2; rx_c4_sel, 0b11, def_IS_VBU && def_bus_id0; rx_c4_sel, 0b00, def_IS_HW && def_bus_id1; rx_c4_sel, 0b11, def_IS_VBU && def_bus_id1; rx_c4_sel, 0b00, def_IS_HW && def_bus_id2; rx_c4_sel, 0b11, def_IS_VBU && def_bus_id2; rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id0; rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id1; rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id1; rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id2; rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id2; rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id0; rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id1; rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id1; rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id2; rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG scom 0x8008180008010C3F { bits, scom_data, expr; rx_master_mode, 0b1, def_is_master; rx_master_mode, 0b1, def_is_master; rx_master_mode, 0b1, def_is_master; } #RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG scom 0x800AB80008010C3F { bits, scom_data, expr; rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id0; rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id1; rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id2; rx_rc_enable_h1ap_tweak, 0b0, def_bus_id0; rx_rc_enable_h1ap_tweak, 0b0, def_bus_id1; rx_rc_enable_h1ap_tweak, 0b0, def_bus_id2; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0; rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO1_PP scom 0x800B900008010C3F { bits, scom_data, expr; rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP scom 0x800B980008010C3F { bits, scom_data, expr; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP scom 0x800BA00008010C3F { bits, scom_data, expr; rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP scom 0x800B600008010C3F { bits, scom_data, expr; rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP scom 0x800B680008010C3F { bits, scom_data, expr; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP scom 0x800B700008010C3F { bits, scom_data, expr; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG scom 0x8009100008010C3F { bits, scom_data, expr; rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG scom 0x8008980008010C3F { bits, scom_data, expr; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id0; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id1; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id0; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id1; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2; rx_ds_timeout_sel, 0b111, def_bus_id0; rx_ds_timeout_sel, 0b111, def_bus_id1; rx_ds_timeout_sel, 0b111, def_bus_id2; rx_sls_timeout_sel, 0b110, def_bus_id0; rx_sls_timeout_sel, 0b110, def_bus_id1; rx_sls_timeout_sel, 0b110, def_bus_id2; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id1; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id2; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id0; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id1; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id2; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG scom 0x8009980008010C3F { bits, scom_data, expr; rx_rx_bus_width, 0b0010111, def_bus_id0; rx_rx_bus_width, 0b0010111, def_bus_id1; rx_rx_bus_width, 0b0010111, def_bus_id2; rx_tx_bus_width, 0b0010111, def_bus_id0; rx_tx_bus_width, 0b0010111, def_bus_id1; rx_tx_bus_width, 0b0010111, def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG scom 0x8009580008010C3F { bits, scom_data, expr; rx_wtr_max_bad_lanes, 0b00001, def_bus_id0; rx_wtr_max_bad_lanes, 0b00001, def_bus_id1; rx_wtr_max_bad_lanes, 0b00001, def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG scom 0x800A300008010C3F { bits, scom_data, expr; rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id0; rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id0; rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id0; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id1; rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id1; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id2; rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id2; rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id0; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id1; rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id1; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id2; rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000501508010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01508010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b001, def_bus_id0; rx_prbs_tap_id, 0b001, def_bus_id1; rx_prbs_tap_id, 0b001, def_bus_id2; } #RX0.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000501408010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01408010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b010, def_bus_id0; rx_prbs_tap_id, 0b010, def_bus_id1; rx_prbs_tap_id, 0b010, def_bus_id2; } #RX0.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000501608010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01608010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b000, def_bus_id0; rx_prbs_tap_id, 0b000, def_bus_id1; rx_prbs_tap_id, 0b000, def_bus_id2; } #RX0.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500A08010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00A08010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b010, def_bus_id0; rx_prbs_tap_id, 0b010, def_bus_id1; rx_prbs_tap_id, 0b010, def_bus_id2; } #RX0.RXPACKS#0.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500B08010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#0.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00B08010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b011, def_bus_id0; rx_prbs_tap_id, 0b011, def_bus_id1; rx_prbs_tap_id, 0b011, def_bus_id2; } #RX0.RXPACKS#0.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500908010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#0.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00908010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b001, def_bus_id0; rx_prbs_tap_id, 0b001, def_bus_id1; rx_prbs_tap_id, 0b001, def_bus_id2; } #RX0.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000501208010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01208010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b100, def_bus_id0; rx_prbs_tap_id, 0b100, def_bus_id1; rx_prbs_tap_id, 0b100, def_bus_id2; } #RX0.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000501708010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01708010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b000, def_bus_id0; rx_prbs_tap_id, 0b000, def_bus_id1; rx_prbs_tap_id, 0b000, def_bus_id2; } #RX0.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500708010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00708010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b111, def_bus_id0; rx_prbs_tap_id, 0b111, def_bus_id1; rx_prbs_tap_id, 0b111, def_bus_id2; } #RX0.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000501308010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01308010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b011, def_bus_id0; rx_prbs_tap_id, 0b011, def_bus_id1; rx_prbs_tap_id, 0b011, def_bus_id2; } #RX0.RXPACKS#1.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500608010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#1.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00608010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b110, def_bus_id0; rx_prbs_tap_id, 0b110, def_bus_id1; rx_prbs_tap_id, 0b110, def_bus_id2; } #RX0.RXPACKS#1.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500808010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#1.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00808010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b000, def_bus_id0; rx_prbs_tap_id, 0b000, def_bus_id1; rx_prbs_tap_id, 0b000, def_bus_id2; } #RX0.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500508010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00508010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b101, def_bus_id0; rx_prbs_tap_id, 0b101, def_bus_id1; rx_prbs_tap_id, 0b101, def_bus_id2; } #RX0.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500308010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00308010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b011, def_bus_id0; rx_prbs_tap_id, 0b011, def_bus_id1; rx_prbs_tap_id, 0b011, def_bus_id2; } #RX0.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000501108010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01108010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b101, def_bus_id0; rx_prbs_tap_id, 0b101, def_bus_id1; rx_prbs_tap_id, 0b101, def_bus_id2; } #RX0.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500408010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00408010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b100, def_bus_id0; rx_prbs_tap_id, 0b100, def_bus_id1; rx_prbs_tap_id, 0b100, def_bus_id2; } #RX0.RXPACKS#2.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000501008010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#2.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01008010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b110, def_bus_id0; rx_prbs_tap_id, 0b110, def_bus_id1; rx_prbs_tap_id, 0b110, def_bus_id2; } #RX0.RXPACKS#2.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500F08010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#2.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00F08010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b111, def_bus_id0; rx_prbs_tap_id, 0b111, def_bus_id1; rx_prbs_tap_id, 0b111, def_bus_id2; } #RX0.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500008010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00008010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b000, def_bus_id0; rx_prbs_tap_id, 0b000, def_bus_id1; rx_prbs_tap_id, 0b000, def_bus_id2; } #RX0.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500208010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00208010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b010, def_bus_id0; rx_prbs_tap_id, 0b010, def_bus_id1; rx_prbs_tap_id, 0b010, def_bus_id2; } #RX0.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500108010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00108010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b001, def_bus_id0; rx_prbs_tap_id, 0b001, def_bus_id1; rx_prbs_tap_id, 0b001, def_bus_id2; } #RX0.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500E08010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00E08010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b000, def_bus_id0; rx_prbs_tap_id, 0b000, def_bus_id1; rx_prbs_tap_id, 0b000, def_bus_id2; } #RX0.RXPACKS#3.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500C08010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#3.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00C08010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b010, def_bus_id0; rx_prbs_tap_id, 0b010, def_bus_id1; rx_prbs_tap_id, 0b010, def_bus_id2; } #RX0.RXPACKS#3.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_AMP_VAL_PL scom 0x8000500D08010C3F { bits, scom_data, expr; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; } #RX0.RXPACKS#3.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00D08010C3F { bits, scom_data, expr; rx_prbs_tap_id, 0b001, def_bus_id0; rx_prbs_tap_id, 0b001, def_bus_id1; rx_prbs_tap_id, 0b001, def_bus_id2; } #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG scom 0x800CC40008010C3F { bits, scom_data, expr; tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id0; tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id1; tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id2; } #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_DYN_RECAL_TIMEOUTS_PP scom 0x800EAC0008010C3F { bits, scom_data, expr; tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; } #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG scom 0x800C940008010C3F { bits, scom_data, expr; tx_bus_id, 0b000001, def_bus_id0; tx_bus_id, 0b000010, def_bus_id1; tx_bus_id, 0b000011, def_bus_id2; tx_group_id, 0b100000, def_bus_id0; tx_group_id, 0b100000, def_bus_id1; tx_group_id, 0b100000, def_bus_id2; } #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID2_PG scom 0x800C9C0008010C3F { bits, scom_data, expr; tx_last_group_id, 0b100000, def_bus_id0; tx_last_group_id, 0b100000, def_bus_id1; tx_last_group_id, 0b100000, def_bus_id2; } #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID3_PG scom 0x800CA40008010C3F { bits, scom_data, expr; tx_end_lane_id, 0b0010110, def_bus_id0; tx_end_lane_id, 0b0010110, def_bus_id1; tx_end_lane_id, 0b0010110, def_bus_id2; tx_start_lane_id, 0b0000000, def_bus_id0; tx_start_lane_id, 0b0000000, def_bus_id1; tx_start_lane_id, 0b0000000, def_bus_id2; } #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG scom 0x800D1C0008010C3F { bits, scom_data, expr; tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0; tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1; tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2; } #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG scom 0x800D240008010C3F { bits, scom_data, expr; tx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id0; tx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id1; tx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id2; } #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_MODE_PG scom 0x800C1C0008010C3F { bits, scom_data, expr; tx_max_bad_lanes, 0b00001, def_bus_id0; tx_max_bad_lanes, 0b00001, def_bus_id1; tx_max_bad_lanes, 0b00001, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341108010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b101, def_bus_id0; tx_prbs_tap_id, 0b101, def_bus_id1; tx_prbs_tap_id, 0b101, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341208010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b100, def_bus_id0; tx_prbs_tap_id, 0b100, def_bus_id1; tx_prbs_tap_id, 0b100, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341608010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b000, def_bus_id0; tx_prbs_tap_id, 0b000, def_bus_id1; tx_prbs_tap_id, 0b000, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340008010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b000, def_bus_id0; tx_prbs_tap_id, 0b000, def_bus_id1; tx_prbs_tap_id, 0b000, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341008010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b110, def_bus_id0; tx_prbs_tap_id, 0b110, def_bus_id1; tx_prbs_tap_id, 0b110, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340108010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b001, def_bus_id0; tx_prbs_tap_id, 0b001, def_bus_id1; tx_prbs_tap_id, 0b001, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341408010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b010, def_bus_id0; tx_prbs_tap_id, 0b010, def_bus_id1; tx_prbs_tap_id, 0b010, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341508010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b001, def_bus_id0; tx_prbs_tap_id, 0b001, def_bus_id1; tx_prbs_tap_id, 0b001, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340E08010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b000, def_bus_id0; tx_prbs_tap_id, 0b000, def_bus_id1; tx_prbs_tap_id, 0b000, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340908010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b001, def_bus_id0; tx_prbs_tap_id, 0b001, def_bus_id1; tx_prbs_tap_id, 0b001, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340208010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b010, def_bus_id0; tx_prbs_tap_id, 0b010, def_bus_id1; tx_prbs_tap_id, 0b010, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004341308010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b011, def_bus_id0; tx_prbs_tap_id, 0b011, def_bus_id1; tx_prbs_tap_id, 0b011, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340308010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b011, def_bus_id0; tx_prbs_tap_id, 0b011, def_bus_id1; tx_prbs_tap_id, 0b011, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340508010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b101, def_bus_id0; tx_prbs_tap_id, 0b101, def_bus_id1; tx_prbs_tap_id, 0b101, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340408010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b100, def_bus_id0; tx_prbs_tap_id, 0b100, def_bus_id1; tx_prbs_tap_id, 0b100, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340D08010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b001, def_bus_id0; tx_prbs_tap_id, 0b001, def_bus_id1; tx_prbs_tap_id, 0b001, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340808010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b000, def_bus_id0; tx_prbs_tap_id, 0b000, def_bus_id1; tx_prbs_tap_id, 0b000, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340608010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b110, def_bus_id0; tx_prbs_tap_id, 0b110, def_bus_id1; tx_prbs_tap_id, 0b110, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340708010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b111, def_bus_id0; tx_prbs_tap_id, 0b111, def_bus_id1; tx_prbs_tap_id, 0b111, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340C08010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b010, def_bus_id0; tx_prbs_tap_id, 0b010, def_bus_id1; tx_prbs_tap_id, 0b010, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340B08010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b011, def_bus_id0; tx_prbs_tap_id, 0b011, def_bus_id1; tx_prbs_tap_id, 0b011, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340A08010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b010, def_bus_id0; tx_prbs_tap_id, 0b010, def_bus_id1; tx_prbs_tap_id, 0b010, def_bus_id2; } #TX_WRAP.TX0.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340F08010C3F { bits, scom_data, expr; tx_prbs_tap_id, 0b111, def_bus_id0; tx_prbs_tap_id, 0b111, def_bus_id1; tx_prbs_tap_id, 0b111, def_bus_id2; }