#-- $Id: mbs_def.initfile,v 1.47 2014/03/19 19:38:44 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- #-- 1.47 |tschang | 3/19/14| SW252733 - L4 Cache UE Handling #-- 1.46 |tschang | 3/19/14| SW252733 - L4 Cache UE Handling typo #-- 1.45 |tschang | 2/24/14| fixed MBA1 only cfg #-- 1.44 |tschang | 2/17/14| bit 12 of MBAXCR23Q should be the same as MBAXCR01Q #-- 1.43 |tschang | 2/07/14| HW246685 - RCE reported even if we also have chip marks or symbol marks in place #-- 1.42 |tschang |01/30/14| Removed CDIMM TYPE and replace with custom dimm #-- 1.41 |tschang |01/24/13| SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT changed to ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT #-- SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE changed to ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE #-- 1.40 |tschang |11/21/13| HW271989 - updated SCOM write to do a full 64 bit write instead of a RMW #-- 1.39 |tschang |11/12/13| no functional changes - clean up unused variables #-- 1.38 |tschang |10/30/13| hash mode update for other IBM types #-- 1.37 |tschang |08/15/13| HW259719 - dd2 only fix - ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL to turn on clock gates #-- 1.36 |tschang |07/03/13| L4.ATTR_FUNCTIONAL for cache enable for some bits I missed #-- 1.35 |tschang |07/02/13| L4.ATTR_FUNCTIONAL for cache enable #-- 1.34 |tschang |06/11/13| removed mask out bit 8 - internal parity error - HW244827 and HW251643 #-- 1.33 |tschang |06/06/13| mask out bit 8 - internal parity error - HW244827 and HW251643 #-- 1.32 |tschang |04/24/13| fixed 1d cfg type #-- 1.31 |tschang |04/17/13| hash mode updated for type 1a/1b/5b #-- 1.30 |tschang |04/16/13| updated file for new IBM_TYPE defnitions #-- 1.29 |tschang |04/08/13| added MBI cfg register initialization for Irving #-- 1.26 |tschang |03/13/13| changed cache interleave mode to have ATTR_MSS_CACHE_ENABLE as a condition #-- 1.25 |tschang |01/17/13| cache enabled when (ATTR_MSS_CACHE_ENABLE != 0) - enabled cache when 1/2 cache mode is choosen #-- 1.21 |tschang |10/23/12| disable interleaving when one or both MBA are disabled (partial good tests) #-- 1.20 |tschang |09/27/12| added partial good support for the SCOM write using ATTR_FUNCTIONAL #-- 1.19 |menlowuu|08/21/12| fixed 2 address typo's #-- 1.18 |tschang |08/20/12| added mbs mcbist setup values for simple write and read test #-- 1.17 |bellows |07/23/12| made ATTR_MSS_CACHE_ENABLE at centaur level instead of system #-- 1.16 |yctschan|07/05/12| Removed sticks for subtype B #-- 1.14 |yctschan|06/28/12| Cleanup define syntax and ()'s #-- 1.13 |menlowuu|06/28/12| Fixed 0x201140B/C bit 9 definition #-- 1.12 |yctschan| 6/25/12| Stuck subtype to B in MBAXCR01Q and MBAXCR23Q bits 4:5 until IBM_TYPE is fixed #-- 1.6 |mwuu |05/09/12| Added extra '()' to work with new compiler #-- 1.5 |bellows |05/03/12| Updates for working version #-- |bellows |04/26/12| Match 1B hardware config #-- |bellows |04/26/12| Updates for VBU #-- |mwuu |04/19/12| fixed MBAXCR01Q address for MBA23 #-- 0.01 |retter |01/13/12| Initial version #-- --------|--------|--------|-------------------------------------------------- #-------------------------------------------------------------------------------- # End of revision history #-------------------------------------------------------------------------------- #--Master list of variables that can be used in this file is at: #-- SyntaxVersion = 1 #-- ----------------------------------------------------------------------------- #--****************************************************************************** #-- ----------------------------------------------------------------------------- #-- #-- Defines #-- #-- ----------------------------------------------------------------------------- #--****************************************************************************** #-- ----------------------------------------------------------------------------- define def_equal_test = (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT32_2); # EFF_DIMM_RANKS_CONFIGED [a][b] - a=0, def_mba01 a = 1, def_mba23 # - b=0, socket0 (mrank 0:3) b = 1, socket1 (mrank 4:7)) # EFF_NUM_RANKS_PER_DIMM = total number of master and slave ranks per socket # # ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] u8[2][2] 0x80 # ATTR_EFF_MBA_POS (0=01, 1=2/3) # # ATTR_EFF_IBM_TYPE # UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_2A = 4, TYPE_2B = 5, TYPE_2C = 6, TYPE_3A = 7, TYPE_3B = 8, TYPE_3C = 9, TYPE_4A = 10, TYPE_4B = 11, TYPE_4C = 12, # TYPE_5A = 13, TYPE_5B = 14, TYPE_5C = 15, TYPE_5D = 16, TYPE_6A = 17, TYPE_6B = 18, TYPE_6C = 19, TYPE_7A = 20, TYPE_7B = 21, TYPE_7C = 22, TYPE_8A = 23, TYPE_8B = 24, TYPE_8C = 25 # # ATTR_EFF_NUM_DROPS_PER_PORT # EMPTY = 0, SINGLE = 1, DUAL = 2 # # ATTR_EFF_DIMM_TYPE # CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3 # # ATTR_EFF_DRAM_DLL_PPD # SLOWEXIT = 0, FASTEXIT = 1 # # ATTR_EFF_DRAM_GEN # EMPTY = 0, DDR3 = 1, DDR4 = 2 # # CENTAUR.ATTR_MSS_FREQ = frequency # not an mba attribute will need hierachy # # ATTR_CHIP_UNIT_POS # 0 = MBA0 (mba01), 1 = MBA1 (mba23) # # SYS.ATTR_MSS_CACHE_ENABLE define MBA0 = TGT1; define MBA1 = TGT2; define L4 = TGT3; #define CENTAUR = TGT4; # parent Centaur # MBA0.ATTR_CHIP_UNIT_POS - that should equal 0 # MBA1.ATTR_CHIP_UNIT_POS should equal define def_no_spare = (SYS.ATTR_IS_SIMULATION==1) ; define def_has_spare = (SYS.ATTR_IS_SIMULATION==0) ; define def_mba01_nomem = ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0b00000000) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0b00000000)); define def_mba23_nomem = ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0b00000000) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0b00000000)); # MBA0 (mba01) define def_mba01_1a_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); # DDR3/4 are same define def_mba01_1a_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2));# || (def_mba01_1b_cdimm)); # DDR3/4 are same #define def_mba01_1a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as 1a_1socket RDIMM define def_mba01_1b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba01_1b_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_1c_cdimm)); #define def_mba01_1b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1A 2 socket RDIMM cfg for DDR3/4 ## 1C 1 and 2 sockets not supported #define def_mba01_1c_1socket = 0; #define def_mba01_1c_2socket = 0; #define def_mba01_1c_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false #define def_mba01_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba01_1c_1socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || def_mba01_1d_1socket; define def_mba01_1c_2socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || def_mba01_1d_2socket; define def_mba01_1c_cdimm = (((MBA0.ATTR_EFF_IBM_TYPE[1][0] == 3 ) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 )) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1B 2 socket RDIMM cfg for DDR3/4 ## Current they is no 1D IBM type in the attribute #define def_mba01_1d_1socket = 0; #define def_mba01_1d_2socket = 0; #define def_mba01_1d_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false #define def_mba01_1d_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba01_1d_1socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba01_1d_2socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); ## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs define def_mba01_2a_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_cdimm)); define def_mba01_2a_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_2c_cdimm) || (def_mba01_3a_cdimm)); define def_mba01_2a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket cfg define def_mba01_2a_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_ddr4_cdimm)); define def_mba01_2a_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3a_ddr4_cdimm)); define def_mba01_2a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket DDR4 cfg define def_mba01_2b_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2b_cdimm)); define def_mba01_2b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); define def_mba01_2b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket cfg define def_mba01_2b_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2b_ddr4_cdimm)); define def_mba01_2b_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3b_ddr4_cdimm)); define def_mba01_2b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket DDR4 cfg # centuar spec only has DDR4 for 2C cfg define def_mba01_2c_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_cdimm)); define def_mba01_2c_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); define def_mba01_2c_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket cfg define def_mba01_2c_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_ddr4_cdimm)); define def_mba01_2c_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3c_ddr4_cdimm)); define def_mba01_2c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket DDR4 cfg define def_mba01_3a_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba01_3a_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4a_cdimm)); #define def_mba01_3a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 2 socket cfg define def_mba01_3a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1))) && (MBA0.ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg define def_mba01_3a_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba01_3a_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4a_ddr4_cdimm)); define def_mba01_3a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1))) && (MBA0.ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg define def_mba01_3b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba01_3b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); define def_mba01_3b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg define def_mba01_3b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg ?? define def_mba01_3c_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba01_3c_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4c_ddr4_cdimm)); define def_mba01_3c_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg define def_mba01_3c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg define def_mba01_4a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 11))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket cfg define def_mba01_4a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 11))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket DDR4 cfg define def_mba01_4b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 12))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3B 2 socket DDR4 cfg define def_mba01_4c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 13))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3C 2 socket DDR4 cfg define def_mba01_5b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_5b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_5c_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 16))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_5c_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 16))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_5d_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 17))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_5d_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 17))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_7a_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_7a_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_7a_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_7a_2socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_7b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_7b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_7b_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_7b_2socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_7c_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_7c_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_7c_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_7c_2socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); # MBA1 (mba23) define def_mba23_1a_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); # DDR3/4 are same define def_mba23_1a_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2));# || (def_mba23_1b_cdimm)); # DDR3/4 are same #define def_mba23_1a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as 1a_1socket RDIMM define def_mba23_1b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba23_1b_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_1c_cdimm)); #define def_mba23_1b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1A 2 socket RDIMM cfg for DDR3/4 ## 1C 1 and 2 sockets not supported #define def_mba23_1c_1socket = 0; #define def_mba23_1c_2socket = 0; #define def_mba23_1c_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false #define def_mba23_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba23_1c_1socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || def_mba23_1d_1socket; define def_mba23_1c_2socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || def_mba23_1d_2socket; define def_mba23_1c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1B 2 socket RDIMM cfg for DDR3/4 ## Current they is no 1D IBM type in the attribute #define def_mba23_1d_1socket = 0; #define def_mba23_1d_2socket = 0; #define def_mba23_1d_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false #define def_mba23_1d_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba23_1d_1socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba23_1d_2socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); ## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs define def_mba23_2a_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_cdimm)); define def_mba23_2a_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_2c_cdimm) || (def_mba23_3a_cdimm)); define def_mba23_2a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket cfg define def_mba23_2a_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_ddr4_cdimm)); define def_mba23_2a_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3a_ddr4_cdimm)); define def_mba23_2a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket DDR4 cfg define def_mba23_2b_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2b_cdimm)); define def_mba23_2b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); define def_mba23_2b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket cfg define def_mba23_2b_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2b_ddr4_cdimm)); define def_mba23_2b_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3b_ddr4_cdimm)); define def_mba23_2b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket DDR4 cfg # centuar spec only has DDR4 for 2C cfg define def_mba23_2c_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_cdimm)); define def_mba23_2c_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); define def_mba23_2c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket cfg define def_mba23_2c_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_ddr4_cdimm)); define def_mba23_2c_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3c_ddr4_cdimm)); define def_mba23_2c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket DDR4 cfg define def_mba23_3a_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba23_3a_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4a_cdimm)); #define def_mba23_3a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 2 socket cfg define def_mba23_3a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1))) && (MBA1.ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg define def_mba23_3a_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba23_3a_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4a_ddr4_cdimm)); define def_mba23_3a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1))) && (MBA1.ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg define def_mba23_3b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba23_3b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); define def_mba23_3b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg define def_mba23_3b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg ?? define def_mba23_3c_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_mba23_3c_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4c_ddr4_cdimm)); define def_mba23_3c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg define def_mba23_3c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg define def_mba23_4a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket cfg define def_mba23_4a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket DDR4 cfg define def_mba23_4b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3B 2 socket DDR4 cfg define def_mba23_4c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 13))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3C 2 socket DDR4 cfg define def_mba23_5b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_5b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_5c_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 16))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_5c_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 16))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_5d_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 17))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_5d_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 17))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_7a_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_7a_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_7a_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_7a_2socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_7b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_7b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_7b_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_7b_2socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_7c_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_7c_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_7c_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba23_7c_2socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); define def_mba01_mtype_1a = (def_mba01_1a_1socket ||def_mba01_1a_2socket);# ||def_mba01_1b_cdimm); define def_mba01_mtype_1b = (def_mba01_1b_1socket ||def_mba01_1b_2socket ||def_mba01_1c_cdimm); define def_mba01_mtype_1c = (def_mba01_1c_1socket ||def_mba01_1c_2socket); define def_mba01_mtype_2a = (def_mba01_2a_1socket ||def_mba01_2a_2socket ||def_mba01_2a_1socket_ddr4||def_mba01_2a_2socket_ddr4||def_mba01_3a_cdimm ||def_mba01_3a_ddr4_cdimm); define def_mba01_mtype_2b = (def_mba01_2b_1socket ||def_mba01_2b_2socket ||def_mba01_2b_1socket_ddr4||def_mba01_2b_2socket_ddr4||def_mba01_3b_cdimm ||def_mba01_3b_ddr4_cdimm); define def_mba01_mtype_2c = (def_mba01_2c_1socket ||def_mba01_2c_2socket ||def_mba01_2c_1socket_ddr4||def_mba01_2c_2socket_ddr4||def_mba01_3c_cdimm ||def_mba01_3c_ddr4_cdimm); define def_mba01_mtype_3a = (def_mba01_3a_1socket ||def_mba01_3a_2socket ||def_mba01_3a_1socket_ddr4||def_mba01_3a_2socket_ddr4||def_mba01_4a_cdimm ||def_mba01_4a_ddr4_cdimm); define def_mba01_mtype_3b = (def_mba01_3b_1socket ||def_mba01_3b_2socket ||def_mba01_4b_ddr4_cdimm); define def_mba01_mtype_3c = (def_mba01_3c_1socket_ddr4||def_mba01_3c_2socket_ddr4||def_mba01_4c_ddr4_cdimm); #define def_mba01_mtype_4a = 0; # not supported #define def_mba01_mtype_4b = 0; # not supported #define def_mba01_mtype_4c = 0; # not supported #define def_mba01_mtype_5a = 0; # not supported define def_mba01_mtype_4a = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba01_mtype_4b = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba01_mtype_4c = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba01_mtype_5a = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba01_mtype_5b = ((def_mba01_5b_1socket )||(def_mba01_5b_2socket)); define def_mba01_mtype_5c = ((def_mba01_5c_1socket )||(def_mba01_5c_2socket)); define def_mba01_mtype_5d = ((def_mba01_5d_1socket )||(def_mba01_5d_2socket)); #define def_mba01_mtype_6a = 0; # not supported #define def_mba01_mtype_6b = 0; # not supported #define def_mba01_mtype_6c = 0; # not supported define def_mba01_mtype_6a = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba01_mtype_6b = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba01_mtype_6c = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba01_mtype_7a = (def_mba01_7a_1socket ||def_mba01_7a_2socket ||def_mba01_7a_1socket_ddr4||def_mba01_7a_2socket_ddr4); define def_mba01_mtype_7b = (def_mba01_7b_1socket ||def_mba01_7b_2socket ||def_mba01_7b_1socket_ddr4||def_mba01_7b_2socket_ddr4); define def_mba01_mtype_7c = (def_mba01_7c_1socket ||def_mba01_7c_2socket ||def_mba01_7c_1socket_ddr4||def_mba01_7c_2socket_ddr4); define def_mba23_mtype_1a = (def_mba23_1a_1socket ||def_mba23_1a_2socket);# ||def_mba23_1b_cdimm); define def_mba23_mtype_1b = (def_mba23_1b_1socket ||def_mba23_1b_2socket ||def_mba23_1c_cdimm); define def_mba23_mtype_1c = (def_mba23_1c_1socket ||def_mba23_1c_2socket); define def_mba23_mtype_2a = (def_mba23_2a_1socket ||def_mba23_2a_2socket ||def_mba23_2a_1socket_ddr4||def_mba23_2a_2socket_ddr4||def_mba23_3a_cdimm ||def_mba23_3a_ddr4_cdimm); define def_mba23_mtype_2b = (def_mba23_2b_1socket ||def_mba23_2b_2socket ||def_mba23_2b_1socket_ddr4||def_mba23_2b_2socket_ddr4||def_mba23_3b_cdimm ||def_mba23_3b_ddr4_cdimm); define def_mba23_mtype_2c = (def_mba23_2c_1socket ||def_mba23_2c_2socket ||def_mba23_2c_1socket_ddr4||def_mba23_2c_2socket_ddr4||def_mba23_3c_cdimm ||def_mba23_3c_ddr4_cdimm); define def_mba23_mtype_3a = (def_mba23_3a_1socket ||def_mba23_3a_2socket ||def_mba23_3a_1socket_ddr4||def_mba23_3a_2socket_ddr4||def_mba23_4a_cdimm ||def_mba23_4a_ddr4_cdimm); define def_mba23_mtype_3b = (def_mba23_3b_1socket ||def_mba23_3b_2socket ||def_mba23_4b_ddr4_cdimm); define def_mba23_mtype_3c = (def_mba23_3c_1socket_ddr4||def_mba23_3c_2socket_ddr4||def_mba23_4c_ddr4_cdimm); #define def_mba23_mtype_4a = 0; # not supported #define def_mba23_mtype_4b = 0; # not supported #define def_mba23_mtype_4c = 0; # not supported #define def_mba23_mtype_5a = 0; # not supported define def_mba23_mtype_4a = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba23_mtype_4b = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba23_mtype_4c = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba23_mtype_5a = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba23_mtype_5b = ((def_mba23_5b_1socket )||(def_mba23_5b_2socket)); define def_mba23_mtype_5c = ((def_mba23_5c_1socket )||(def_mba23_5c_2socket)); define def_mba23_mtype_5d = ((def_mba23_5d_1socket )||(def_mba23_5d_2socket)); #define def_mba23_mtype_6a = 0; # not supported #define def_mba23_mtype_6b = 0; # not supported #define def_mba23_mtype_6c = 0; # not supported define def_mba23_mtype_6a = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba23_mtype_6b = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba23_mtype_6c = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false define def_mba23_mtype_7a = (def_mba23_7a_1socket ||def_mba23_7a_2socket ||def_mba23_7a_1socket_ddr4||def_mba23_7a_2socket_ddr4); define def_mba23_mtype_7b = (def_mba23_7b_1socket ||def_mba23_7b_2socket ||def_mba23_7b_1socket_ddr4||def_mba23_7b_2socket_ddr4); define def_mba23_mtype_7c = (def_mba23_7c_1socket ||def_mba23_7c_2socket ||def_mba23_7c_1socket_ddr4||def_mba23_7c_2socket_ddr4); define def_mba01_type1_memory_populated_behind_MBA01 = (def_mba01_mtype_1a ||def_mba01_mtype_1b ||def_mba01_mtype_1c);# ||def_mba01_mtype_1d); define def_mba01_type2_memory_populated_behind_MBA01 = (def_mba01_mtype_2a ||def_mba01_mtype_2b ||def_mba01_mtype_2c ||def_mba01_mtype_5d); define def_mba01_type3_memory_populated_behind_MBA01 = (def_mba01_mtype_3a ||def_mba01_mtype_3b ||def_mba01_mtype_3c); define def_mba01_type4_memory_populated_behind_MBA01 = (def_mba01_mtype_4a ||def_mba01_mtype_4b ||def_mba01_mtype_4c); define def_mba01_type5_memory_populated_behind_MBA01 = (def_mba01_mtype_5a ||def_mba01_mtype_5b ||def_mba01_mtype_5c); define def_mba01_type6_memory_populated_behind_MBA01 = (def_mba01_mtype_6a ||def_mba01_mtype_6b ||def_mba01_mtype_6c); define def_mba01_type7_memory_populated_behind_MBA01 = (def_mba01_mtype_7a ||def_mba01_mtype_7b ||def_mba01_mtype_7c); #define def_mba01_type8_memory_populated_behind_MBA01 = (def_mba01_mtype_8a ||def_mba01_mtype_8b ||def_mba01_mtype_8c); define def_mba23_type1_memory_populated_behind_MBA23 = (def_mba23_mtype_1a ||def_mba23_mtype_1b ||def_mba23_mtype_1c);# ||def_mba23_mtype_1d); define def_mba23_type2_memory_populated_behind_MBA23 = (def_mba23_mtype_2a ||def_mba23_mtype_2b ||def_mba23_mtype_2c ||def_mba23_mtype_5d); define def_mba23_type3_memory_populated_behind_MBA23 = (def_mba23_mtype_3a ||def_mba23_mtype_3b ||def_mba23_mtype_3c); define def_mba23_type4_memory_populated_behind_MBA23 = (def_mba23_mtype_4a ||def_mba23_mtype_4b ||def_mba23_mtype_4c); define def_mba23_type5_memory_populated_behind_MBA23 = (def_mba23_mtype_5a ||def_mba23_mtype_5b ||def_mba23_mtype_5c); define def_mba23_type6_memory_populated_behind_MBA23 = (def_mba23_mtype_6a ||def_mba23_mtype_6b ||def_mba23_mtype_6c); define def_mba23_type7_memory_populated_behind_MBA23 = (def_mba23_mtype_7a ||def_mba23_mtype_7b ||def_mba23_mtype_7c); #define def_mba23_type8_memory_populated_behind_MBA23 = (def_mba23_mtype_8a ||def_mba23_mtype_8b ||def_mba23_mtype_8c); define def_mba01_subtype_A = (def_mba01_mtype_1a || def_mba01_mtype_2a || def_mba01_mtype_3a || def_mba01_mtype_4a || def_mba01_mtype_5a || def_mba01_mtype_6a || def_mba01_mtype_7a);# || def_mba01_mtype_8a); define def_mba01_subtype_B = (def_mba01_mtype_1b || def_mba01_mtype_2b || def_mba01_mtype_3b || def_mba01_mtype_4b || def_mba01_mtype_5b || def_mba01_mtype_6b || def_mba01_mtype_7b);# || def_mba01_mtype_8b); #define def_mba01_subtype_C = (def_mba01_mtype_1c || def_mba01_mtype_1d || def_mba01_mtype_2c || def_mba01_mtype_3c || def_mba01_mtype_4c || def_mba01_mtype_5c || def_mba01_mtype_5d || def_mba01_mtype_6c || def_mba01_mtype_7c);# || def_mba01_mtype_8c); define def_mba01_subtype_C = (def_mba01_mtype_1c || def_mba01_mtype_2c || def_mba01_mtype_3c || def_mba01_mtype_4c || def_mba01_mtype_5c || def_mba01_mtype_5d || def_mba01_mtype_6c || def_mba01_mtype_7c );# || def_mba01_mtype_8c); define def_mba23_subtype_A = (def_mba23_mtype_1a || def_mba23_mtype_2a || def_mba23_mtype_3a || def_mba23_mtype_4a || def_mba23_mtype_5a || def_mba23_mtype_6a || def_mba23_mtype_7a);# || def_mba23_mtype_8a); define def_mba23_subtype_B = (def_mba23_mtype_1b || def_mba23_mtype_2b || def_mba23_mtype_3b || def_mba23_mtype_4b || def_mba23_mtype_5b || def_mba23_mtype_6b || def_mba23_mtype_7b);# || def_mba23_mtype_8b); #define def_mba23_subtype_C = (def_mba23_mtype_1c || def_mba23_mtype_1d || def_mba23_mtype_2c || def_mba23_mtype_3c || def_mba23_mtype_4c || def_mba23_mtype_5c || def_mba23_mtype_5d || def_mba23_mtype_6c || def_mba23_mtype_7c);# || def_mba23_mtype_8c); define def_mba23_subtype_C = (def_mba23_mtype_1c || def_mba23_mtype_2c || def_mba23_mtype_3c || def_mba23_mtype_4c || def_mba23_mtype_5c || def_mba23_mtype_5d || def_mba23_mtype_6c || def_mba23_mtype_7c );# || def_mba23_mtype_8c); define def_mba01_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated = (def_mba01_1a_1socket ||def_mba01_1b_1socket ||def_mba01_1c_1socket ||def_mba01_2a_1socket ||def_mba01_2a_1socket_ddr4 ||def_mba01_2b_1socket ||def_mba01_2b_1socket_ddr4 ||def_mba01_2c_1socket ||def_mba01_2c_1socket_ddr4 ||def_mba01_3a_1socket ||def_mba01_3a_1socket_ddr4 ||def_mba01_3b_1socket ||def_mba01_3c_1socket_ddr4 ||def_mba01_5b_1socket ||def_mba01_5c_1socket ||def_mba01_5d_1socket ||def_mba01_7a_1socket ||def_mba01_7b_1socket ||def_mba01_7c_1socket ||def_mba01_7a_1socket_ddr4 ||def_mba01_7b_1socket_ddr4 ||def_mba01_7c_1socket_ddr4); define def_mba01_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mba01_1a_2socket ||def_mba01_1b_2socket ||def_mba01_1c_2socket ||def_mba01_2a_2socket ||def_mba01_2a_2socket_ddr4 ||def_mba01_2b_2socket ||def_mba01_2b_2socket_ddr4 ||def_mba01_2c_2socket ||def_mba01_2c_2socket_ddr4 ||def_mba01_3a_2socket ||def_mba01_3a_2socket_ddr4 ||def_mba01_3b_2socket ||def_mba01_3c_2socket_ddr4 ||def_mba01_5b_2socket ||def_mba01_5c_2socket ||def_mba01_5d_2socket ||def_mba01_7a_2socket ||def_mba01_7b_2socket ||def_mba01_7c_2socket ||def_mba01_7a_2socket_ddr4 ||def_mba01_7b_2socket_ddr4 ||def_mba01_7c_2socket_ddr4 ||def_mba01_1c_cdimm ||def_mba01_3a_cdimm ||def_mba01_3b_cdimm ||def_mba01_3c_cdimm ||def_mba01_3a_ddr4_cdimm ||def_mba01_3b_ddr4_cdimm ||def_mba01_3c_ddr4_cdimm ||def_mba01_4a_cdimm ||def_mba01_4a_ddr4_cdimm ||def_mba01_4b_ddr4_cdimm ||def_mba01_4c_ddr4_cdimm); #define def_mba01_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mba01_1a_2socket ||def_mba01_1b_2socket ||def_mba01_1c_2socket ||def_mba01_2a_2socket ||def_mba01_2a_2socket_ddr4 ||def_mba01_2b_2socket ||def_mba01_2b_2socket_ddr4 ||def_mba01_2c_2socket ||def_mba01_2c_2socket_ddr4 ||def_mba01_3a_2socket ||def_mba01_3a_2socket_ddr4 ||def_mba01_3b_2socket ||def_mba01_3c_2socket_ddr4 ||def_mba01_5b_2socket ||def_mba01_5c_2socket ||def_mba01_5d_2socket ||def_mba01_7a_2socket ||def_mba01_7b_2socket ||def_mba01_7c_2socket ||def_mba01_7a_2socket_ddr4 ||def_mba01_7b_2socket_ddr4 ||def_mba01_7c_2socket_ddr4 ||def_mba01_1b_cdimm ||def_mba01_1c_cdimm ||def_mba01_3a_cdimm ||def_mba01_3b_cdimm ||def_mba01_3c_cdimm ||def_mba01_3a_ddr4_cdimm ||def_mba01_3b_ddr4_cdimm ||def_mba01_3c_ddr4_cdimm ||def_mba01_4a_cdimm ||def_mba01_4a_ddr4_cdimm ||def_mba01_4b_ddr4_cdimm ||def_mba01_4c_ddr4_cdimm); define def_mba23_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated = (def_mba23_1a_1socket ||def_mba23_1b_1socket ||def_mba23_1c_1socket ||def_mba23_2a_1socket ||def_mba23_2a_1socket_ddr4 ||def_mba23_2b_1socket ||def_mba23_2b_1socket_ddr4 ||def_mba23_2c_1socket ||def_mba23_2c_1socket_ddr4 ||def_mba23_3a_1socket ||def_mba23_3a_1socket_ddr4 ||def_mba23_3b_1socket ||def_mba23_3c_1socket_ddr4 ||def_mba23_5b_1socket ||def_mba23_5c_1socket ||def_mba23_5d_1socket ||def_mba23_7a_1socket ||def_mba23_7b_1socket ||def_mba23_7c_1socket ||def_mba23_7a_1socket_ddr4 ||def_mba23_7b_1socket_ddr4 ||def_mba23_7c_1socket_ddr4); #define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mba23_1a_2socket ||def_mba23_1b_2socket ||def_mba23_1c_2socket ||def_mba23_2a_2socket ||def_mba23_2a_2socket_ddr4 ||def_mba23_2b_2socket ||def_mba23_2b_2socket_ddr4 ||def_mba23_2c_2socket ||def_mba23_2c_2socket_ddr4 ||def_mba23_3a_2socket ||def_mba23_3a_2socket_ddr4 ||def_mba23_3b_2socket ||def_mba23_3c_2socket_ddr4 ||def_mba23_5b_2socket ||def_mba23_5c_2socket ||def_mba23_5d_2socket ||def_mba23_7a_2socket ||def_mba23_7b_2socket ||def_mba23_7c_2socket ||def_mba23_7a_2socket_ddr4 ||def_mba23_7b_2socket_ddr4 ||def_mba23_7c_2socket_ddr4 ||def_mba23_1b_cdimm ||def_mba23_1c_cdimm ||def_mba23_3a_cdimm ||def_mba23_3b_cdimm ||def_mba23_3c_cdimm ||def_mba23_3a_ddr4_cdimm ||def_mba23_3b_ddr4_cdimm ||def_mba23_3c_ddr4_cdimm ||def_mba23_4a_cdimm ||def_mba23_4a_ddr4_cdimm ||def_mba23_4b_ddr4_cdimm ||def_mba23_4c_ddr4_cdimm); define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mba23_1a_2socket ||def_mba23_1b_2socket ||def_mba23_1c_2socket ||def_mba23_2a_2socket ||def_mba23_2a_2socket_ddr4 ||def_mba23_2b_2socket ||def_mba23_2b_2socket_ddr4 ||def_mba23_2c_2socket ||def_mba23_2c_2socket_ddr4 ||def_mba23_3a_2socket ||def_mba23_3a_2socket_ddr4 ||def_mba23_3b_2socket ||def_mba23_3c_2socket_ddr4 ||def_mba23_5b_2socket ||def_mba23_5c_2socket ||def_mba23_5d_2socket ||def_mba23_7a_2socket ||def_mba23_7b_2socket ||def_mba23_7c_2socket ||def_mba23_7a_2socket_ddr4 ||def_mba23_7b_2socket_ddr4 ||def_mba23_7c_2socket_ddr4 ||def_mba23_1c_cdimm ||def_mba23_3a_cdimm ||def_mba23_3b_cdimm ||def_mba23_3c_cdimm ||def_mba23_3a_ddr4_cdimm ||def_mba23_3b_ddr4_cdimm ||def_mba23_3c_ddr4_cdimm ||def_mba23_4a_cdimm ||def_mba23_4a_ddr4_cdimm ||def_mba23_4b_ddr4_cdimm ||def_mba23_4c_ddr4_cdimm); ## Temp defines until the code adds these attributes #--****************************************************************************** #-- MBS FIR MASK Register #--****************************************************************************** # scom 0x02011403 { # bits , scom_data ; # 8 , 0b1 ; # int_parity_error - HW244827 and HW251643 # # } #--****************************************************************************** # HW246685 : Need RCE FIR bit if NCE/SCE/MPE/MCE on 2nd try # - Want to be able to see RCE reported even if we also have chip marks or symbol marks in place. # - To enable maint fix: set MBSTR(60)=1 to see the RCE in conjunction with the other errors # - To enable mainline fix: set MBSECC(16)=1 to see the RCE in conjunction with the other errors #--****************************************************************************** # MBS01_MBSTRQ scom 0x02011655 { bits , scom_data , ATTR_FUNCTIONAL, expr; 60 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 == 1); # cfg_maint_rce_with_ce } # MBS23_MBSTRQ scom 0x02011755 { bits , scom_data , ATTR_FUNCTIONAL, expr; 60 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 == 1); # cfg_maint_rce_with_ce } # MBU.MBS.ECC0.MBSECCQ scom 0x0201144A { bits , scom_data , ATTR_FUNCTIONAL, expr; 16 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 == 1); # Report RCE on corrections } # MBU.MBS.ECC1.MBSECCQ scom 0x0201148A { bits , scom_data , ATTR_FUNCTIONAL, expr; 16 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 == 1); # Report RCE on corrections } #--****************************************************************************** # TRACE_TRCTRL_CONFIG Trace Control Configuration Register # # HW259719 - lcl_clk_gate_ctrl needs to be turned on and left on # DD2 fixed ONLY #--****************************************************************************** # MBI trace scom 0x02010C42 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:63 , 0x000C000000000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl } # MBS1 trace scom 0x02011882 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:63 , 0x000C000000000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl } # MBS2 trace scom 0x020118C2 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:63 , 0x000C000000000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl } # YCT added for Irving #--****************************************************************************** #-- MBI Configuration Register #--****************************************************************************** scom 0x000000000201080A { bits , scom_data ; 0 , 0b0 ; # MBICFGQ_FORCE_CHANNEL_FAIL 1 , 0b0 ; # MBICFGQ_REPLAY_CRC_DISABLE 2 , 0b0 ; # MBICFGQ_REPLAY_NOACK_DISABLE 3 , 0b0 ; # MBICFGQ_REPLAY_OUTOFORDER_DISABLE 4 , 0b0 ; # MBICFGQ_FORCE_LFSR_REPLAY 5 , 0b0 ; # MBICFGQ_CRC_CHECK_DISABLE 6 , 0b0 ; # MBICFGQ_ECC_CHECK_DISABLE 7 , 0b0 ; # MBICFGQ_START_FRAME_LOCK 8 , 0b0 ; # MBICFGQ_FORCE_FRTL 9 , 0b0 ; # MBICFGQ_AUTO_FRTL_DISABLE 10:16, 0b0000000 ; # MBICFGQ_MANUAL_FRTL_VALUE 17 , 0x0 ; # MBICFGQ_MANUAL_FRTL_DONE 18 , 0b0 ; # MBICFGQ_ECC_CORRECT_DISABLE 19 , 0b0 ; # MBICFGQ_SPARE1 20 , 0b0 ; # MBICFGQ_LANE_VOTING_BYPASS 21:25, 0b00000 ; # MBICFGQ_BAD_LANE_VALUE 26 , 0b0 ; # MBICFGQ_BAD_LANE_VOTING_DISABLE 27:32, 0b010010 ; # MBICFGQ_NO_FORWARD_PROGRESS_TIMEOUT_VALUE (0x12 = 18 => 2ms) 33:34, 0b00 ; # MBICFGQ_PERFORMANCE_DEGRADATION_PERCENT_SELECT 35:36, 0b00 ; # MBICFGQ_CHANNEL_INITIALIZATION_STATE_MACHINE_TIMEOUT_VALUE 37 , 0b0 ; # MBICFGQ_RESET_KEEPER 38 , 0b0 ; # MBICFGQ_FAULT_LINE_ERROR_ENABLE 39:43, 0b00000 ; # MBICFGQ_RESERVED } ###################### # temp VBU settings # ###################### # Name = MBU.MBS.ECC01 (scomdef) # MBSECCQ MBS Memory ECC Control Register (01) scom 0x0201144A { bits, scom_data , MBA0.ATTR_FUNCTIONAL, expr ; 0 , 0b1 , 1 , any ; # disable mba01 memory ecc check/correct } # Name = MBU.MBS.ECC23 (scomdef) # MBSECCQ MBS Memory ECC Control Register (23) scom 0x0201148A { bits, scom_data , MBA1.ATTR_FUNCTIONAL, expr ; 0 , 0b1 , 1 , any ; # disable MBA23 memory ecc check/correct } ###################### # MBS Configuration # ###################### # MBS OCC Idle Threshold count Regsiter # B0.C0.M00A.CEN.MBU.MBS.MBSOCCITCQ(0:63) = 0x0000000600000000 # added to match dials -MW scom 0x02011428 { scom_data ; 0x0000000600000000 ; } # Name = MBU.MBS (scomdef) # MBSCFGQ MBS Configuration Register scom 0x02011411 { bits, scom_data , expr; 0 , 0b0 , any ; # MBSCFGQ_eccbp_exit_sel 1 , 0b0 , any ; # MBSCFGQ_dram_ecc_bypass_dis } # Name = MBU.MBS (scomdef) # MBCCFGQ MBC Configuration Register scom 0x0201140F { bits, scom_data , expr; 0 , 0b0 , (L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0); # MBCCFGQ_cache_enable 0 , 0b1 , (L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0); # MBCCFGQ_cache_enable 1 , 0b0 , any ; # MBCCFGQ_cfg_dyn_whap_en 2 , 0b0 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 0) || ((L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0))); # MBCCFGQ_cleaner_enable 2 , 0b1 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 1) && ((L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0))); # MBCCFGQ_cleaner_enable 3 , 0b0 , any ; # MBCCFGQ_cache_only_enable 4 , 0b0 , any ; # MBCCFGQ_lru_dmap_en 5 , 0b0 , any ; # MBCCFGQ_lru_random_en 6 , 0b0 , any ; # MBCCFGQ_lru_single_mem_en 7 , 0b1 , any ; # MBCCFGQ_cfg_srw_delete_ue_en # SW252733 : L4 Cache UE Handling 8 , 0b0 , any ; # MBCCFGQ_srw_line_delete_next_ce_en 9 , 0b0 , any ; # MBCCFGQ_only_log_ecc_ue 10 , 0b0 , any ; # MBCCFGQ_only_log_ecc_ce 11 , 0b0 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 1); # MBCCFGQ_srw_prefetch_dis 11 , 0b1 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 0); # MBCCFGQ_srw_prefetch_dis 12 , 0b0 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 1); # MBCCFGQ_prq_prefetch_dis 12 , 0b1 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 0); # MBCCFGQ_prq_prefetch_dis 13:16 , 0xE , any ; # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 17:22 , 0x1F , any ; # MBCCFGQ_cln_wrq_tgt_alloc_0_5 23:28 , 0x7 , any ; # MBCCFGQ_cln_wr_priority_wrq_hwmark_0_5 29:34 , 0x6 , any ; # MBCCFGQ_cln_wr_priority_wrq_lwmark_0_5 35:48 , 0x1000 , any ; # MBCCFGQ_cln_wr_priority_dv_hwmark_0_13 49:62 , 0x0FC0 , any ; # MBCCFGQ_cln_wr_priority_dv_lwmark_0_13 } ######################################## #MBA Swizzle Control Register (MBAXCRMS) ######################################## # Name = MBU.MBS.ARB.MBAXCRMS (scomdef) # MBA Swizzle Control Register (MBAXCRMS) scom 0x0201140D { bits, scom_data , MBA0.ATTR_FUNCTIONAL, MBA1.ATTR_FUNCTIONAL, expr; 0:2 , 0b000 , 1 , 0 , any; # MBA01_master_rank_0_select is 0 for all cfgs 0:2 , 0b000 , 1 , 1 , any; # MBA01_master_rank_0_select is 0 for all cfgs 3:5 , 0b001 , 1 , 0 , any; # MBA01_master_rank_1_select is 1 for all cfgs 3:5 , 0b001 , 1 , 1 , any; # MBA01_master_rank_1_select is 1 for all cfgs 6:8 , 0b010 , 1 , 0 , any; # MBA01_master_rank_2_select is 2 for all cfgs 6:8 , 0b010 , 1 , 1 , any; # MBA01_master_rank_2_select is 2 for all cfgs 24:26 , 0b000 , 0 , 1 , any; # MBA23_master_rank_0_select is 0 for all cfgs 24:26 , 0b000 , 1 , 1 , any; # MBA23_master_rank_0_select is 0 for all cfgs 27:29 , 0b001 , 0 , 1 , any; # MBA23_master_rank_1_select is 1 for all cfgs 27:29 , 0b001 , 1 , 1 , any; # MBA23_master_rank_1_select is 1 for all cfgs 30:32 , 0b010 , 0 , 1 , any; # MBA23_master_rank_2_select is 2 for all cfgs 30:32 , 0b010 , 1 , 1 , any; # MBA23_master_rank_2_select is 2 for all cfgs } ######################################## # MBA address interleave bit selection # ######################################## # Name = MBU.MBS.ARB.RXLT (scomdef) # MBSXCRQ MBS Address Translate Control Register # address interleave mode scom 0x0201140A { bits, scom_data , expr; 0:4 , 0b00000 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 0) || (MBA0.ATTR_FUNCTIONAL == 0) || (MBA1.ATTR_FUNCTIONAL == 0); # no MBA interleave 0:4 , 0b10000 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 23) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # 0:4 , 0b10001 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 24) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # 0:4 , 0b10010 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 25) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # 0:4 , 0b10011 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 26) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # 0:4 , 0b10100 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 27) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # 0:4 , 0b10101 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 28) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # 0:4 , 0b10110 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 29) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # 0:4 , 0b10111 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 30) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # 0:4 , 0b11000 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 31) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # 0:4 , 0b11001 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 32) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # 5 , 0b0 , any ; # Z mode only } # Hash mode Selection # Select hash mode with most interleaving (higher hash number) # Section 5.6 in centuar workbook for hashing # MBA01 Type 1A - simplied table to hash mode 1 when both dimm configured define def_mba01_hash1_type1a = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1) || (MBA0.ATTR_EFF_IBM_TYPE[0][1] == 1)) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] != 0) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] != 0); define def_mba01_hash0_type1a = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1) || (MBA0.ATTR_EFF_IBM_TYPE[0][1] == 1)) && ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0) || (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0)); # Type 1B/5B - simplied table to hash mode 2 when both dimm configured and hash mode 1 when 1 dimm is configured define def_mba01_hash2_type1b_5b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15)) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] != 0) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] != 0); define def_mba01_hash1_type1b_5b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15)) && ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0) || (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0)); # Type 1D/5C - simplied table to hash mode 2 for all cfgs define def_mba01_hash2_type1d_5c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 16)); # Type 2A - simplied table to hash mode 1 when both dimm configured and hash mode 0 when 1 dimm is configured define def_mba01_hash1_type2a = (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] != 0) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] != 0); define def_mba01_hash0_type2a = (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5) && ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0) || (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0)); # Type 2B - simplied table to hash mode 0 for all cfgs define def_mba01_hash0_type2b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6)); # Type 3A/7A - simplied table to hash mode 1 for all cfgs define def_mba01_hash1_type3a_7a = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21)); # Type 3B/7B - simplied table to hash mode 0 for all cfgs define def_mba01_hash0_type3b_7b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22)); # Type 2C - simplied table to hash mode 0 for all cfgs define def_mba01_hash0_type2c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7)); # Type 3C/7C - simplied table to hash mode 0 for all cfgs define def_mba01_hash0_type3c_7c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23)); # MBA23 Type 1A - simplied table to hash mode 1 when both dimm configured define def_mba23_hash1_type1a = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1) || (MBA1.ATTR_EFF_IBM_TYPE[1][1] == 1)) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] != 0) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] != 0); define def_mba23_hash0_type1a = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1) || (MBA1.ATTR_EFF_IBM_TYPE[1][1] == 1)) && ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0) || (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0)); # Type 1B/5B - simplied table to hash mode 2 when both dimm configured and hash mode 1 when 1 dimm is configured define def_mba23_hash2_type1b_5b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15)) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] != 0) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] != 0); define def_mba23_hash1_type1b_5b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15)) && ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0) || (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0)); # Type 1D/5C - simplied table to hash mode 2 for all cfgs define def_mba23_hash2_type1d_5c = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 16)); # Type 2A - simplied table to hash mode 1 when both dimm configured and hash mode 0 when 1 dimm is configured define def_mba23_hash1_type2a = (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] != 0) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] != 0); define def_mba23_hash0_type2a = (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5) && ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0) || (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0)); # Type 2B - simplied table to hash mode 0 for all cfgs define def_mba23_hash0_type2b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6)); # Type 3A/7A - simplied table to hash mode 1 for all cfgs define def_mba23_hash1_type3a_7a = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21)); # Type 3B/7B - simplied table to hash mode 0 for all cfgs define def_mba23_hash0_type3b_7b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22)); # Type 2C - simplied table to hash mode 0 for all cfgs define def_mba23_hash0_type2c = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7)); # Type 3C/7C - simplied table to hash mode 0 for all cfgs define def_mba23_hash0_type3c_7c = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23)); define def_mba01_hash0_sel = (def_mba01_hash0_type1a) ||(def_mba01_hash0_type2a) ||(def_mba01_hash0_type2b) ||(def_mba01_hash0_type2c) ||(def_mba01_hash0_type3b_7b) ||(def_mba01_hash0_type3c_7c) ; define def_mba01_hash1_sel = (def_mba01_hash1_type1a) ||(def_mba01_hash1_type1b_5b) ||(def_mba01_hash1_type2a) ||(def_mba01_hash1_type3a_7a) ; define def_mba01_hash2_sel = (def_mba01_hash2_type1b_5b) ||(def_mba01_hash2_type1d_5c) ; define def_mba23_hash0_sel = (def_mba23_hash0_type1a) ||(def_mba23_hash0_type2a) ||(def_mba23_hash0_type2b) ||(def_mba23_hash0_type2c) ||(def_mba23_hash0_type3b_7b) ||(def_mba23_hash0_type3c_7c) ; define def_mba23_hash1_sel = (def_mba23_hash1_type1a) ||(def_mba23_hash1_type1b_5b) ||(def_mba23_hash1_type2a) ||(def_mba23_hash1_type3a_7a) ; define def_mba23_hash2_sel = (def_mba23_hash2_type1b_5b) ||(def_mba23_hash2_type1d_5c) ; #################################### # MBA01 address translation config # #################################### # Name = MBU.MBS.ARB.RXLT (scomdef) # MBU.MBS.ARB.RXLT.MBAXCR01Q_MBA01_CONFIG_TYPE from (edial spydef) # MBAXCR01Q MBA01 Address Translate Control Register # scom 0x0201140B { bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; 0:3 , 0b0000 , 1 , (def_mba01_nomem == 1); # MBAXCR01Q_MBA01_config_type D 0:3 , 0b0001 , 1 , (def_mba01_type1_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D 0:3 , 0b0010 , 1 , (def_mba01_type2_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D 0:3 , 0b0011 , 1 , (def_mba01_type3_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D 0:3 , 0b0100 , 1 , (def_mba01_type4_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D 0:3 , 0b0101 , 1 , (def_mba01_type5_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D 0:3 , 0b0110 , 1 , (def_mba01_type6_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D 0:3 , 0b0111 , 1 , (def_mba01_type7_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D # 0:3 , 0b1000 , 1 , (def_mba01_type8_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D # 4:5 , 0b01 , 1 , any ; # temp until ibm type is fully supported # MBAXCR01Q_MBA01_config_subtype D 4:5 , 0b00 , 1 , (def_mba01_subtype_A == 1); # MBAXCR01Q_MBA01_config_subtype D 4:5 , 0b01 , 1 , (def_mba01_subtype_B == 1); # MBAXCR01Q_MBA01_config_subtype D 4:5 , 0b10 , 1 , (def_mba01_subtype_C == 1); # MBAXCR01Q_MBA01_config_subtype D 6:7 , 0b00 , 1 , (MBA0.ATTR_EFF_DRAM_DENSITY == 2); # MBAXCR01Q_MBA01_DRAM_size D 6:7 , 0b01 , 1 , (MBA0.ATTR_EFF_DRAM_DENSITY == 4); # MBAXCR01Q_MBA01_DRAM_size D 6:7 , 0b10 , 1 , (MBA0.ATTR_EFF_DRAM_DENSITY == 8); # MBAXCR01Q_MBA01_DRAM_size D 8 , 0b0 , 1 , (def_mba01_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated == 1); # MBAXCR01Q_MBA01_Configuration D 8 , 0b1 , 1 , (def_mba01_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated == 1); # MBAXCR01Q_MBA01_Configuration D # 8 , 0b0 , 1 , (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1); # MBAXCR01Q_MBA01_Configuration D # 8 , 0b1 , 1 , (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2); # MBAXCR01Q_MBA01_Configuration D 9 , 0b1 , 1 , (MBA0.ATTR_EFF_DRAM_WIDTH == 4); # MBAXCR01Q_MBA01_DRAM_Width D 9 , 0b0 , 1 , (MBA0.ATTR_EFF_DRAM_WIDTH == 8); # MBAXCR01Q_MBA01_DRAM_Width D 10:11 , 0b00 , 1 , def_mba01_hash0_sel; # MBAXCR01Q_MBA01_Hash_Mode 10:11 , 0b01 , 1 , def_mba01_hash1_sel; # MBAXCR01Q_MBA01_Hash_Mode 10:11 , 0b10 , 1 , def_mba01_hash2_sel; # MBAXCR01Q_MBA01_Hash_Mode # 10:11 , 0b00 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 0); # MBAXCR01Q_MBA01_Hash_Mode # 10:11 , 0b01 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 1); # MBAXCR01Q_MBA01_Hash_Mode # 10:11 , 0b10 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 2); # MBAXCR01Q_MBA01_Hash_Mode 12 , 0b0 , 1 , ((ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE == 0) || ((L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0))); # MBAXCR01Q_MBA01_Interleave_Mode 12 , 0b1 , 1 , ((ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE == 1) && ((L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0))); # MBAXCR01Q_MBA01_Interleave_Mod } #################################### # MBA23 address translation config # #################################### # Name = MBU.MBS.ARB.RXLT (scomdef) # MBU.MBS.ARB.RXLT.MBAXCR01Q_MBA23_CONFIG_TYPE from (edial spydef) # MBAXCR23Q MBA23 Address Translate Control Register # scom 0x0201140C { bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; 0:3 , 0b0000 , 1 , (def_mba23_nomem == 1); # MBAXCR01Q_MBA23_config_type D 0:3 , 0b0001 , 1 , (def_mba23_type1_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D 0:3 , 0b0010 , 1 , (def_mba23_type2_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D 0:3 , 0b0011 , 1 , (def_mba23_type3_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D 0:3 , 0b0100 , 1 , (def_mba23_type4_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D 0:3 , 0b0101 , 1 , (def_mba23_type5_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D 0:3 , 0b0110 , 1 , (def_mba23_type6_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D 0:3 , 0b0111 , 1 , (def_mba23_type7_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D # 0:3 , 0b1000 , 1 , (def_mba23_type8_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D # 4:5 , 0b01 , 1 , any ;# temp until ibm type is fully supported # MBAXCR01Q_MBA23_config_subtype D 4:5 , 0b00 , 1 , (def_mba23_subtype_A == 1); # MBAXCR01Q_MBA23_config_subtype D 4:5 , 0b01 , 1 , (def_mba23_subtype_B == 1); # MBAXCR01Q_MBA23_config_subtype D 4:5 , 0b10 , 1 , (def_mba23_subtype_C == 1); # MBAXCR01Q_MBA23_config_subtype D 6:7 , 0b00 , 1 , (MBA1.ATTR_EFF_DRAM_DENSITY == 2); # MBAXCR01Q_MBA23_DRAM_size D 6:7 , 0b01 , 1 , (MBA1.ATTR_EFF_DRAM_DENSITY == 4); # MBAXCR01Q_MBA23_DRAM_size D 6:7 , 0b10 , 1 , (MBA1.ATTR_EFF_DRAM_DENSITY == 8); # MBAXCR01Q_MBA23_DRAM_size D 8 , 0b0 , 1 , (def_mba23_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated == 1); # MBAXCR01Q_MBA23_Configuration D 8 , 0b1 , 1 , (def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated == 1); # MBAXCR01Q_MBA23_Configuration D # 8 , 0b0 , 1 , (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1); # MBAXCR01Q_MBA23_Configuration D # 8 , 0b1 , 1 , (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2); # MBAXCR01Q_MBA23_Configuration D 9 , 0b1 , 1 , (MBA1.ATTR_EFF_DRAM_WIDTH == 4); # MBAXCR01Q_MBA23_DRAM_Width D 9 , 0b0 , 1 , (MBA1.ATTR_EFF_DRAM_WIDTH == 8); # MBAXCR01Q_MBA23_DRAM_Width D 10:11 , 0b00 , 1 , def_mba23_hash0_sel; # MBAXCR01Q_MBA23_Hash_Mode 10:11 , 0b01 , 1 , def_mba23_hash1_sel; # MBAXCR01Q_MBA23_Hash_Mode 10:11 , 0b10 , 1 , def_mba23_hash2_sel; # MBAXCR01Q_MBA23_Hash_Mode # 12 , 0b0 , 1 , any; # -MW match dials # MBAXCR01Q_MBA23_Interleave_Mode 12 , 0b0 , 1 , ((ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE == 0) || ((L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0))); # MBAXCR01Q_MBA23_Interleave_Mode 12 , 0b1 , 1 , ((ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE == 1) && ((L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0))); # MBAXCR01Q_MBA23_Interleave_Mode } ########################################################################################### # MBS MCBIST SETUP SECTION # ########################################################################################### ################################### # MCBIST Fixed data pattern MBA01 ################################### # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFD[0-7]Q_Q(0:63) (scomdef) # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDQ_Q(0:63) (scomdef) # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDSPQ_Q(0:63) (scomdef) scom 0x02011681 { bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; 0:63 , 0x1111111111111111, 1 , any; # Fixed data burst 0 } scom 0x02011682 { bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; 0:63 , 0x2222222222222222, 1 , any; # Fixed data burst 1 } scom 0x02011683 { bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; 0:63 , 0x3333333333333333, 1 , any; # Fixed data burst 2 } scom 0x02011684 { bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; 0:63 , 0x4444444444444444, 1 , any; # Fixed data burst 3 } scom 0x02011685 { bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; 0:63 , 0x5555555555555555, 1 , any; # Fixed data burst 4 } scom 0x02011686 { bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; 0:63 , 0x6666666666666666, 1 , any; # Fixed data burst 5 } scom 0x02011687 { bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; 0:63 , 0x7777777777777777, 1 , any; # Fixed data burst 6 } scom 0x02011688 { bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; 0:63 , 0x8888888888888888, 1 , any; # Fixed data burst 7 } scom 0x02011689 { bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; 0:63 , 0x9999999999999999, 1 , any; # Fixed data burst 0-7 ECC bits } scom 0x0201168A { bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; 0:63 , 0xAAAAAAAAAAAAAAAA, 1 , any; # Fixed data burst 0-7 SPARE bits } ################################### # MCBIST Fixed data pattern MBA23 ################################### # Name = MBA23.MBA_MCBIST.SCOMFIR.MCBFD[0-7]Q_Q(0:63) (scomdef) # Name = MBA23.MBA_MCBIST.SCOMFIR.MCBFDQ_Q(0:63) (scomdef) # Name = MBA23.MBA_MCBIST.SCOMFIR.MCBFDSPQ_Q(0:63) (scomdef) scom 0x02011781 { bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; 0:63 , 0x1111111111111111, 1 , any; # Fixed data burst 0 } scom 0x02011782 { bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; 0:63 , 0x2222222222222222, 1 , any; # Fixed data burst 1 } scom 0x02011783 { bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; 0:63 , 0x3333333333333333, 1 , any; # Fixed data burst 2 } scom 0x02011784 { bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; 0:63 , 0x4444444444444444, 1 , any; # Fixed data burst 3 } scom 0x02011785 { bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; 0:63 , 0x5555555555555555, 1 , any; # Fixed data burst 4 } scom 0x02011786 { bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; 0:63 , 0x6666666666666666, 1 , any; # Fixed data burst 5 } scom 0x02011787 { bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; 0:63 , 0x7777777777777777, 1 , any; # Fixed data burst 6 } scom 0x02011788 { bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; 0:63 , 0x8888888888888888, 1 , any; # Fixed data burst 7 } scom 0x02011789 { bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; 0:63 , 0x9999999999999999, 1 , any; # Fixed data burst 0-7 ECC bits } scom 0x0201178A { bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; 0:63 , 0xAAAAAAAAAAAAAAAA, 1 , any; # Fixed data burst 0-7 SPARE bits }