#-- $Id: mba_def.initfile,v 1.74 2015/04/13 18:33:12 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- #-- 1.74|yctschan| 4/10/15| SW302059 - turn off row hammer when ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE is 1 #-- 1.73|yctschan| 4/01/15| SW302059 - turn off row hammer #-- 1.72|yctschan| 3/24/15| Added support for 2N mode for DDR4 parts for timing parms #-- 1.71|yctschan| 2/13/15| SW294743 - Update initfile to support RCD parity error reporting #-- 1.70|yctschan|12/05/14| Updated settings for fast exit power down #-- 1.69|asaetow | 9/24/14| Force SpareCKE sync. Spare DRAM workaround. #-- 1.68|jdsloat | 4/04/14| Turned off Power controls for GA1 concerns - Turn back on at a later date #-- 1.67|tschang | 4/01/14| Adjusted the PUP Avail and SEPD/FEPD time. #-- 1.66|tschang | 3/28/14| Removed Performance enhancement for rdtag with DMI freq #-- |baysah | 3/31/14| Added def_margin_pup_fast=12 and def_margin_pup_slow=0 for Yuen with values from Randy/Anuwat #-- 1.65|tschang | 3/18/14| Fixed typos in the dly7 settings from 0001 to 01111 #-- 1.64|baysah | 3/05/14| Added MBA Power Ctrol Settings and backed out the refresh avoidance settings until spec benchmark results #-- 1.63|tschang | 3/03/14| Performance enhancement for rdtag with DMI freq, refresh avoidance and CFG_PUP_AVAIL #-- 1.62|tschang | 2/14/14| Set Safe mode throttle when ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE is 1 #-- 1.61|tschang | 2/14/14| Safe mode throttle using sys attributes ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, ATTR_MRW_MEM_THROTTLE_DENOMINATOR #-- 1.60|tschang | 2/03/14| Removed CDIMM TYPE and replace with custom dimm #-- 1.59|tschang | 1/30/14| Using VPD values for CKE maps instead of calculated values - ATTR ATTR_VPD_CKE_PRI_MAP, ATTR ATTR_VPD_CKE_PWR_MAP #-- 1.58|tschang | 1/30/14| HW278587 - if TFAW is 16, set it to 15 otherwise use the TFAW attribute value #-- 1.57|tschang | 1/22/14| DD2 enhancement - Enable Page Mode for the Read Reorder Queue - MBA_RRQ0Q(57) = 1 #-- 1.56|baysah | 1/16/14| Changed row hammer primary decrement interval from 64K DRAM clocks (3200 accesses) to 512 DRAM clocks (100K accesses) to hash group. #-- 1.55|tschang | 1/07/14| ATTR_EFF_DRAM_TFAW attribute used for TFAW timing register. #-- 1.54|tschang |11/21/13| HW271989 - updated SCOM write to do a full 64 bit write instead of a RMW #-- 1.53|tschang |11/12/13|EFF to VPD attribute update #-- 1.52|tschang |11/12/13|wrdata_dly updated with def_WLO parameter and RW_dly updated for LRDIMMS #-- 1.51|tschang |11/06/13|DD2 row hammer enhancement added with ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE attribute #-- 1.50|tschang |11/06/13|ATTR_CENTAUR_EC_ENABLE_NM_CHANGE_AFTER_SYNC is 1 for DD2 - HW245888 #-- 1.49|tschang |10/24/13|added ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT, ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT to throttle settings #-- 1.48|tschang | 9/30/13|add 10% margin to refresh check interval calculations #-- 1.47|tschang | 8/15/13| HW259719 - dd2 only fix - ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL to turn on clock gates #-- 1.46|tschang | 7/17/13|updated refresh interval and refresh check interval calculations #-- 1.45|tschang | 6/04/13|using ATTR_EFF_DRAM_RRD, etc timing parms for settings #-- setting RD ODT according to Menlo's equation #-- 1.44|tschang | 5/06/13|added 2n_mode to timing parms equations #-- 1.43|tschang | 5/01/13|def_refresh_interval optimized to avoid divide by 0 condition #-- 1.42|tschang | 5/01/13|cfg_min_domain_reduction disabled as requested by performance team #-- 1.41|tschang | 4/24/13|fixed typos for a couple type cfgs #-- 1.40|tschang | 4/24/13|fixed 1d type cfg #-- 1.39|tschang | 4/17/13|commented out maxall_min0 power controls until decision has been made for default value #-- 1.38|tschang | 4/08/13|set cfg_min_domain_reduction_enable to 1 and maxall_min0 power controls #-- 1.37|tschang | 4/04/13|ACT signal in CCS idle pattern set to 1 for DDR4 and 0 for non DDR4 #-- 1.36|tschang | 4/04/13|MBA_FARB2Q fixed rank master typo for IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C cfg #-- 1.35|tschang | 3/27/13|set trfc and refresh interval according to refresh equation #-- update wrdata_dly parm with ATTR_EFF_DRAM_AL attribute #-- 1.34|tschang | 3/26/13|wrdata_dly parm updated to detect LRDIMMs #-- 1.33|tschang | 3/12/13|RWDM_dly margin increased by 1 to match other RW dlys - HW243893 #-- 1.32|tschang | 3/12/13|Def_margin_rdtag set it to 4 - increased by 2 #-- 1.31|tschang | 3/11/13|Defined new def_margin_rdtag and set it to 2 to increase it from figtree values #-- 1.30|tschang | 3/05/13|Set def_margin2 to 0 to decrease timing parmeters for performance and added def_margin1 for RW parms #-- 1.29|tschang | 2/27/13|Set def_margin to 1 to decrease timing parmeters for performance #-- 1.28|tschang | 2/11/13|Set WR ODT start to 1 and end to 5 (HW239026) #-- Updated cfg_nm_per_slot_enabled for CDIMM cfgs #-- 1.27|tschang | 1/28/13|Set mba_cal3 register to max timeout values for periodic cal #-- 1.26|tschang | 1/23/13|Write Latency equation changed for mba_tmr0 register - define def_WL = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 1 - 7) #-- 1.25|tschang | 1/17/13|added def_margin constant to increment mba tmr0 register by the value of def_margin - current setting of margin is 2 #-- 1.24|tschang | 1/04/13|added code to detect and overrun condition with periodic cal and choose a larger timebase when that happens #-- |fixed periodic cal type to properly choose periodic cal #-- 1.23|tschang |12/18/12|changed SYS.ATTR_IS_SIMULATION ==0 to CENTAUR.ATTR_MSS_FREQ ==1400 to cause a false coniditon place holder #-- changed rdtag to be 36 for all configurations #-- 1.22|menlowuu|12/04/12|changed CCS_Mode register to set RAS, CAS, WE to high on idles #-- 1.21|tschang |11/14/12|added throttle control for n/m #-- 1.20|tschang |11/13/12|updated file for new IBM_TYPE defnitions and added MCBIST ADDR and ADDR mapping fro SCHMOO #-- 1.16|tschang |09/27/12| added partial good support for the SCOM write using ATTR_FUNCTIONAL #-- 1.15|tschang |09/18/12|update periodic cal registers bit register definitions #-- 1.14|tschang |09/11/12|update periodic cal registers #-- 1.13|tschang |09/11/12|backout periodic cal registers settings change #-- 1.12|tschang |09/10/12|added periodic cal registers settings #-- 1.11|tschang |08/20/12|added mba mcbist setup values for simple write and read test #-- 1.10|menlowuu|08/01/12|add/fixed comments in refresh section, missed a line #-- 1.10|menlowuu|08/01/12|add/fixed comments in refresh section, missed a line #-- 1.9 |menlowuu|07/30/12|add/fixed comments in refresh section #-- 1.8 |tschang |07/28/12|set refresh interval value and refresh check interval values #-- 1.4 |tschang |06/28/12|clean up define syntax and ()'s #-- 1.3 |tschang |05/08/12|moved refresh settings from mss_draminit_mc to this init file #-- 1.2 |bellows |05/03/12|Updates for working version #-- 1.1 |bellows |04/04/12|Created File In Proper Directory #-- 0.03|bellows |04/04/12|Fixed up this comment #-- 0.02|bellows |03/27/12|Removed accesses to MBA23 #-- 0.01|retter |01/13/12|Initial version #-- --------|--------|--------|-------------------------------------------------- #-------------------------------------------------------------------------------- # End of revision history #-------------------------------------------------------------------------------- #--Master list of variables that can be used in this file is at: #-- SyntaxVersion = 1 #-- ----------------------------------------------------------------------------- #--****************************************************************************** #-- ----------------------------------------------------------------------------- #-- #-- Defines #-- #-- ----------------------------------------------------------------------------- #--****************************************************************************** #-- ----------------------------------------------------------------------------- define def_equal_test = (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT32_2); # EFF_DIMM_RANKS_CONFIGED [a][b] - a=0, def_mba01 a = 1, def_mba23 # - b=0, socket0 (mrank 0:3) b = 1, socket1 (mrank 4:7)) # EFF_NUM_RANKS_PER_DIMM = total number of master and slave ranks per socket # # ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] u8[2][2] 0x80 # ATTR_EFF_MBA_POS (0=01, 1=2/3) # # ATTR_EFF_IBM_TYPE [][] 2x2 array # OLD # UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_2A = 4, TYPE_2B = 5, TYPE_2C = 6, TYPE_3A = 7, TYPE_3B = 8, TYPE_3C = 9, TYPE_4A = 10, TYPE_4B = 11, TYPE_4C = 12, # TYPE_5A = 13, TYPE_5B = 14, TYPE_5C = 15, TYPE_5D = 16, TYPE_6A = 17, TYPE_6B = 18, TYPE_6C = 19, TYPE_7A = 20, TYPE_7B = 21, TYPE_7C = 22, TYPE_8A = 23, TYPE_8B = 24, TYPE_8C = 25 # NEW ## UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_1D = 4, TYPE_2A = 5, TYPE_2B = 6, TYPE_2C = 7, TYPE_3A = 8, TYPE_3B = 9, TYPE_3C = 10, TYPE_4A = 11, TYPE_4B = 12, TYPE_4C = 13, # TYPE_5A = 14, TYPE_5B = 15, TYPE_5C = 16, TYPE_5D = 17, TYPE_6A = 18, TYPE_6B = 19, TYPE_6C = 20, TYPE_7A = 21, TYPE_7B = 22, TYPE_7C = 23, TYPE_8A = 24, TYPE_8B = 25, TYPE_8C = 26 # # ATTR_EFF_NUM_DROPS_PER_PORT # EMPTY = 0, SINGLE = 1, DUAL = 2 # # ATTR_EFF_DIMM_TYPE # CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3 # # ATTR_EFF_DRAM_DLL_PPD # SLOWEXIT = 0, FASTEXIT = 1 # # ATTR_EFF_DRAM_GEN # EMPTY = 0, DDR3 = 1, DDR4 = 2 # # CENTAUR.ATTR_MSS_FREQ = frequency # not an mba attribute will need hierachy # # ATTR_CHIP_UNIT_POS # 0 = MBA0 (mba01), 1 = MBA1 (mba23) # # ATTR_EFF_MEMCAL_INTERVAL # TARGET_TYPE_MBA_CHIPLET # Specifies the memcal interval in clocks. # uint32 # DISABLE = 0 # ATTR_EFF_ZQCAL_INTERVAL # TARGET_TYPE_MBA_CHIPLET # Specifies the zqcal interval in clocks. # uint32 # DISABLE = 0 # mba tmr0 register timings are added to the value below define def_margin1 = (1); define def_margin2 = (0); define def_margin_pup_fast = (0); define def_margin_pup_slow = (0); define def_margin_rdtag = (4); define def_no_spare = (SYS.ATTR_IS_SIMULATION==1) ; define def_has_spare = (SYS.ATTR_IS_SIMULATION==0) ; define CENTAUR = TGT1; # MBA0 (mba01) define def_1a_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 1 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); # DDR3/4 are same define def_1a_2socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 1 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)));# || (def_1b_cdimm)); # DDR3/4 are same #define def_1a_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 1 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as 1a_1socket RDIMM define def_1b_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 2 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_1b_2socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 2 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_1c_cdimm)); #define def_1b_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 2 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1A 2 socket RDIMM cfg for DDR3/4 ## 1C 1 and 2 sockets not supported define def_1c_1socket_nodt = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || def_1d_1socket); define def_1c_2socket_nodt = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || def_1d_2socket); define def_1c_1socket_odt = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_1c_2socket_odt = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); define def_1c_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1B 2 socket RDIMM cfg for DDR3/4 ## Current they is no 1D IBM type in the attribute define def_1d_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_1d_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); ## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs define def_2a_1socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_cdimm)); define def_2a_2socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_2c_cdimm) || (def_3a_cdimm)); define def_2a_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket cfg define def_2a_1socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_ddr4_cdimm)); define def_2a_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3a_ddr4_cdimm)); define def_2a_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket DDR4 cfg define def_2b_1socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2b_cdimm)); define def_2b_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); define def_2b_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket cfg define def_2b_1socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2b_ddr4_cdimm)); define def_2b_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3b_ddr4_cdimm)); define def_2b_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket DDR4 cfg # centuar spec only has DDR4 for 2C cfg define def_2c_1socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_cdimm)); define def_2c_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); define def_2c_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket cfg define def_2c_1socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_ddr4_cdimm)); define def_2c_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3c_ddr4_cdimm)); define def_2c_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket DDR4 cfg define def_3a_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_3a_2socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_4a_cdimm)); #define def_3a_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 2 socket cfg define def_3a_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1))) && (ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg define def_3a_1socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_3a_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_4a_ddr4_cdimm)); define def_3a_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1))) && (ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg define def_3b_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_3b_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); define def_3b_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg define def_3b_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg ?? define def_3c_1socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); define def_3c_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_4c_ddr4_cdimm)); define def_3c_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg define def_3c_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg define def_4a_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 11)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 11))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket cfg define def_4a_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 11)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 11))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket DDR4 cfg define def_4b_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 12)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 12))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3B 2 socket DDR4 cfg define def_4c_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 13)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 13))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3C 2 socket DDR4 cfg define def_5b_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 15)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 15))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); define def_5b_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 15)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 15))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); define def_5c_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 16)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 16))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); define def_5c_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 16)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 16))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); define def_5d_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 17)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 17))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); define def_5d_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 17)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 17))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); define def_7a_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); define def_7a_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); define def_7a_1socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); define def_7a_2socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); define def_7b_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); define def_7b_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); define def_7b_1socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); define def_7b_2socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); define def_7c_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 23)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 23))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); define def_7c_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 23)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 23))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); define def_7c_1socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 23)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 23))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); define def_7c_2socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 23)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 23))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); define def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C = ((def_1a_1socket )||(def_1a_2socket )||(def_1b_1socket )||(def_1b_2socket )||(def_1c_cdimm )||(def_1c_1socket_nodt )||(def_1c_2socket_nodt )||(def_5b_1socket )||(def_5b_2socket )||(def_5c_1socket )||(def_5c_2socket)); define def_IS7a_C4a_C3a = ((def_3a_1socket )||(def_3a_2socket )||(def_4a_cdimm )||(def_7a_1socket )||(def_7a_2socket)); define def_IS3b_IS7b = ((def_3b_1socket )||(def_3b_2socket )||(def_4b_ddr4_cdimm )||(def_7b_1socket )||(def_7b_2socket)); define def_IS7C = ((def_7c_1socket )||(def_7c_2socket)); define def_C3b = ((def_2a_1socket )||(def_2a_2socket )||(def_3a_cdimm )||(def_2b_1socket )||(def_2b_2socket )||(def_3b_cdimm)); define def_C3c = ((def_2c_1socket )||(def_2c_2socket )||(def_3c_cdimm)); define def_C3c_C4C_ddr4 = ((def_2b_1socket_ddr4)||(def_2b_2socket_ddr4)||(def_3b_ddr4_cdimm )||(def_2c_1socket_ddr4)||(def_2c_2socket_ddr4)||(def_3c_ddr4_cdimm )||(def_3c_1socket_ddr4)||(def_3c_2socket_ddr4)||(def_4c_ddr4_cdimm )||(def_7b_1socket_ddr4)||(def_7b_2socket_ddr4)||(def_7c_1socket_ddr4)||(def_7c_2socket_ddr4)); define def_C4A_ddr4 = ((def_2a_1socket_ddr4)||(def_2a_2socket_ddr4)||(def_3a_ddr4_cdimm )||(def_7a_1socket_ddr4)||(def_7a_2socket_ddr4)||(def_3a_1socket_ddr4)||(def_3a_2socket_ddr4)||(def_4a_ddr4_cdimm)); define def_IS5D = ((def_5d_1socket )||(def_5d_2socket)); # ODT Mappings define def_odt_mapping_1a = (def_1a_1socket); define def_odt_mapping_1b1dimm = (def_1b_1socket ||def_3a_1socket ||def_3a_1socket_ddr4 ||def_3b_1socket ||def_3c_1socket_ddr4); define def_odt_mapping_1b2dimm = (def_3c_2socket_ddr4 ||def_1b_2socket ||def_3a_2socket ||def_3a_2socket_ddr4 ||def_3b_2socket); #define def_odt_mapping_1bcdimm = (def_1a_2socket ||def_1b_cdimm ||def_3a_cdimm ||def_3a_ddr4_cdimm ||def_3b_cdimm ||def_3b_ddr4_cdimm ||def_3c_cdimm ||def_3c_ddr4_cdimm); define def_odt_mapping_1bcdimm = (def_1a_2socket ||def_3a_cdimm ||def_3a_ddr4_cdimm ||def_3b_cdimm ||def_3b_ddr4_cdimm ||def_3c_cdimm ||def_3c_ddr4_cdimm); define def_odt_mapping_1c2dimm = (def_1c_2socket_odt); define def_odt_mapping_1c1dimm = (def_1c_1socket_odt); define def_odt_mapping_1ccdimm = (def_1c_cdimm ||def_4a_cdimm ||def_4a_ddr4_cdimm ||def_4b_ddr4_cdimm ||def_4c_ddr4_cdimm); define def_odt_mapping_1dx82dimm = (def_1d_2socket); define def_odt_mapping_1dx4 = (def_1d_1socket); define def_odt_mapping_2abc = (def_2a_1socket ||def_2a_2socket ||def_2a_1socket_ddr4 ||def_2a_2socket_ddr4 ||def_2a_cdimm ||def_2a_ddr4_cdimm ||def_2b_1socket ||def_2b_2socket ||def_2b_1socket_ddr4 ||def_2b_2socket_ddr4 ||def_2b_cdimm ||def_2b_ddr4_cdimm ||def_2c_1socket ||def_2c_2socket ||def_2c_1socket_ddr4 ||def_2c_2socket_ddr4 ||def_2c_ddr4_cdimm); define def_odt_mapping_56781lrdm = (def_5b_1socket ||def_5c_1socket ||def_7a_1socket ||def_7a_1socket_ddr4 ||def_7b_1socket ||def_7b_1socket_ddr4 ||def_7c_1socket ||def_7c_1socket_ddr4); define def_odt_mapping_56782lrdm = (def_5b_2socket ||def_5c_2socket ||def_7a_2socket ||def_7a_2socket_ddr4 ||def_7b_2socket ||def_7b_2socket_ddr4 ||def_7c_2socket ||def_7c_2socket_ddr4); define def_odt_mapping_5d1dimm = (def_5d_1socket); define def_odt_mapping_5d2dimm = (def_5d_2socket); #gdial std_size ( MBA_SRQ.mba_tmr1q_cfg_tfaw, MBA_SRQ.pc.MBAREF0Q_cfg_trfc, MBA_SRQ.pc.MBAREF0Q_cfg_refr_tsv_stack, MBA_SRQ.pc.MBARPC0Q_cfg_pup_pdn, MBA_SRQ.pc.MBARPC0Q_cfg_pdn_pup, MBA_SRQ.pc.MBARPC0Q_cfg_pup_avail, MBA_SRQ.mba_tmr0q_RRSMSR_dly , MBA_SRQ.mba_tmr0q_RRSMDR_dly, MBA_SRQ.mba_tmr0q_WWSMSR_dly, MBA_SRQ.mba_tmr0q_WWSMDR_dly , MBA_SRQ.MBA_TMR0Q_Trrd, MBA_SRQ.srqdbg.cfg_std_size_id)= define def_1066_2gb = ((CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1066_4gb = ((CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1066_8gb = ((CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1066_2gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1066_4gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1066_8gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1333_2gb = ((CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1333_4gb = ((CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1333_8gb = ((CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1600_2gb = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1600_4gb = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1600_8gb = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1866_2gb = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1866_4gb = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1866_8gb = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1333_2gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1333_4gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1333_8gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1600_2gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1600_4gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1600_8gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1866_2gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1866_4gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1866_8gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); define def_1600_2gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_1600_4gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_1600_8gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_1866_2gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_1866_4gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_1866_8gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_2133_2gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_2133_4gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_2133_8gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_2400_2gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_2400_4gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_2400_8gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_1600_2gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_1600_4gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_1600_8gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_1866_2gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_1866_4gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_1866_8gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_2133_2gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_2133_4gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_2133_8gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_2400_2gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_2400_4gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); define def_2400_8gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); #gdial std_timming ( mba_tmr0q_RRDM_dly, mba_tmr0q_RWSMSR_dly, mba_tmr0q_RWSMDR_dly, mba_tmr0q_RWDM_dly, mba_tmr0q_WRSMSR_dly, mba_tmr0q_WRSMDR_dly, mba_tmr0q_WRDM_dly, mba_tmr0q_WWDM_dly, mba_tmr0q_RROP_dly, mba_tmr0q_WWOP_dly, mba_tmr1q_RRSBG_dly, MBA_TMR1Q_WRSBG_dly, mba_tmr1q_cfg_trap, mba_tmr1q_cfg_twap, mba_dsm0q_cfg_rdtag_dly, mba_dsm0q_cfg_wrdata_dly, mba_dsm0q_cfg_wrdone_dly, mba_dsm0q_CFG_RODT_start_dly, mba_dsm0q_CFG_RODT_end_dly, mba_dsm0q_CFG_RODT_BC4_END_DLY, mba_dsm0q_CFG_WODT_start_dly, mba_dsm0q_CFG_WODT_end_dly, mba_dsm0q_CFG_WODT_BC4_END_DLY, srqdbg.cfg_std_timing_id)= define def_ddr3_1066_6_6_6 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1066_6_6_6R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr3_1066_6_6_6_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1066_6_6_6_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1066_6_6_6_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1066_6_6_6_group = ((def_ddr3_1066_6_6_6 )||( def_ddr3_1066_6_6_6_2N )||( def_ddr3_1066_6_6_6R )||( def_ddr3_1066_6_6_6_LR )||( def_ddr3_1066_6_6_6_L2)); define def_ddr3_1066_7_7_7 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1066_7_7_7R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr3_1066_7_7_7_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1066_7_7_7_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1066_7_7_7_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1066_7_7_7_group = ((def_ddr3_1066_7_7_7 )||( def_ddr3_1066_7_7_7_2N )||( def_ddr3_1066_7_7_7R )||( def_ddr3_1066_7_7_7_LR )||( def_ddr3_1066_7_7_7_L2)); define def_ddr3_1066_8_8_8 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1066_8_8_8R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr3_1066_8_8_8_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1066_8_8_8_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1066_8_8_8_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1066_8_8_8_group = ((def_ddr3_1066_8_8_8 )||( def_ddr3_1066_8_8_8_2N )||( def_ddr3_1066_8_8_8R )||( def_ddr3_1066_8_8_8_LR )||( def_ddr3_1066_8_8_8_L2)); define def_ddr3_1333_8_8_8 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1333_8_8_8R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr3_1333_8_8_8_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1333_8_8_8_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1333_8_8_8_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1333_9_9_9 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1333_9_9_9R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr3_1333_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1333_9_9_9_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1333_9_9_9_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1600_10_10_10 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1600_10_10_10R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr3_1600_10_10_10_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1600_10_10_10_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1600_10_10_10_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1600_11_11_11 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1600_11_11_11R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr3_1600_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1600_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1600_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1600_9_9_9 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1600_9_9_9R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr3_1600_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1600_9_9_9_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1600_9_9_9_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1866_11_11_11 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1866_11_11_11R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr3_1866_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1866_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1866_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1866_12_12_12 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1866_12_12_12R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr3_1866_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr3_1866_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr3_1866_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); # DDR4 1600 define def_ddr4_1600_9_9_9 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); define def_ddr4_1600_9_9_9R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr4_1600_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr4_1600_9_9_9_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr4_1600_9_9_9_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr4_1600_10_10_10 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); define def_ddr4_1600_10_10_10R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr4_1600_10_10_10_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr4_1600_10_10_10_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr4_1600_10_10_10_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr4_1600_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); define def_ddr4_1600_11_11_11R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr4_1600_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr4_1600_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr4_1600_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr4_1600_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); define def_ddr4_1600_12_12_12R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr4_1600_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr4_1600_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr4_1600_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); # DDR4 1866 define def_ddr4_1866_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); define def_ddr4_1866_11_11_11R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr4_1866_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr4_1866_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr4_1866_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr4_1866_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); define def_ddr4_1866_12_12_12R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr4_1866_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr4_1866_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr4_1866_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr4_1866_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); define def_ddr4_1866_13_13_13R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); define def_ddr4_1866_13_13_13_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); define def_ddr4_1866_13_13_13_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); define def_ddr4_1866_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); # DDR4 2133 12 -13 - not supported #define def_ddr4_2133_12_12_12 = 0; #define def_ddr4_2133_12_12_12R = 0; #define def_ddr4_2133_12_12_12_2N = 0; #define def_ddr4_2133_12_12_12_L2 = 0; #define def_ddr4_2133_12_12_12_LR = 0; #define def_ddr4_2133_13_13_13 = 0; #define def_ddr4_2133_13_13_13R = 0; #define def_ddr4_2133_13_13_13_2N = 0; #define def_ddr4_2133_13_13_13_L2 = 0; #define def_ddr4_2133_13_13_13_LR = 0; define def_ddr4_2133_12_12_12 = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2133_12_12_12R = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2133_12_12_12_2N = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2133_12_12_12_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2133_12_12_12_LR = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2133_13_13_13 = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2133_13_13_13R = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2133_13_13_13_2N = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2133_13_13_13_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2133_13_13_13_LR = (CENTAUR.ATTR_MSS_FREQ == 1400); #define def_ddr4_2133_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); #define def_ddr4_2133_12_12_12R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); #define def_ddr4_2133_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_2133_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); #define def_ddr4_2133_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); #define def_ddr4_2133_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); #define def_ddr4_2133_13_13_13R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); #define def_ddr4_2133_13_13_13_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_2133_13_13_13_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); #define def_ddr4_2133_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); # DDR4 2400 13-14 not supported #define def_ddr4_2400_13_13_13 = 0; #define def_ddr4_2400_13_13_13R = 0; #define def_ddr4_2400_13_13_13_2N = 0; #define def_ddr4_2400_13_13_13_L2 = 0; #define def_ddr4_2400_13_13_13_LR = 0; #define def_ddr4_2400_14_14_14 = 0; #define def_ddr4_2400_14_14_14R = 0; #define def_ddr4_2400_14_14_14_2N = 0; #define def_ddr4_2400_14_14_14_L2 = 0; #define def_ddr4_2400_14_14_14_LR = 0; define def_ddr4_2400_13_13_13 = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2400_13_13_13R = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2400_13_13_13_2N = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2400_13_13_13_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2400_13_13_13_LR = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2400_14_14_14 = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2400_14_14_14R = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2400_14_14_14_2N = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2400_14_14_14_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400); define def_ddr4_2400_14_14_14_LR = (CENTAUR.ATTR_MSS_FREQ == 1400); #define def_ddr4_2400_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); #define def_ddr4_2400_13_13_13R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); #define def_ddr4_2400_13_13_13_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_2400_13_13_13_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); #define def_ddr4_2400_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); #define def_ddr4_2400_14_14_14 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); #define def_ddr4_2400_14_14_14R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); #define def_ddr4_2400_14_14_14_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_2400_14_14_14_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); #define def_ddr4_2400_14_14_14_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); #define def_ddr4_1600_10_10_10 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr3_1600_10_10_10R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); #define def_ddr4_1600_10_10_10_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_1600_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_1600_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_1600_9_9_9 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_1600_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_1866_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_1866_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_1866_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_1866_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_2133_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_2133_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_2133_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_2400_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); #define def_ddr4_2400_14_14_14 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); # new 7,8,9 define def_mba_tmr0q_RW_dlys7 = ((def_ddr3_1066_6_6_6 )||( def_ddr3_1066_6_6_6_2N )||( def_ddr3_1066_6_6_6R )||( def_ddr4_1600_9_9_9 )||(def_ddr4_1600_9_9_9_2N )||(def_ddr4_1600_9_9_9R)); define def_mba_tmr0q_RW_dlys8 = ((def_ddr3_1066_7_7_7 )||( def_ddr3_1066_7_7_7_2N )||( def_ddr3_1066_7_7_7R )||( def_ddr3_1333_8_8_8 )||(def_ddr3_1600_9_9_9 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1600_9_9_9_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1600_9_9_9R )||(def_ddr4_1600_10_10_10 )||(def_ddr4_1600_10_10_10_2N )||(def_ddr4_1600_10_10_10R)); define def_mba_tmr0q_RW_dlys9 = ((def_ddr3_1066_8_8_8 )||( def_ddr3_1066_8_8_8_2N )||( def_ddr3_1066_8_8_8R )||( def_ddr3_1333_9_9_9 )||(def_ddr3_1600_10_10_10 )||(def_ddr3_1333_9_9_9_2N )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1333_9_9_9R )||(def_ddr3_1600_10_10_10R )||(def_ddr4_1600_11_11_11 )||(def_ddr4_1866_11_11_11 )||(def_ddr4_2133_12_12_12 )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_2133_12_12_12_2N )||(def_ddr4_1600_11_11_11R )||(def_ddr4_1866_11_11_11R )||(def_ddr4_2133_12_12_12R )); define def_mba_tmr0q_RW_dlys10 = ((def_ddr4_1600_12_12_12)||(def_ddr4_1600_12_12_12_2N)||(def_ddr4_1600_12_12_12R)||(def_ddr4_2133_13_13_13R)||(def_ddr4_2133_13_13_13_2N )||(def_ddr4_2133_13_13_13 )||(def_ddr3_1600_11_11_11 )||(def_ddr3_1866_11_11_11 )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1866_11_11_11_2N )||(def_ddr3_1600_11_11_11R )||(def_ddr3_1866_11_11_11R )||(def_ddr4_1866_12_12_12 )||(def_ddr4_2400_13_13_13 )||(def_ddr4_1866_12_12_12_2N )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_1866_12_12_12R )||(def_ddr4_2400_13_13_13R)); define def_mba_tmr0q_RW_dlys11 = ((def_ddr4_1866_13_13_13)||(def_ddr4_1866_13_13_13_2N)||(def_ddr4_1866_13_13_13R)||(def_ddr3_1066_6_6_6_L2)||( def_ddr3_1066_6_6_6_LR )||(def_ddr3_1866_12_12_12 )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1866_12_12_12R )||(def_ddr4_2400_14_14_14 )||(def_ddr4_2400_14_14_14_2N )||(def_ddr4_2400_14_14_14R )||(def_ddr4_1600_9_9_9_LR )||(def_ddr4_1600_9_9_9_L2)); define def_mba_tmr0q_RW_dlys12 = (( def_ddr3_1066_7_7_7_L2)||( def_ddr3_1066_7_7_7_LR )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1600_9_9_9_LR )||(def_ddr3_1333_8_8_8_L2 )||(def_ddr3_1600_9_9_9_L2 )||(def_ddr4_1600_10_10_10_LR )||(def_ddr4_1600_10_10_10_L2)); # change RW_dly for LRDIMMs define def_mba_tmr0q_RW_dlys13 = (( def_ddr3_1066_8_8_8_L2)||( def_ddr3_1066_8_8_8_LR )||(def_ddr3_1333_9_9_9_L2 )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr3_1866_11_11_11_L2 )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_2133_12_12_12_LR )||(def_ddr4_1600_11_11_11_L2 )||(def_ddr4_1866_11_11_11_L2 )||(def_ddr4_2133_12_12_12_L2 )); define def_mba_tmr0q_RW_dlys14 = ((def_ddr4_1600_12_12_12_LR)||(def_ddr4_1600_12_12_12_L2)||(def_ddr4_2133_13_13_13_L2)||(def_ddr4_2133_13_13_13_LR )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1600_11_11_11_L2 )||(def_ddr3_1866_12_12_12_L2 )||(def_ddr4_1866_12_12_12_LR )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_1866_12_12_12_L2 )||(def_ddr4_2400_13_13_13_L2)||(def_ddr3_1333_9_9_9_LR )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1866_11_11_11_LR )); define def_mba_tmr0q_RW_dlys15 = ((def_ddr4_1866_13_13_13_LR)||(def_ddr4_1866_13_13_13_L2)||(def_ddr4_2400_14_14_14_LR )||(def_ddr4_2400_14_14_14_L2)); #new 19,20,21 define def_mba_tmr0q_WRSM_dlys19 = (def_ddr3_1066_6_6_6_group); define def_mba_tmr0q_WRSM_dlys20 = (def_ddr3_1066_7_7_7_group); define def_mba_tmr0q_WRSM_dlys21 = (def_ddr3_1066_8_8_8_group); define def_mba_tmr0q_WRSM_dlys23 = ((def_ddr3_1333_8_8_8 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1333_8_8_8_L2)); define def_mba_tmr0q_WRSM_dlys24 = ((def_ddr3_1333_9_9_9 )||(def_ddr3_1333_9_9_9_2N )||(def_ddr3_1333_9_9_9R )||(def_ddr3_1333_9_9_9_LR )||(def_ddr3_1333_9_9_9_L2 )); define def_mba_tmr0q_WRSM_dlys25 = ((def_ddr4_1600_9_9_9 )||(def_ddr4_1600_9_9_9_2N )||(def_ddr4_1600_9_9_9R )||(def_ddr4_1600_9_9_9_LR )||(def_ddr4_1600_9_9_9_L2 )); define def_mba_tmr0q_WRSM_dlys26 = ((def_ddr3_1600_9_9_9 )||(def_ddr3_1600_9_9_9_2N )||(def_ddr3_1600_9_9_9R )||(def_ddr3_1600_9_9_9_LR )||(def_ddr3_1600_9_9_9_L2 )||(def_ddr4_1600_10_10_10 )||(def_ddr4_1600_10_10_10_2N )||(def_ddr4_1600_10_10_10R )||(def_ddr4_1600_10_10_10_LR )||(def_ddr4_1600_10_10_10_L2 )); define def_mba_tmr0q_WRSM_dlys27 = ((def_ddr3_1600_10_10_10 )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1600_10_10_10R )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr4_1600_11_11_11 )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1600_11_11_11R )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1600_11_11_11_L2 )); define def_mba_tmr0q_WRSM_dlys28 = (def_ddr4_1600_12_12_12 ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2 || (def_ddr3_1600_11_11_11 )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1600_11_11_11R )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1600_11_11_11_L2 )||(def_ddr4_1866_11_11_11 )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_1866_11_11_11R )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_1866_11_11_11_L2 )); define def_mba_tmr0q_WRSM_dlys29 = ((def_ddr4_1866_12_12_12 )||(def_ddr4_1866_12_12_12_2N )||(def_ddr4_1866_12_12_12R )||(def_ddr4_1866_12_12_12_LR )||(def_ddr4_1866_12_12_12_L2 )); define def_mba_tmr0q_WRSM_dlys30 = ((def_ddr4_2133_12_12_12 )||(def_ddr4_2133_12_12_12_2N )||(def_ddr4_2133_12_12_12R )||(def_ddr4_2133_12_12_12_LR )||(def_ddr4_2133_12_12_12_L2 )); define def_mba_tmr0q_WRSM_dlys31 = ((def_ddr3_1866_11_11_11 )||(def_ddr3_1866_11_11_11_2N )||(def_ddr3_1866_11_11_11R )||(def_ddr3_1866_11_11_11_LR )||(def_ddr3_1866_11_11_11_L2 )||(def_ddr4_2133_13_13_13 )||(def_ddr4_2133_13_13_13_2N )||(def_ddr4_2133_13_13_13R )||(def_ddr4_2133_13_13_13_LR )||(def_ddr4_2133_13_13_13_L2 )); define def_mba_tmr0q_WRSM_dlys32 = (def_ddr4_1866_13_13_13 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2 || (def_ddr3_1866_12_12_12 )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1866_12_12_12R )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1866_12_12_12_L2 )||(def_ddr4_2400_13_13_13 )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_2400_13_13_13R )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_2400_13_13_13_L2 )); define def_mba_tmr0q_WRSM_dlys33 = ((def_ddr4_2400_14_14_14 )||(def_ddr4_2400_14_14_14_2N )||(def_ddr4_2400_14_14_14R )||(def_ddr4_2400_14_14_14_LR )||(def_ddr4_2400_14_14_14_L2 )); #new 7,6,5 define def_mba_tmr0q_WRDM_dlys4 = (def_ddr4_1600_12_12_12 ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2 || (def_ddr3_1600_11_11_11 )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1600_11_11_11R )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1600_11_11_11_L2)); define def_mba_tmr0q_WRDM_dlys5 = (def_ddr4_1866_13_13_13 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2 || (def_ddr3_1066_8_8_8_group )||(def_ddr3_1333_9_9_9 )||(def_ddr3_1600_10_10_10 )||(def_ddr3_1866_12_12_12 )||(def_ddr3_1333_9_9_9_2N )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1333_9_9_9R )||(def_ddr3_1600_10_10_10R )||(def_ddr3_1866_12_12_12R )||(def_ddr3_1333_9_9_9_LR )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1333_9_9_9_L2 )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr3_1866_12_12_12_L2 )||(def_ddr4_1600_11_11_11 )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1600_11_11_11R )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1600_11_11_11_L2)); define def_mba_tmr0q_WRDM_dlys6 = ((def_ddr3_1066_7_7_7_group )||(def_ddr3_1333_8_8_8 )||(def_ddr3_1600_9_9_9 )||(def_ddr3_1866_11_11_11 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1600_9_9_9_2N )||(def_ddr3_1866_11_11_11_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1600_9_9_9R )||(def_ddr3_1866_11_11_11R )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1600_9_9_9_LR )||(def_ddr3_1866_11_11_11_LR )||(def_ddr3_1333_8_8_8_L2 )||(def_ddr3_1600_9_9_9_L2 )||(def_ddr3_1866_11_11_11_L2 )||(def_ddr4_1600_10_10_10 )||(def_ddr4_1866_12_12_12 )||(def_ddr4_2133_13_13_13 )||(def_ddr4_1600_10_10_10_2N )||(def_ddr4_1866_12_12_12_2N )||(def_ddr4_2133_13_13_13_2N )||(def_ddr4_1600_10_10_10R )||(def_ddr4_1866_12_12_12R )||(def_ddr4_2133_13_13_13R )||(def_ddr4_1600_10_10_10_LR )||(def_ddr4_1866_12_12_12_LR )||(def_ddr4_2133_13_13_13_LR )||(def_ddr4_1600_10_10_10_L2 )||(def_ddr4_1866_12_12_12_L2 )||(def_ddr4_2133_13_13_13_L2)); define def_mba_tmr0q_WRDM_dlys7 = ((def_ddr3_1066_6_6_6_group )||(def_ddr4_1600_9_9_9 )||(def_ddr4_1866_11_11_11 )||(def_ddr4_2133_12_12_12 )||(def_ddr4_2400_14_14_14 )||(def_ddr4_1600_9_9_9_2N )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_2133_12_12_12_2N )||(def_ddr4_2400_14_14_14_2N )||(def_ddr4_1600_9_9_9R )||(def_ddr4_1866_11_11_11R )||(def_ddr4_2133_12_12_12R )||(def_ddr4_2400_14_14_14R )||(def_ddr4_1600_9_9_9_LR )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_2133_12_12_12_LR )||(def_ddr4_2400_14_14_14_LR )||(def_ddr4_1600_9_9_9_L2 )||(def_ddr4_1866_11_11_11_L2 )||(def_ddr4_2133_12_12_12_L2 )||(def_ddr4_2400_14_14_14_L2)); define def_mba_tmr0q_WRDM_dlys8 = ((def_ddr4_2400_13_13_13 )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_2400_13_13_13R )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_2400_13_13_13_L2)); #new all 0 define def_mba_tmr1q_RRSBG_dlys0 = ((def_ddr3_1066_6_6_6_group )||( def_ddr3_1066_7_7_7_group )||( def_ddr3_1066_8_8_8_group )||( def_ddr3_1600_11_11_11 )||( def_ddr3_1600_11_11_11_2N )||( def_ddr3_1600_11_11_11R )||( def_ddr3_1600_11_11_11_LR )||( def_ddr3_1600_11_11_11_L2 )||( def_ddr3_1333_9_9_9 )||( def_ddr3_1600_10_10_10 )||( def_ddr3_1333_9_9_9_2N )||( def_ddr3_1600_10_10_10_2N )||( def_ddr3_1333_9_9_9R )||( def_ddr3_1600_10_10_10R )||( def_ddr3_1333_9_9_9_LR )||( def_ddr3_1600_10_10_10_LR )||( def_ddr3_1333_9_9_9_L2 )||( def_ddr3_1600_10_10_10_L2 )||( def_ddr3_1333_8_8_8 )||( def_ddr3_1600_9_9_9 )||( def_ddr3_1333_8_8_8_2N )||( def_ddr3_1600_9_9_9_2N )||( def_ddr3_1333_8_8_8R )||( def_ddr3_1600_9_9_9R )||( def_ddr3_1333_8_8_8_LR )||( def_ddr3_1600_9_9_9_LR )||( def_ddr3_1333_8_8_8_L2 )||( def_ddr3_1600_9_9_9_L2 )||( def_ddr3_1866_12_12_12 )||( def_ddr3_1866_12_12_12_2N )||( def_ddr3_1866_12_12_12R )||( def_ddr3_1866_12_12_12_LR )||( def_ddr3_1866_12_12_12_L2 )||( def_ddr3_1866_11_11_11 )||( def_ddr3_1866_11_11_11_2N )||( def_ddr3_1866_11_11_11R )||( def_ddr3_1866_11_11_11_LR )||( def_ddr3_1866_11_11_11_L2)); define def_mba_tmr1q_RRSBG_dlys5 = (def_ddr4_1600_12_12_12 ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2 ||def_ddr4_1866_13_13_13 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2 || (def_ddr4_1600_11_11_11 )||( def_ddr4_1600_11_11_11_2N )||( def_ddr4_1600_11_11_11R )||( def_ddr4_1600_11_11_11_LR )||( def_ddr4_1600_11_11_11_L2 )||( def_ddr4_1600_10_10_10 )||( def_ddr4_1600_10_10_10_2N )||( def_ddr4_1600_10_10_10R )||( def_ddr4_1600_10_10_10_LR )||( def_ddr4_1600_10_10_10_L2 )||( def_ddr4_1600_9_9_9 )||( def_ddr4_1600_9_9_9_2N )||( def_ddr4_1600_9_9_9R )||( def_ddr4_1600_9_9_9_LR )||( def_ddr4_1600_9_9_9_L2 )||( def_ddr4_1866_12_12_12 )||( def_ddr4_1866_12_12_12_2N )||( def_ddr4_1866_12_12_12R )||( def_ddr4_1866_12_12_12_LR )||( def_ddr4_1866_12_12_12_L2 )||( def_ddr4_1866_11_11_11 )||( def_ddr4_1866_11_11_11_2N )||( def_ddr4_1866_11_11_11R )||( def_ddr4_1866_11_11_11_LR )||( def_ddr4_1866_11_11_11_L2)); define def_mba_tmr1q_RRSBG_dlys6 = ((def_ddr4_2133_13_13_13 )||( def_ddr4_2133_13_13_13_2N )||( def_ddr4_2133_13_13_13R )||( def_ddr4_2133_13_13_13_LR )||( def_ddr4_2133_13_13_13_L2 )||( def_ddr4_2133_12_12_12 )||( def_ddr4_2133_12_12_12_2N )||( def_ddr4_2133_12_12_12R )||( def_ddr4_2133_12_12_12_LR )||( def_ddr4_2133_12_12_12_L2 )||( def_ddr4_2400_14_14_14 )||( def_ddr4_2400_14_14_14_2N )||( def_ddr4_2400_14_14_14R )||( def_ddr4_2400_14_14_14_LR )||( def_ddr4_2400_14_14_14_L2 )||( def_ddr4_2400_13_13_13 )||( def_ddr4_2400_13_13_13_2N )||( def_ddr4_2400_13_13_13R )||( def_ddr4_2400_13_13_13_LR )||( def_ddr4_2400_13_13_13_L2)); #new all 0 define def_mba_tmr1q_WRSBG_dlys0 = ((def_ddr3_1066_6_6_6_group )||( def_ddr3_1066_7_7_7_group )||( def_ddr3_1066_8_8_8_group )||( def_ddr3_1333_8_8_8 )||( def_ddr3_1333_9_9_9 )||( def_ddr3_1600_9_9_9 )||( def_ddr3_1600_10_10_10 )||( def_ddr3_1600_11_11_11 )||( def_ddr3_1866_11_11_11 )||( def_ddr3_1866_12_12_12 )||( def_ddr3_1333_8_8_8_2N )||( def_ddr3_1333_9_9_9_2N )||( def_ddr3_1600_9_9_9_2N )||( def_ddr3_1600_10_10_10_2N )||( def_ddr3_1600_11_11_11_2N )||( def_ddr3_1866_11_11_11_2N )||( def_ddr3_1866_12_12_12_2N )||( def_ddr3_1333_8_8_8R )||( def_ddr3_1333_9_9_9R )||( def_ddr3_1600_9_9_9R )||( def_ddr3_1600_10_10_10R )||( def_ddr3_1600_11_11_11R )||( def_ddr3_1866_11_11_11R )||( def_ddr3_1866_12_12_12R )||( def_ddr3_1333_8_8_8_LR )||( def_ddr3_1333_9_9_9_LR )||( def_ddr3_1600_9_9_9_LR )||( def_ddr3_1600_10_10_10_LR )||( def_ddr3_1600_11_11_11_LR )||( def_ddr3_1866_11_11_11_LR )||( def_ddr3_1866_12_12_12_LR )||( def_ddr3_1333_8_8_8_L2 )||( def_ddr3_1333_9_9_9_L2 )||( def_ddr3_1600_9_9_9_L2 )||( def_ddr3_1600_10_10_10_L2 )||( def_ddr3_1600_11_11_11_L2 )||( def_ddr3_1866_11_11_11_L2 )||( def_ddr3_1866_12_12_12_L2)); define def_mba_tmr1q_WRSBG_dlys26 = ((def_ddr4_1600_9_9_9 )||( def_ddr4_1600_9_9_9_2N )||( def_ddr4_1600_9_9_9R )||( def_ddr4_1600_9_9_9_LR )||( def_ddr4_1600_9_9_9_L2)); define def_mba_tmr1q_WRSBG_dlys27 = ((def_ddr4_1600_10_10_10 )||( def_ddr4_1600_10_10_10_2N )||( def_ddr4_1600_10_10_10R )||( def_ddr4_1600_10_10_10_LR )||( def_ddr4_1600_10_10_10_L2)); define def_mba_tmr1q_WRSBG_dlys28 = ((def_ddr4_1600_11_11_11 )||( def_ddr4_1600_11_11_11_2N )||( def_ddr4_1600_11_11_11R )||( def_ddr4_1600_11_11_11_LR )||( def_ddr4_1600_11_11_11_L2)); define def_mba_tmr1q_WRSBG_dlys29 = (def_ddr4_1600_12_12_12 ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2 ); define def_mba_tmr1q_WRSBG_dlys30 = ((def_ddr4_1866_11_11_11 )||( def_ddr4_1866_11_11_11_2N )||( def_ddr4_1866_11_11_11R )||( def_ddr4_1866_11_11_11_LR )||( def_ddr4_1866_11_11_11_L2)); define def_mba_tmr1q_WRSBG_dlys31 = ((def_ddr4_1866_12_12_12 )||( def_ddr4_1866_12_12_12_2N )||( def_ddr4_1866_12_12_12R )||( def_ddr4_1866_12_12_12_LR )||( def_ddr4_1866_12_12_12_L2)); #define def_mba_tmr1q_WRSBG_dlys32 = (def_ddr4_1866_13_13_13 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2 ); #define def_mba_tmr1q_WRSBG_dlys33 = ((def_ddr4_2133_12_12_12 )||( def_ddr4_2133_12_12_12_2N )||( def_ddr4_2133_12_12_12R )||( def_ddr4_2133_12_12_12_LR )||( def_ddr4_2133_12_12_12_L2)); #define def_mba_tmr1q_WRSBG_dlys34 = ((def_ddr4_2133_13_13_13 )||( def_ddr4_2133_13_13_13_2N )||( def_ddr4_2133_13_13_13R )||( def_ddr4_2133_13_13_13_LR )||( def_ddr4_2133_13_13_13_L2)); #define def_mba_tmr1q_WRSBG_dlys36 = ((def_ddr4_2400_13_13_13 )||( def_ddr4_2400_13_13_13_2N )||( def_ddr4_2400_13_13_13R )||( def_ddr4_2400_13_13_13_LR )||( def_ddr4_2400_13_13_13_L2)); #define def_mba_tmr1q_WRSBG_dlys37 = ((def_ddr4_2400_14_14_14 )||( def_ddr4_2400_14_14_14_2N )||( def_ddr4_2400_14_14_14R )||( def_ddr4_2400_14_14_14_LR )||( def_ddr4_2400_14_14_14_L2)); #new 26,27,28 define def_mba_tmr1q_cfg_trap26 = ((def_ddr3_1066_6_6_6_group )||(def_ddr3_1333_8_8_8 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1333_8_8_8_L2)); define def_mba_tmr1q_cfg_trap27 = ((def_ddr3_1066_7_7_7_group )||(def_ddr3_1333_8_8_8 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1333_8_8_8_L2)); define def_mba_tmr1q_cfg_trap28 = ((def_ddr3_1066_8_8_8_group )||(def_ddr3_1333_8_8_8 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1333_8_8_8_L2)); define def_mba_tmr1q_cfg_trap32 = ((def_ddr3_1333_8_8_8 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1333_8_8_8_L2)); define def_mba_tmr1q_cfg_trap33 = ((def_ddr3_1333_9_9_9 )||(def_ddr3_1333_9_9_9_2N )||(def_ddr3_1333_9_9_9R )||(def_ddr3_1333_9_9_9_LR )||(def_ddr3_1333_9_9_9_L2)); define def_mba_tmr1q_cfg_trap37 = ((def_ddr3_1600_9_9_9 )||(def_ddr3_1600_9_9_9_2N )||(def_ddr3_1600_9_9_9R )||(def_ddr3_1600_9_9_9_LR )||(def_ddr3_1600_9_9_9_L2 )||(def_ddr4_1600_9_9_9 )||(def_ddr4_1600_9_9_9_2N )||(def_ddr4_1600_9_9_9R )||(def_ddr4_1600_9_9_9_LR )||(def_ddr4_1600_9_9_9_L2)); define def_mba_tmr1q_cfg_trap38 = ((def_ddr3_1600_10_10_10 )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1600_10_10_10R )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr4_1600_10_10_10 )||(def_ddr4_1600_10_10_10_2N )||(def_ddr4_1600_10_10_10R )||(def_ddr4_1600_10_10_10_LR )||(def_ddr4_1600_10_10_10_L2)); define def_mba_tmr1q_cfg_trap39 = ((def_ddr3_1600_11_11_11 )||(def_ddr3_1866_11_11_11 )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1866_11_11_11_2N )||(def_ddr3_1600_11_11_11R )||(def_ddr3_1866_11_11_11R )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1866_11_11_11_LR )||(def_ddr3_1600_11_11_11_L2 )||(def_ddr3_1866_11_11_11_L2 )||(def_ddr4_1600_11_11_11 )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1600_11_11_11R )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1600_11_11_11_L2)); define def_mba_tmr1q_cfg_trap40 = ((def_ddr3_1866_12_12_12 )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1866_12_12_12R )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1866_12_12_12_L2)); define def_mba_tmr1q_cfg_trap42 = (def_ddr4_1600_12_12_12 ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2); define def_mba_tmr1q_cfg_trap43 = ((def_ddr4_1866_11_11_11 )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_1866_11_11_11R )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_1866_11_11_11_L2)); define def_mba_tmr1q_cfg_trap44 = ((def_ddr4_1866_12_12_12 )||(def_ddr4_1866_12_12_12_2N )||(def_ddr4_1866_12_12_12R )||(def_ddr4_1866_12_12_12_LR )||(def_ddr4_1866_12_12_12_L2)); define def_mba_tmr1q_cfg_trap46 = (def_ddr4_1866_13_13_13 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2); #define def_mba_tmr1q_cfg_trap48 = ((def_ddr4_2133_12_12_12 )||(def_ddr4_2133_12_12_12_2N )||(def_ddr4_2133_12_12_12R )||(def_ddr4_2133_12_12_12_LR )||(def_ddr4_2133_12_12_12_L2)); #define def_mba_tmr1q_cfg_trap49 = ((def_ddr4_2133_13_13_13 )||(def_ddr4_2133_13_13_13_2N )||(def_ddr4_2133_13_13_13R )||(def_ddr4_2133_13_13_13_LR )||(def_ddr4_2133_13_13_13_L2)); #define def_mba_tmr1q_cfg_trap52 = ((def_ddr4_2400_13_13_13 )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_2400_13_13_13R )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_2400_13_13_13_L2)); #define def_mba_tmr1q_cfg_trap53 = ((def_ddr4_2400_14_14_14 )||(def_ddr4_2400_14_14_14_2N )||(def_ddr4_2400_14_14_14R )||(def_ddr4_2400_14_14_14_LR )||(def_ddr4_2400_14_14_14_L2)); #new 30,32,34 define def_mba_tmr1q_cfg_twap30 = (def_ddr3_1066_6_6_6_group); define def_mba_tmr1q_cfg_twap32 = (def_ddr3_1066_7_7_7_group); define def_mba_tmr1q_cfg_twap34 = (def_ddr3_1066_8_8_8_group); define def_mba_tmr1q_cfg_twap37 = (def_mba_tmr1q_cfg_trap32); define def_mba_tmr1q_cfg_twap39 = (def_mba_tmr1q_cfg_trap33); define def_mba_tmr1q_cfg_twap42 = (def_mba_tmr1q_cfg_trap37); define def_mba_tmr1q_cfg_twap44 = (def_mba_tmr1q_cfg_trap38); define def_mba_tmr1q_cfg_twap46 = ((def_ddr3_1600_11_11_11 )||( def_ddr3_1600_11_11_11_2N )||( def_ddr3_1600_11_11_11R )||( def_ddr3_1600_11_11_11_LR )||( def_ddr3_1600_11_11_11_L2 )||( def_ddr4_1600_11_11_11 )||( def_ddr4_1600_11_11_11_2N )||( def_ddr4_1600_11_11_11R )||( def_ddr4_1600_11_11_11_LR )||( def_ddr4_1600_11_11_11_L2)); define def_mba_tmr1q_cfg_twap48 = (def_ddr4_1600_12_12_12 ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2); define def_mba_tmr1q_cfg_twap49 = ((def_ddr3_1866_11_11_11 )||( def_ddr3_1866_11_11_11_2N )||( def_ddr3_1866_11_11_11R )||( def_ddr3_1866_11_11_11_LR )||( def_ddr3_1866_11_11_11_L2 )||( def_ddr4_1866_11_11_11 )||( def_ddr4_1866_11_11_11_2N )||( def_ddr4_1866_11_11_11R )||( def_ddr4_1866_11_11_11_LR )||( def_ddr4_1866_11_11_11_L2)); define def_mba_tmr1q_cfg_twap51 = ((def_ddr3_1866_12_12_12 )||( def_ddr3_1866_12_12_12_2N )||( def_ddr3_1866_12_12_12R )||( def_ddr3_1866_12_12_12_LR )||( def_ddr3_1866_12_12_12_L2 )||( def_ddr4_1866_12_12_12 )||( def_ddr4_1866_12_12_12_2N )||( def_ddr4_1866_12_12_12R )||( def_ddr4_1866_12_12_12_LR )||( def_ddr4_1866_12_12_12_L2)); define def_mba_tmr1q_cfg_twap53 = (def_ddr4_1866_13_13_13 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2); #define def_mba_tmr1q_cfg_twap54 = (def_mba_tmr1q_cfg_trap48); #define def_mba_tmr1q_cfg_twap56 = (def_mba_tmr1q_cfg_trap49); #define def_mba_tmr1q_cfg_twap59 = (def_mba_tmr1q_cfg_trap52); #define def_mba_tmr1q_cfg_twap61 = (def_mba_tmr1q_cfg_trap53); #mixed stop here define def_mba_dsm0q_cfg_rdtag_dly12 = (def_ddr3_1066_6_6_6_2N); define def_mba_dsm0q_cfg_rdtag_dly13 = (def_ddr3_1066_6_6_6); define def_mba_dsm0q_cfg_rdtag_dly14 = (def_ddr3_1066_7_7_7_2N || def_ddr3_1066_6_6_6R ||def_ddr3_1333_8_8_8_2N); define def_mba_dsm0q_cfg_rdtag_dly15 = (def_ddr3_1066_7_7_7 ||def_ddr3_1066_8_8_8_2N ||def_ddr3_1333_8_8_8 ||def_ddr3_1600_9_9_9_2N ||def_ddr4_1600_9_9_9_2N); define def_mba_dsm0q_cfg_rdtag_dly16 = (def_ddr3_1066_8_8_8 ||def_ddr3_1066_7_7_7R ||def_ddr3_1066_6_6_6_L2 ||def_ddr3_1600_9_9_9 ||def_ddr3_1333_9_9_9_2N ||def_ddr3_1600_10_10_10_2N ||def_ddr3_1333_8_8_8R ||def_ddr4_1600_9_9_9); define def_mba_dsm0q_cfg_rdtag_dly17 = (def_ddr3_1066_8_8_8R ||def_ddr3_1066_6_6_6_LR ||def_ddr3_1333_9_9_9 ||def_ddr3_1600_9_9_9R ||def_ddr4_1600_10_10_10_2N ||def_ddr4_1600_9_9_9R); define def_mba_dsm0q_cfg_rdtag_dly18 = (def_ddr3_1066_7_7_7_L2 ||def_ddr3_1600_10_10_10 ||def_ddr3_1600_11_11_11_2N ||def_ddr3_1866_11_11_11_2N ||def_ddr3_1333_9_9_9R ||def_ddr3_1333_8_8_8_L2 ||def_ddr4_1600_10_10_10); define def_mba_dsm0q_cfg_rdtag_dly19 = (def_ddr3_1066_7_7_7_LR ||def_ddr3_1066_8_8_8_L2 ||def_ddr3_1600_10_10_10R ||def_ddr3_1333_8_8_8_LR ||def_ddr3_1600_9_9_9_L2 ||def_ddr4_1600_11_11_11_2N ||def_ddr4_1866_11_11_11_2N ||def_ddr4_1600_10_10_10R ||def_ddr4_1600_9_9_9_L2); define def_mba_dsm0q_cfg_rdtag_dly20 = (def_ddr3_1066_8_8_8_LR ||def_ddr3_1600_11_11_11 ||def_ddr3_1866_11_11_11 ||def_ddr3_1866_12_12_12_2N ||def_ddr3_1600_9_9_9_LR ||def_ddr3_1333_9_9_9_L2 ||def_ddr4_1600_11_11_11 ||def_ddr4_1866_11_11_11 ||def_ddr4_1600_9_9_9_LR); define def_mba_dsm0q_cfg_rdtag_dly21 = (def_ddr4_1600_12_12_12_2N ||def_ddr3_1600_11_11_11R ||def_ddr3_1866_11_11_11R ||def_ddr3_1333_9_9_9_LR ||def_ddr3_1600_10_10_10_L2 ||def_ddr4_1866_12_12_12_2N ||def_ddr4_2133_12_12_12_2N ||def_ddr4_1600_11_11_11R ||def_ddr4_1866_11_11_11R ||def_ddr4_1600_10_10_10_L2); define def_mba_dsm0q_cfg_rdtag_dly22 = (def_ddr4_1600_12_12_12 ||def_ddr3_1866_12_12_12 ||def_ddr3_1600_10_10_10_LR ||def_ddr4_1866_12_12_12 ||def_ddr4_2133_12_12_12 ||def_ddr4_2400_13_13_13_2N ||def_ddr4_1600_10_10_10_LR); define def_mba_dsm0q_cfg_rdtag_dly23 = (def_ddr4_1866_13_13_13_2N ||def_ddr4_1600_12_12_12R ||def_ddr3_1866_12_12_12R ||def_ddr3_1600_11_11_11_L2 ||def_ddr3_1866_11_11_11_L2 ||def_ddr4_2400_13_13_13 ||def_ddr4_2133_13_13_13_2N ||def_ddr4_1866_12_12_12R ||def_ddr4_2133_12_12_12R ||def_ddr4_1600_11_11_11_L2 ||def_ddr4_1866_11_11_11_L2); define def_mba_dsm0q_cfg_rdtag_dly24 = (def_ddr4_1866_13_13_13 ||def_ddr3_1600_11_11_11_LR ||def_ddr3_1866_11_11_11_LR ||def_ddr4_2133_13_13_13 ||def_ddr4_2400_14_14_14_2N ||def_ddr4_2400_13_13_13R ||def_ddr4_1600_11_11_11_LR ||def_ddr4_1866_11_11_11_LR); define def_mba_dsm0q_cfg_rdtag_dly25 = (def_ddr4_1866_13_13_13R ||def_ddr4_1600_12_12_12_L2 ||def_ddr3_1866_12_12_12_L2 ||def_ddr4_2400_14_14_14 ||def_ddr4_2133_13_13_13R ||def_ddr4_1866_12_12_12_L2 ||def_ddr4_2133_12_12_12_L2); define def_mba_dsm0q_cfg_rdtag_dly26 = (def_ddr4_1600_12_12_12_LR ||def_ddr3_1866_12_12_12_LR ||def_ddr4_2400_14_14_14R ||def_ddr4_1866_12_12_12_LR ||def_ddr4_2133_12_12_12_LR ||def_ddr4_2400_13_13_13_L2); define def_mba_dsm0q_cfg_rdtag_dly27 = (def_ddr4_1866_13_13_13_L2 ||def_ddr4_2400_13_13_13_LR ||def_ddr4_2133_13_13_13_L2); define def_mba_dsm0q_cfg_rdtag_dly28 = (def_ddr4_1866_13_13_13_LR ||def_ddr4_2133_13_13_13_LR ||def_ddr4_2400_14_14_14_L2); define def_mba_dsm0q_cfg_rdtag_dly29 = (def_ddr4_2400_14_14_14_LR); #mixed define def_mba_dsm0q_cfg_wrdata_dly3 = (def_ddr3_1066_6_6_6_2N ||def_ddr3_1066_6_6_6_L2); define def_mba_dsm0q_cfg_wrdata_dly4 = (def_ddr3_1066_6_6_6 ||def_ddr3_1066_7_7_7_2N ||def_ddr3_1066_6_6_6_LR ||def_ddr3_1066_7_7_7_L2); define def_mba_dsm0q_cfg_wrdata_dly5 = (def_ddr3_1066_7_7_7 ||def_ddr3_1066_8_8_8_2N ||def_ddr3_1066_6_6_6R ||def_ddr3_1066_7_7_7_LR ||def_ddr3_1066_8_8_8_L2); define def_mba_dsm0q_cfg_wrdata_dly6 = (def_ddr3_1066_8_8_8 ||def_ddr3_1066_7_7_7R ||def_ddr3_1066_8_8_8_LR ||def_ddr3_1333_8_8_8_2N ||def_ddr3_1333_8_8_8_L2); define def_mba_dsm0q_cfg_wrdata_dly7 = (def_ddr3_1066_8_8_8R ||def_ddr3_1333_8_8_8 ||def_ddr3_1333_9_9_9_2N ||def_ddr3_1333_8_8_8_LR ||def_ddr3_1333_9_9_9_L2); define def_mba_dsm0q_cfg_wrdata_dly8 = (def_ddr3_1333_9_9_9 ||def_ddr3_1600_9_9_9_2N ||def_ddr3_1333_8_8_8R ||def_ddr3_1333_9_9_9_LR ||def_ddr3_1600_9_9_9_L2); define def_mba_dsm0q_cfg_wrdata_dly9 = (def_ddr3_1600_9_9_9 ||def_ddr3_1600_10_10_10_2N ||def_ddr3_1333_9_9_9R ||def_ddr3_1600_9_9_9_LR ||def_ddr3_1600_10_10_10_L2 ||def_ddr4_1600_9_9_9_2N ||def_ddr4_1600_9_9_9_L2); define def_mba_dsm0q_cfg_wrdata_dly10 = (def_ddr3_1600_10_10_10 ||def_ddr3_1600_11_11_11_2N ||def_ddr3_1600_9_9_9R ||def_ddr3_1600_10_10_10_LR ||def_ddr3_1600_11_11_11_L2 ||def_ddr4_1600_9_9_9 ||def_ddr4_1600_10_10_10_2N ||def_ddr4_1600_9_9_9_LR ||def_ddr4_1600_10_10_10_L2); define def_mba_dsm0q_cfg_wrdata_dly11 = (def_ddr3_1600_11_11_11 ||def_ddr3_1866_11_11_11_2N ||def_ddr3_1600_10_10_10R ||def_ddr3_1600_11_11_11_LR ||def_ddr3_1866_11_11_11_L2 ||def_ddr4_1600_10_10_10 ||def_ddr4_1600_11_11_11_2N ||def_ddr4_1600_9_9_9R ||def_ddr4_1600_10_10_10_LR ||def_ddr4_1600_11_11_11_L2); define def_mba_dsm0q_cfg_wrdata_dly12 = (def_ddr4_1600_12_12_12_L2 ||def_ddr4_1600_12_12_12_2N ||def_ddr3_1866_11_11_11 ||def_ddr3_1866_12_12_12_2N ||def_ddr3_1600_11_11_11R ||def_ddr3_1866_11_11_11_LR ||def_ddr3_1866_12_12_12_L2 ||def_ddr4_1600_11_11_11 ||def_ddr4_1866_11_11_11_2N ||def_ddr4_1600_10_10_10R ||def_ddr4_1600_11_11_11_LR ||def_ddr4_1866_11_11_11_L2); define def_mba_dsm0q_cfg_wrdata_dly13 = (def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12 ||def_ddr3_1866_12_12_12 ||def_ddr3_1866_11_11_11R ||def_ddr3_1866_12_12_12_LR ||def_ddr4_1866_11_11_11 ||def_ddr4_1866_12_12_12_2N ||def_ddr4_1600_11_11_11R ||def_ddr4_1866_11_11_11_LR ||def_ddr4_1866_12_12_12_L2); define def_mba_dsm0q_cfg_wrdata_dly14 = (def_ddr4_1866_13_13_13_L2 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1600_12_12_12R ||def_ddr3_1866_12_12_12R ||def_ddr4_1866_12_12_12 ||def_ddr4_2133_12_12_12_2N ||def_ddr4_1866_11_11_11R ||def_ddr4_1866_12_12_12_LR ||def_ddr4_2133_12_12_12_L2); define def_mba_dsm0q_cfg_wrdata_dly15 = (def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13 ||def_ddr4_2133_12_12_12 ||def_ddr4_2133_13_13_13_2N ||def_ddr4_1866_12_12_12R ||def_ddr4_2133_12_12_12_LR ||def_ddr4_2133_13_13_13_L2); define def_mba_dsm0q_cfg_wrdata_dly16 = (def_ddr4_1866_13_13_13R ||def_ddr4_2133_13_13_13 ||def_ddr4_2400_13_13_13_2N ||def_ddr4_2133_12_12_12R ||def_ddr4_2133_13_13_13_LR ||def_ddr4_2400_13_13_13_L2); define def_mba_dsm0q_cfg_wrdata_dly17 = (def_ddr4_2400_13_13_13 ||def_ddr4_2400_14_14_14_2N ||def_ddr4_2133_13_13_13R ||def_ddr4_2400_13_13_13_LR ||def_ddr4_2400_14_14_14_L2); define def_mba_dsm0q_cfg_wrdata_dly18 = (def_ddr4_2400_14_14_14 ||def_ddr4_2400_13_13_13R ||def_ddr4_2400_14_14_14_LR); define def_mba_dsm0q_cfg_wrdata_dly19 = (def_ddr4_2400_14_14_14R); # define def_MBAREF0Q_cfg_refr_tsv_stack_dly32 = (def_1066_2gb || def_1333_2gb || def_1600_2gb || def_1866_2gb || def_1066_2gb_fast_exit_pd || def_1333_2gb_fast_exit_pd || def_1600_2gb_fast_exit_pd || def_1866_2gb_fast_exit_pd || def_1600_2gb_ddr4 || def_1866_2gb_ddr4 || def_2133_2gb_ddr4 || def_2400_2gb_ddr4 || def_1600_2gb_fast_exit_pd_ddr4 || def_1866_2gb_fast_exit_pd_ddr4 || def_2133_2gb_fast_exit_pd_ddr4 || def_2400_2gb_fast_exit_pd_ddr4 ); define def_MBAREF0Q_cfg_refr_tsv_stack_dly48 = (def_1066_4gb || def_1333_4gb || def_1600_4gb || def_1866_4gb || def_1066_4gb_fast_exit_pd || def_1333_4gb_fast_exit_pd || def_1600_4gb_fast_exit_pd || def_1866_4gb_fast_exit_pd || def_1600_4gb_ddr4 || def_1866_4gb_ddr4 || def_2133_4gb_ddr4 || def_2400_4gb_ddr4 || def_1600_4gb_fast_exit_pd_ddr4 || def_1866_4gb_fast_exit_pd_ddr4 || def_2133_4gb_fast_exit_pd_ddr4 || def_2400_4gb_fast_exit_pd_ddr4 ); define def_MBAREF0Q_cfg_refr_tsv_stack_dly64 = (def_1066_8gb || def_1333_8gb || def_1600_8gb || def_1866_8gb || def_1066_8gb_fast_exit_pd || def_1333_8gb_fast_exit_pd || def_1600_8gb_fast_exit_pd || def_1866_8gb_fast_exit_pd || def_1600_8gb_ddr4 || def_1866_8gb_ddr4 || def_2133_8gb_ddr4 || def_2400_8gb_ddr4 || def_1600_8gb_fast_exit_pd_ddr4 || def_1866_8gb_fast_exit_pd_ddr4 || def_2133_8gb_fast_exit_pd_ddr4 || def_2400_8gb_fast_exit_pd_ddr4 ); # 3 -- old #define def_MBARPC0Q_cfg_pup_pdn_dly3 = (def_1066_2gb ||def_1066_2gb_fast_exit_pd ||def_1066_4gb ||def_1066_4gb_fast_exit_pd ||def_1066_8gb ||def_1066_8gb_fast_exit_pd ); # #define def_MBARPC0Q_cfg_pup_pdn_dly4 = (def_1333_2gb ||def_1333_2gb_fast_exit_pd ||def_1600_2gb ||def_1600_2gb_fast_exit_pd ||def_1600_2gb_ddr4 ||def_1600_2gb_fast_exit_pd_ddr4 ||def_1333_4gb ||def_1333_4gb_fast_exit_pd ||def_1333_8gb ||def_1333_8gb_fast_exit_pd ||def_1600_4gb ||def_1600_4gb_fast_exit_pd ||def_1600_4gb_ddr4 ||def_1600_4gb_fast_exit_pd_ddr4 ||def_1600_8gb ||def_1600_8gb_fast_exit_pd ||def_1600_8gb_ddr4 ||def_1600_8gb_fast_exit_pd_ddr4 ); #define def_MBARPC0Q_cfg_pup_pdn_dly5 = (def_1866_2gb ||def_1866_2gb_fast_exit_pd ||def_1866_2gb_ddr4 ||def_1866_2gb_fast_exit_pd_ddr4 ||def_2133_2gb_ddr4 ||def_2133_2gb_fast_exit_pd_ddr4 ||def_2400_2gb_ddr4 ||def_2400_2gb_fast_exit_pd_ddr4 ||def_2133_4gb_fast_exit_pd_ddr4 ||def_2133_4gb_ddr4 ||def_2400_4gb_ddr4 ||def_2400_4gb_fast_exit_pd_ddr4 ||def_1866_4gb ||def_1866_4gb_fast_exit_pd ||def_1866_4gb_ddr4 ||def_1866_4gb_fast_exit_pd_ddr4 ||def_1866_8gb ||def_1866_8gb_fast_exit_pd ||def_1866_8gb_ddr4 ||def_1866_8gb_fast_exit_pd_ddr4 ||def_2133_8gb_fast_exit_pd_ddr4 ||def_2133_8gb_ddr4 ||def_2400_8gb_ddr4 ||def_2400_8gb_fast_exit_pd_ddr4 ); # new define def_MBARPC0Q_cfg_pup_pdn_dly3 = (def_1066_2gb ||def_1066_4gb ||def_1066_8gb ||def_1066_2gb_fast_exit_pd ||def_1066_4gb_fast_exit_pd ||def_1066_8gb_fast_exit_pd ); define def_MBARPC0Q_cfg_pup_pdn_dly4 = (def_1333_2gb ||def_1333_4gb ||def_1333_8gb ||def_1600_2gb ||def_1600_4gb ||def_1600_8gb ||def_1333_2gb_fast_exit_pd ||def_1333_4gb_fast_exit_pd ||def_1333_8gb_fast_exit_pd ||def_1600_2gb_fast_exit_pd ||def_1600_4gb_fast_exit_pd ||def_1600_8gb_fast_exit_pd ||def_1600_2gb_ddr4 ||def_1600_4gb_ddr4 ||def_1600_8gb_ddr4 ||def_1600_2gb_fast_exit_pd_ddr4 ||def_1600_4gb_fast_exit_pd_ddr4 ||def_1600_8gb_fast_exit_pd_ddr4 ); define def_MBARPC0Q_cfg_pup_pdn_dly5 = (def_1866_2gb ||def_1866_4gb ||def_1866_8gb ||def_1866_2gb_fast_exit_pd ||def_1866_4gb_fast_exit_pd ||def_1866_8gb_fast_exit_pd ||def_1866_2gb_ddr4 ||def_1866_4gb_ddr4 ||def_1866_8gb_ddr4 ||def_1866_2gb_fast_exit_pd_ddr4 ||def_1866_4gb_fast_exit_pd_ddr4 ||def_1866_8gb_fast_exit_pd_ddr4 ); define def_MBARPC0Q_cfg_pup_pdn_dly6 = (def_2133_2gb_ddr4 ||def_2133_4gb_ddr4 ||def_2133_8gb_ddr4 ||def_2400_2gb_ddr4 ||def_2400_4gb_ddr4 ||def_2400_8gb_ddr4 ||def_2133_2gb_fast_exit_pd_ddr4 ||def_2133_4gb_fast_exit_pd_ddr4 ||def_2133_8gb_fast_exit_pd_ddr4 ||def_2400_2gb_fast_exit_pd_ddr4 ||def_2400_4gb_fast_exit_pd_ddr4 ||def_2400_8gb_fast_exit_pd_ddr4 ); #3 #define def_MBARPC0Q_cfg_pdn_pup_dly3 = (def_1066_2gb ||def_1066_2gb_fast_exit_pd ||def_1066_4gb ||def_1066_4gb_fast_exit_pd ||def_1066_8gb ||def_1066_8gb_fast_exit_pd ); #define def_MBARPC0Q_cfg_pdn_pup_dly4 = (def_1333_2gb ||def_1333_2gb_fast_exit_pd ||def_1600_2gb ||def_1600_2gb_fast_exit_pd ||def_1600_2gb_ddr4 ||def_1600_2gb_fast_exit_pd_ddr4 ||def_1333_4gb ||def_1333_4gb_fast_exit_pd ||def_1333_8gb ||def_1333_8gb_fast_exit_pd ||def_1600_4gb ||def_1600_4gb_fast_exit_pd ||def_1600_4gb_ddr4 ||def_1600_4gb_fast_exit_pd_ddr4 ||def_1600_8gb ||def_1600_8gb_fast_exit_pd ||def_1600_8gb_ddr4 ||def_1600_8gb_fast_exit_pd_ddr4 ); #define def_MBARPC0Q_cfg_pdn_pup_dly5 = (def_1866_2gb ||def_1866_2gb_fast_exit_pd ||def_1866_2gb_ddr4 ||def_1866_2gb_fast_exit_pd_ddr4 ||def_2133_2gb_ddr4 ||def_2133_2gb_fast_exit_pd_ddr4 ||def_2400_2gb_ddr4 ||def_2400_2gb_fast_exit_pd_ddr4 ||def_2133_4gb_fast_exit_pd_ddr4 ||def_2133_4gb_ddr4 ||def_2400_4gb_ddr4 ||def_2400_4gb_fast_exit_pd_ddr4 ||def_1866_4gb ||def_1866_4gb_fast_exit_pd ||def_1866_4gb_ddr4 ||def_1866_4gb_fast_exit_pd_ddr4 ||def_1866_8gb ||def_1866_8gb_fast_exit_pd ||def_1866_8gb_ddr4 ||def_1866_8gb_fast_exit_pd_ddr4 ||def_2133_8gb_fast_exit_pd_ddr4 ||def_2133_8gb_ddr4 ||def_2400_8gb_ddr4 ||def_2400_8gb_fast_exit_pd_ddr4 ); #3 define def_MBARPC0Q_cfg_pdn_pup_dly3 = (def_MBARPC0Q_cfg_pup_pdn_dly3); define def_MBARPC0Q_cfg_pdn_pup_dly4 = (def_MBARPC0Q_cfg_pup_pdn_dly4); define def_MBARPC0Q_cfg_pdn_pup_dly5 = (def_MBARPC0Q_cfg_pup_pdn_dly5); define def_MBARPC0Q_cfg_pdn_pup_dly6 = (def_MBARPC0Q_cfg_pup_pdn_dly6); # 13 -- old #define def_MBARPC0Q_cfg_pup_avail_dly13 = (def_1066_2gb )||(def_1066_4gb )||(def_1066_8gb); # #define def_MBARPC0Q_cfg_pup_avail_dly4 = ((def_1066_2gb_fast_exit_pd )||(def_1066_4gb_fast_exit_pd )||(def_1066_8gb_fast_exit_pd )||(def_1333_2gb_fast_exit_pd )||(def_1333_4gb_fast_exit_pd )||(def_1333_8gb_fast_exit_pd)); #define def_MBARPC0Q_cfg_pup_avail_dly5 = ((def_1600_2gb_fast_exit_pd )||(def_1600_2gb_fast_exit_pd_ddr4 )||(def_1600_4gb_fast_exit_pd )||(def_1600_4gb_fast_exit_pd_ddr4 )||(def_1600_8gb_fast_exit_pd )||(def_1600_8gb_fast_exit_pd_ddr4 )); #define def_MBARPC0Q_cfg_pup_avail_dly6 = ((def_1866_2gb_fast_exit_pd )||(def_1866_2gb_fast_exit_pd_ddr4 )||(def_2133_2gb_fast_exit_pd_ddr4 )||(def_2400_2gb_fast_exit_pd_ddr4 )||(def_2133_4gb_fast_exit_pd_ddr4 )||(def_2400_4gb_fast_exit_pd_ddr4 )||(def_1866_4gb_fast_exit_pd )||(def_1866_4gb_fast_exit_pd_ddr4 )||(def_1866_8gb_fast_exit_pd )||(def_1866_8gb_fast_exit_pd_ddr4 )||(def_2133_8gb_fast_exit_pd_ddr4 )||(def_2400_8gb_fast_exit_pd_ddr4 )); #define def_MBARPC0Q_cfg_pup_avail_dly16 = ((def_1333_2gb )||(def_1333_4gb )||(def_1333_8gb)); #define def_MBARPC0Q_cfg_pup_avail_dly20 = ((def_1600_2gb )||(def_1600_2gb_ddr4 )||(def_1600_4gb )||(def_1600_4gb_ddr4 )||(def_1600_8gb )||(def_1600_8gb_ddr4 )); #define def_MBARPC0Q_cfg_pup_avail_dly23 = ((def_1866_2gb )||(def_1866_2gb_ddr4 )||(def_2133_2gb_ddr4 )||(def_2400_2gb_ddr4 )||(def_2133_4gb_ddr4 )||(def_2400_4gb_ddr4 )||(def_1866_4gb )||(def_1866_4gb_ddr4 )||(def_1866_8gb )||(def_1866_8gb_ddr4 )||(def_2133_8gb_ddr4 )||(def_2400_8gb_ddr4 )); # new define def_MBARPC0Q_cfg_pup_avail_dly4 = ( def_1066_2gb_fast_exit_pd ||def_1066_4gb_fast_exit_pd ||def_1066_8gb_fast_exit_pd ||def_1333_2gb_fast_exit_pd ||def_1333_4gb_fast_exit_pd ||def_1333_8gb_fast_exit_pd ); define def_MBARPC0Q_cfg_pup_avail_dly5 = ( def_1600_2gb_fast_exit_pd ||def_1600_4gb_fast_exit_pd ||def_1600_8gb_fast_exit_pd ||def_1600_2gb_fast_exit_pd_ddr4 ||def_1600_4gb_fast_exit_pd_ddr4 ||def_1600_8gb_fast_exit_pd_ddr4 ); define def_MBARPC0Q_cfg_pup_avail_dly6 = ( def_1866_2gb_fast_exit_pd ||def_1866_4gb_fast_exit_pd ||def_1866_8gb_fast_exit_pd ||def_1866_2gb_fast_exit_pd_ddr4 ||def_1866_4gb_fast_exit_pd_ddr4 ||def_1866_8gb_fast_exit_pd_ddr4 ); define def_MBARPC0Q_cfg_pup_avail_dly7 = ( def_2133_2gb_fast_exit_pd_ddr4 ||def_2133_4gb_fast_exit_pd_ddr4 ||def_2133_8gb_fast_exit_pd_ddr4 ); define def_MBARPC0Q_cfg_pup_avail_dly8 = ( def_2400_2gb_fast_exit_pd_ddr4 ||def_2400_4gb_fast_exit_pd_ddr4 ||def_2400_8gb_fast_exit_pd_ddr4 ); define def_MBARPC0Q_cfg_pup_avail_dly13 = ( def_1066_2gb ||def_1066_4gb ||def_1066_8gb ); define def_MBARPC0Q_cfg_pup_avail_dly16 = ( def_1333_2gb ||def_1333_4gb ||def_1333_8gb ); define def_MBARPC0Q_cfg_pup_avail_dly20 = ( def_1600_2gb ||def_1600_4gb ||def_1600_8gb ||def_1600_2gb_ddr4 ||def_1600_4gb_ddr4 ||def_1600_8gb_ddr4 ); define def_MBARPC0Q_cfg_pup_avail_dly23 = ( def_1866_2gb ||def_1866_4gb ||def_1866_8gb ||def_1866_2gb_ddr4 ||def_1866_4gb_ddr4 ||def_1866_8gb_ddr4 ); define def_MBARPC0Q_cfg_pup_avail_dly26 = ( def_2133_2gb_ddr4 ||def_2133_4gb_ddr4 ||def_2133_8gb_ddr4 ); define def_MBARPC0Q_cfg_pup_avail_dly29 = ( def_2400_2gb_ddr4 ||def_2400_4gb_ddr4 ||def_2400_8gb_ddr4 ); ## MCBIST address map defines ## cols define def_mcb_addr_col13_29 = (ATTR_EFF_DRAM_COLS == 12); define def_mcb_addr_unset_col13 = ((ATTR_EFF_DRAM_COLS == 10) || (ATTR_EFF_DRAM_COLS == 11)); define def_mcb_addr_col11_30 = ((ATTR_EFF_DRAM_COLS == 11) || (ATTR_EFF_DRAM_COLS == 12)); define def_mcb_addr_unset_col11 = (ATTR_EFF_DRAM_COLS == 10); ## banks define def_mcb_addr_bank3_27 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16)); define def_mcb_addr_bank3_26 = ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16)); define def_mcb_addr_bank3_25 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16)); define def_mcb_addr_unset_bank3 = (ATTR_EFF_DRAM_BANKS == 8); define def_mcb_addr_bank2_28 = ((ATTR_EFF_DRAM_COLS == 10) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); define def_mcb_addr_bank2_27 = ((ATTR_EFF_DRAM_COLS == 11) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); define def_mcb_addr_bank2_26 = ((ATTR_EFF_DRAM_COLS == 12) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); define def_mcb_addr_bank1_29 = ((ATTR_EFF_DRAM_COLS == 10) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); define def_mcb_addr_bank1_28 = ((ATTR_EFF_DRAM_COLS == 11) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); define def_mcb_addr_bank1_27 = ((ATTR_EFF_DRAM_COLS == 12) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); define def_mcb_addr_bank0_30 = ((ATTR_EFF_DRAM_COLS == 10) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); define def_mcb_addr_bank0_29 = ((ATTR_EFF_DRAM_COLS == 11) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); define def_mcb_addr_bank0_28 = ((ATTR_EFF_DRAM_COLS == 12) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); ## Rows define def_mcb_addr_row16_11 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17)); define def_mcb_addr_row16_10 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row16_9 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row16_8 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)); define def_mcb_addr_unset_row16 = ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16)); define def_mcb_addr_row15_12 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row15_11 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row15_10 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row15_9 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_unset_row15 = ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15)); define def_mcb_addr_row14_13 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row14_12 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row14_11 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row14_10 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_unset_row14 = (ATTR_EFF_DRAM_ROWS == 14); define def_mcb_addr_row13_14 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row13_13 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row13_12 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row13_11 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row12_15 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row12_14 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row12_13 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row12_12 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row11_16 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row11_15 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row11_14 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row11_13 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row10_17 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row10_16 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row10_15 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row10_14 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row9_18 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row9_17 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row9_16 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row9_15 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row8_19 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row8_18 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row8_17 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row8_16 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row7_20 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row7_19 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row7_18 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row7_17 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row6_21 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row6_20 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row6_19 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row6_18 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row5_22 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row5_21 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row5_20 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row5_19 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row4_23 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row4_22 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row4_21 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row4_20 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row3_24 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row3_23 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row3_22 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row3_21 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row2_25 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row2_24 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row2_23 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row2_22 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row1_26 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row1_25 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row1_24 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row1_23 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row0_27 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row0_26 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row0_25 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); define def_mcb_addr_row0_24 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_srank0_unset = ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 8); define def_mcb_srank1_unset = ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 4); define def_mcb_srank2_unset = ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2); ## SRANKS ############################################# SRANK bits Col = 10 , banks = 16 define def_mcb_addr_col10_bnk16_srank2_12 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col10_bnk16_srank1_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col10_bnk16_srank0_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col10_bnk16_srank2_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col10_bnk16_srank1_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col10_bnk16_srank0_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col10_bnk16_srank2_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col10_bnk16_srank1_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col10_bnk16_srank0_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col10_bnk16_srank2_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_col10_bnk16_srank1_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_col10_bnk16_srank0_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); ############################################# SRANK bits Col = 10 , banks = 8 define def_mcb_addr_col10_bnk8_srank2_13 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col10_bnk8_srank1_12 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col10_bnk8_srank0_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col10_bnk8_srank2_12 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col10_bnk8_srank1_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col10_bnk8_srank0_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col10_bnk8_srank2_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col10_bnk8_srank1_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col10_bnk8_srank0_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col10_bnk8_srank2_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_col10_bnk8_srank1_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_col10_bnk8_srank0_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); ############################################# SRANK bits Col = 11 , banks = 16 define def_mcb_addr_col11_bnk16_srank2_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col11_bnk16_srank1_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col11_bnk16_srank0_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col11_bnk16_srank2_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col11_bnk16_srank1_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col11_bnk16_srank0_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col11_bnk16_srank2_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col11_bnk16_srank1_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col11_bnk16_srank0_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col11_bnk16_srank2_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_col11_bnk16_srank1_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_col11_bnk16_srank0_6 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); ############################################# SRANK bits Col = 11 , banks = 8 define def_mcb_addr_col11_bnk8_srank2_12 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col11_bnk8_srank1_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col11_bnk8_srank0_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col11_bnk8_srank2_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col11_bnk8_srank1_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col11_bnk8_srank0_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col11_bnk8_srank2_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col11_bnk8_srank1_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col11_bnk8_srank0_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col11_bnk8_srank2_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_col11_bnk8_srank1_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_col11_bnk8_srank0_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); ############################################# SRANK bits Col = 12 , banks = 16 define def_mcb_addr_col12_bnk16_srank2_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col12_bnk16_srank1_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col12_bnk16_srank0_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col12_bnk16_srank2_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col12_bnk16_srank1_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col12_bnk16_srank0_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col12_bnk16_srank2_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col12_bnk16_srank1_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col12_bnk16_srank0_6 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col12_bnk16_srank2_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_col12_bnk16_srank1_6 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_col12_bnk16_srank0_5 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); ############################################# SRANK bits Col = 12 , banks = 8 define def_mcb_addr_col12_bnk8_srank2_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col12_bnk8_srank1_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col12_bnk8_srank0_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_col12_bnk8_srank2_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col12_bnk8_srank1_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col12_bnk8_srank0_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_col12_bnk8_srank2_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col12_bnk8_srank1_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col12_bnk8_srank0_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_col12_bnk8_srank2_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_col12_bnk8_srank1_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_col12_bnk8_srank0_6 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); ### MRANKS define def_mcb_mrank1_unset = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 8); define def_mcb_mrank2_unset = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 4); define def_mcb_mrank3_unset = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 0); ############################################# MRANK bits Col = 10 , banks = 16 define def_mcb_addr_row14_col10_bnk16_mrank3_12 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk16_mrank2_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk16_mrank1_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk16_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk16_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk16_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk16_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk16_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk16_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row15_col10_bnk16_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk16_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk16_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk16_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk16_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk16_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row16_col10_bnk16_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk16_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk16_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row17_col10_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk16_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk16_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk16_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); ############################################# MRANK bits Col = 10 , banks = 8 define def_mcb_addr_row14_col10_bnk8_mrank3_13 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk8_mrank2_12 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk8_mrank1_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk8_mrank3_12 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk8_mrank2_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk8_mrank1_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk8_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk8_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk8_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col10_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row15_col10_bnk8_mrank3_12 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk8_mrank2_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk8_mrank1_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk8_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk8_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk8_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col10_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row16_col10_bnk8_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk8_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk8_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col10_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row17_col10_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk8_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk8_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col10_bnk8_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); ############################################# MRANK bits Col = 11 , banks = 16 define def_mcb_addr_row14_col11_bnk16_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk16_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk16_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk16_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk16_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk16_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row15_col11_bnk16_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk16_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk16_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row16_col11_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk16_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk16_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk16_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row17_col11_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk16_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk16_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk16_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk16_mrank3_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk16_mrank2_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk16_mrank1_3 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); ############################################# MRANK bits Col = 11 , banks = 8 define def_mcb_addr_row14_col11_bnk8_mrank3_12 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk8_mrank2_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk8_mrank1_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk8_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk8_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk8_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col11_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row15_col11_bnk8_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk8_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk8_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col11_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row16_col11_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk8_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk8_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col11_bnk8_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row17_col11_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk8_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk8_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk8_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk8_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk8_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col11_bnk8_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); ############################################# MRANK bits Col = 12 , banks = 16 define def_mcb_addr_row14_col12_bnk16_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk16_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk16_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row15_col12_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk16_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk16_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk16_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row16_col12_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk16_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk16_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk16_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk16_mrank3_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk16_mrank2_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk16_mrank1_3 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row17_col12_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk16_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk16_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk16_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk16_mrank3_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk16_mrank2_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk16_mrank1_3 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk16_mrank3_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk16_mrank2_3 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk16_mrank1_2 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); ############################################# MRANK bits Col = 12 , banks = 8 define def_mcb_addr_row14_col12_bnk8_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk8_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk8_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row14_col12_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); define def_mcb_addr_row15_col12_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk8_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk8_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row15_col12_bnk8_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); define def_mcb_addr_row16_col12_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk8_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk8_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk8_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk8_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk8_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row16_col12_bnk8_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); define def_mcb_addr_row17_col12_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk8_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk8_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk8_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk8_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk8_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk8_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk8_mrank3_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk8_mrank2_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); define def_mcb_addr_row17_col12_bnk8_mrank1_3 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); # ADDRESS setup for different SCHMOO setting define def_mcb_addr_total28_max28 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 28 )); define def_mcb_addr_total28_max29 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 28 )); define def_mcb_addr_total28_max30 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 28 )); define def_mcb_addr_total28_max31 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 28 )); define def_mcb_addr_total27_max27 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 27 )); define def_mcb_addr_total27_max28 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 27 )); define def_mcb_addr_total27_max29 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 27 )); define def_mcb_addr_total27_max30 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 27 )); define def_mcb_addr_total26_max26 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 26 )); define def_mcb_addr_total26_max27 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 26 )); define def_mcb_addr_total26_max28 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 26 )); define def_mcb_addr_total26_max29 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 26 )); define def_mcb_addr_total25_max25 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 25 )); define def_mcb_addr_total25_max26 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 25 )); define def_mcb_addr_total25_max27 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 25 )); define def_mcb_addr_total25_max28 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 25 )); define def_mcb_addr_total24_max24 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 24 )); define def_mcb_addr_total24_max25 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 24 )); define def_mcb_addr_total24_max26 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 24 )); define def_mcb_addr_total24_max27 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 24 )); define def_mcb_addr_total23_max23 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 23 )); define def_mcb_addr_total23_max24 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 23 )); define def_mcb_addr_total23_max25 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 23 )); define def_mcb_addr_total23_max26 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 23 )); define def_mcb_addr_total22_max22 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 )); define def_mcb_addr_total22_max23 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 )); define def_mcb_addr_total22_max24 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 )); define def_mcb_addr_total22_max25 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 )); ####################################### # MBA01_MBA_MBAREFAQ Base Address: 0x03010436 # MBA23_MBA_MBAREFAQ Base Address: 0x03010c36 ####################################### scom 0x03010436 { bits , scom_data , ATTR_FUNCTIONAL, expr; # 0:63 , 0xE1FFFFC421020C00 , 1 , any; #Enable Dynamic Refresh Avoidance with coef2 0:63 , 0x6591B48421021400 , 1 , any; #Old Default settings to turn off Dynamic refresh avoidance } ####################################### # MBA01_MBA_RRQ0Q Base Address: 0x0301040E # MBA23_MBA_RRQ0Q Base Address: 0x03010C0E ####################################### scom 0x0301040E { bits , scom_data , ATTR_FUNCTIONAL, expr; 57 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_PAGE_MODE_FOR_RRQ == 1); # Enable Page Mode for the Read Reorder Queue } #Register Name Final Arb Parms #Mnemonic MBA_FARB0Q #Attributes PAR:EVEN Bit Field Mnemonic Attribute or Setting to use #Description FARB command control #1. FARB0 bit 38: cfg_parity_after_cmd # - set this bit if DDR3 and (RDIMM or LDRIMM) # - clear this bit if DDR4 and (RDIMM or LDRIMM) #2. FARB0 bit 60: cfg_ignore_rcd_parity_err # - clear this bit if (RDIMM or LDRIMM) #3. FARB0 bit 61: cfg_enable_rcd_rw_retry # - set this bit if (RDIMM or LDRIMM) scom 0x03010413 { bits , scom_data , ATTR_FUNCTIONAL, expr; 38 , 0b1 , 1 , (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_GEN == 1)); 38 , 0b0 , 1 , (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_GEN == 2)); 60 , 0b0 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)); 61 , 0b1 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)); } ####################################### #MBA01 MBASRQ Base Address: 0x03010416 #MBA23 MBASRQ Base Address: 0x03010C16 ####################################### # #Register Name N/M Throttling Control #Mnemonic MBA_FARB3Q #Attributes PAR:EVEN Bit Field Mnemonic Attribute or Setting to use #Description N/M throttling control (Centaur only) # 0:14 cfg_nm_n_per_mba MSS_MEM_THROTTLE_NUMERATOR_PER_MBA # 15:30 cfg_nm_n_per_chip MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP # 31:44 cfg_nm_m MSS_MEM_THROTTLE_DENOMINATOR # 51 cfg_nm_per_slot_enabled 1 # 52 cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else #cfg_nm_ras_weight, bits 45:47 = ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT #cfg_nm_cas_weight, bits 48:50 = ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT scom 0x03010416 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:14 , ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA , 1 , any; # cfg_nm_n_per_mba MSS_MEM_THROTTLE_NUMERATOR_PER_MBA 15:30 , ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP , 1 , any; # cfg_nm_n_per_chip MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP 31:44 , ATTR_MSS_MEM_THROTTLE_DENOMINATOR , 1 , any; # cfg_nm_m MSS_MEM_THROTTLE_DENOMINATOR 45:47 , ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT , 1 , any; # cfg_nm_ras_weight 48:50 , ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT , 1 , any; # cfg_nm_cas_weight 51 , 0b0 , 1 , (ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1); # cfg_nm_per_slot_enabled Set to 0 for CDIMM, Set to 1 for everything else 51 , 0b1 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 0)) || (ATTR_EFF_DIMM_TYPE == 3)); # cfg_nm_per_slot_enabled Set to 0 for CDIMM, Set to 1 for everything else 52 , 0b0 , 1 , (ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 1); # cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else 52 , 0b1 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 0)) || (ATTR_EFF_DIMM_TYPE == 3)); # cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else 53 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_NM_CHANGE_AFTER_SYNC == 1); # cfg_nm_change_after_sync } #Register Name N/M Throttling Control #Mnemonic MBA_FARB4Q #Attributes PAR:EVEN Bit Field Mnemonic Attribute or Setting to use #Description N/M throttling control (Centaur only) #MBA_FARB4Q(0:1) cfg_rhmr_en 01 Track only (only FIRs will go off, signaling when a block would have occurred) #MBA_FARB4Q(2) cfg_rhmr_secondary_en 0 Secondary Structure disabled (this is for repair sequence) #MBA_FARB4Q(3) cfg_rhmr_hash_swizzle_en 0 Disable swizzling hash (so we don't switch which rows correspond to which counters) #MBA_FARB4Q(4:9) Reserved 000000 Don't Care #MBA_FARB4Q(10:11) cfg_rhmr_decrement_weight 01 Decrement by 1 (minimum weight) #MBA_FARB4Q(12:18) cfg_rhmr_primary_decr_intv 1111111 Slowest rate of decrements. Once ever 2^14 or 16K DRAM clocks* #MBA_FARB4Q(12:18) cfg_rhmr_primary_decr_intv 0000011 decrement every 512 DRAM clocks for 100K accesses to hash group #MBA_FARB4Q(19:25) cfg_rhmr_secondary_decr_intv 0000000 Don't care #MBA_FARB4Q(26) cfg_rhmr_sim_en 0 Disable sim mode # -- bits 27:41 (cfg_emer_n) = ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP # -- bits 42:55 (cfg_emer_m) = ATTR_MRW_MEM_THROTTLE_DENOMINATOR #*I think this corresponds to protecting a row from being hammered 64K times. scom 0x03010417 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:1 , 0b00 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); # disable row hammer permanently eventhough attribute says enable it 2 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); 3 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); 4:9 , 0b000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); 10:11 , 0b01 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); 12:18 , 0b0000011 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); 19:25 , 0b0000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); 26 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); 27:41 , SYS.ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, 1 , (ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE == 1); 42:55 , SYS.ATTR_MRW_MEM_THROTTLE_DENOMINATOR , 1 , (ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE == 1); } # ATTR_EFF_DIMM_TYPE # CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3 ################################### # TRACE_TRCTRL_CONFIG MBA01 Trace Control Configuration Register # # HW259719 - lcl_clk_gate_ctrl needs to be turned on and left on # DD2 fixed ONLY ################################### scom 0x03010882 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:63 , 0x000C000000000000 , 1 , (CENTAUR.ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl # 12:13 , 0b11 , 1 , (CENTAUR.ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl } ################################### # Turn on DDR PHY clks ################################### # Name = MBA01.MBA_MCBIST.SCOMFIR.CCS_MODEQ_Q(0:63) (scomdef) # Turn on DDR phy clk p and n scom 0x030106A7 { bits , scom_data , ATTR_FUNCTIONAL, expr; 4:5 , 0b01 , 1 , any; # ddr_dphy_nclk 00 = off , 01 = on 6:7 , 0b10 , 1 , any; # ddr_dphy_pclk 00 = off , 10 = on 51 , 0b0 , 1 , ATTR_EFF_DRAM_GEN != 2; # set ACT signal to 0 for DDR3 51 , 0b1 , 1 , ATTR_EFF_DRAM_GEN == 2; # set ACT signal to 1 for DDR4 52 , 0b1 , 1 , any; # RAS# high 53 , 0b1 , 1 , any; # CAS# high 54 , 0b1 , 1 , any; # WE# high } ################################### # MBA chip select mapping tables # ################################### # Name = MBA01.FARB.FARB_CS (scomdef) # MBA_FARB1Q Slot0, Master Rank 0/2 chip select programming # scom 0x03010414 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:5 , 0b011100, 1 , (def_C3b == 1); # cfg_M0S0_cs 0:5 , 0b011100, 1 , (def_C3c == 1); # cfg_M0S0_cs 0:5 , 0b010000, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S0_cs 0:5 , 0b010100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S0_cs 0:5 , 0b011100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S0_cs 0:5 , 0b010000, 1 , (def_IS3b_IS7b == 1); # cfg_M0S0_cs 0:5 , 0b010000, 1 , (def_IS5D == 1); # cfg_M0S0_cs 0:5 , 0b010000, 1 , (def_IS7C == 1); # cfg_M0S0_cs 0:5 , 0b011100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S0_cs 6:11 , 0b101100, 1 , (def_C3b == 1); # cfg_M0S1_cs 6:11 , 0b101100, 1 , (def_C3c == 1); # cfg_M0S1_cs 6:11 , 0b011000, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S1_cs 6:11 , 0b011100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S1_cs 6:11 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S1_cs 6:11 , 0b011000, 1 , (def_IS3b_IS7b == 1); # cfg_M0S1_cs 6:11 , 0b011000, 1 , (def_IS5D == 1); # cfg_M0S1_cs 6:11 , 0b011000, 1 , (def_IS7C == 1); # cfg_M0S1_cs 6:11 , 0b110100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S1_cs 12:17 , 0b110100, 1 , (def_C3b == 1); # cfg_M0S2_cs 12:17 , 0b110100, 1 , (def_C3c == 1); # cfg_M0S2_cs 12:17 , 0b010100, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S2_cs 12:17 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S2_cs 12:17 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S2_cs 12:17 , 0b010100, 1 , (def_IS3b_IS7b == 1); # cfg_M0S2_cs 12:17 , 0b010100, 1 , (def_IS5D == 1); # cfg_M0S2_cs 12:17 , 0b010100, 1 , (def_IS7C == 1); # cfg_M0S2_cs 12:17 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S2_cs 18:23 , 0b111000, 1 , (def_C3b == 1); # cfg_M0S3_cs 18:23 , 0b111000, 1 , (def_C3c == 1); # cfg_M0S3_cs 18:23 , 0b011100, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S3_cs 18:23 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S3_cs 18:23 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S3_cs 18:23 , 0b011100, 1 , (def_IS3b_IS7b == 1); # cfg_M0S3_cs 18:23 , 0b011100, 1 , (def_IS5D == 1); # cfg_M0S3_cs 18:23 , 0b011100, 1 , (def_IS7C == 1); # cfg_M0S3_cs 18:23 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S3_cs 24:29 , 0b111100, 1 , (def_C3b == 1); # cfg_M0S4_cs 24:29 , 0b011110, 1 , (def_C3c == 1); # cfg_M0S4_cs 24:29 , 0b010001, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S4_cs 24:29 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S4_cs 24:29 , 0b110100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S4_cs 24:29 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M0S4_cs 24:29 , 0b100000, 1 , (def_IS5D == 1); # cfg_M0S4_cs 24:29 , 0b010010, 1 , (def_IS7C == 1); # cfg_M0S4_cs 24:29 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S4_cs 30:35 , 0b111100, 1 , (def_C3b == 1); # cfg_M0S5_cs 30:35 , 0b101110, 1 , (def_C3c == 1); # cfg_M0S5_cs 30:35 , 0b011001, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S5_cs 30:35 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S5_cs 30:35 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S5_cs 30:35 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M0S5_cs 30:35 , 0b101000, 1 , (def_IS5D == 1); # cfg_M0S5_cs 30:35 , 0b011010, 1 , (def_IS7C == 1); # cfg_M0S5_cs 30:35 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S5_cs 36:41 , 0b111100, 1 , (def_C3b == 1); # cfg_M0S6_cs 36:41 , 0b110110, 1 , (def_C3c == 1); # cfg_M0S6_cs 36:41 , 0b010101, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S6_cs 36:41 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S6_cs 36:41 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S6_cs 36:41 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M0S6_cs 36:41 , 0b100100, 1 , (def_IS5D == 1); # cfg_M0S6_cs 36:41 , 0b010110, 1 , (def_IS7C == 1); # cfg_M0S6_cs 36:41 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S6_cs 42:47 , 0b111100, 1 , (def_C3b == 1); # cfg_M0S7_cs 42:47 , 0b111010, 1 , (def_C3c == 1); # cfg_M0S7_cs 42:47 , 0b011101, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S7_cs 42:47 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S7_cs 42:47 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S7_cs 42:47 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M0S7_cs 42:47 , 0b101100, 1 , (def_IS5D == 1); # cfg_M0S7_cs 42:47 , 0b011110, 1 , (def_IS7C == 1); # cfg_M0S7_cs 42:47 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S7_cs 48:51 , 0b1111, 1 , (def_C3b == 1); # cfg_cs_s0_mask 48:51 , 0b1111, 1 , (def_C3c == 1); # cfg_cs_s0_mask 48:51 , 0b1100, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_cs_s0_mask 48:51 , 0b1101, 1 , (def_C4A_ddr4 == 1); # cfg_cs_s0_mask 48:51 , 0b1111, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_cs_s0_mask 48:51 , 0b1100, 1 , (def_IS3b_IS7b == 1); # cfg_cs_s0_mask 48:51 , 0b1100, 1 , (def_IS5D == 1); # cfg_cs_s0_mask 48:51 , 0b1100, 1 , (def_IS7C == 1); # cfg_cs_s0_mask 48:51 , 0b1111, 1 , (def_IS7a_C4a_C3a == 1); # cfg_cs_s0_mask 52 , 0b0 , 1 , (def_C3b == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR 52 , 0b0 , 1 , (def_C3c == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR 52 , 0b0 , 1 , (def_C3c_C4C_ddr4 == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR 52 , 0b0 , 1 , (def_C4A_ddr4 == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR 52 , 0b0 , 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR 52 , 0b0 , 1 , (def_IS3b_IS7b == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR 52 , 0b1 , 1 , (def_IS5D == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR 52 , 0b0 , 1 , (def_IS7C == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR 52 , 0b0 , 1 , (def_IS7a_C4a_C3a == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR } # MBA_FARB2Q Slot0, Master Rank 1/3 chip select programming # scom 0x03010415 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:5 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S0_cs 0:5 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S0_cs 0:5 , 0b100000, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S0_cs 0:5 , 0b100100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S0_cs 0:5 , 0b101100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S0_cs 0:5 , 0b100000, 1 , (def_IS3b_IS7b == 1); # cfg_M1S0_cs 0:5 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S0_cs 0:5 , 0b100000, 1 , (def_IS7C == 1); # cfg_M1S0_cs 0:5 , 0b101100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S0_cs 6:11 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S1_cs 6:11 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S1_cs 6:11 , 0b101000, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S1_cs 6:11 , 0b101100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S1_cs 6:11 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S1_cs 6:11 , 0b101000, 1 , (def_IS3b_IS7b == 1); # cfg_M1S1_cs 6:11 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S1_cs 6:11 , 0b101000, 1 , (def_IS7C == 1); # cfg_M1S1_cs 6:11 , 0b111000, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S1_cs 12:17 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S2_cs 12:17 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S2_cs 12:17 , 0b100100, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S2_cs 12:17 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S2_cs 12:17 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S2_cs 12:17 , 0b100100, 1 , (def_IS3b_IS7b == 1); # cfg_M1S2_cs 12:17 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S2_cs 12:17 , 0b100100, 1 , (def_IS7C == 1); # cfg_M1S2_cs 12:17 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S2_cs 18:23 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S3_cs 18:23 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S3_cs 18:23 , 0b101100, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S3_cs 18:23 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S3_cs 18:23 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S3_cs 18:23 , 0b101100, 1 , (def_IS3b_IS7b == 1); # cfg_M1S3_cs 18:23 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S3_cs 18:23 , 0b101100, 1 , (def_IS7C == 1); # cfg_M1S3_cs 18:23 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S3_cs 24:29 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S4_cs 24:29 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S4_cs 24:29 , 0b100001, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S4_cs 24:29 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S4_cs 24:29 , 0b111000, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S4_cs 24:29 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M1S4_cs 24:29 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S4_cs 24:29 , 0b100010, 1 , (def_IS7C == 1); # cfg_M1S4_cs 24:29 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S4_cs 30:35 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S5_cs 30:35 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S5_cs 30:35 , 0b101001, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S5_cs 30:35 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S5_cs 30:35 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S5_cs 30:35 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M1S5_cs 30:35 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S5_cs 30:35 , 0b101010, 1 , (def_IS7C == 1); # cfg_M1S5_cs 30:35 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S5_cs 36:41 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S6_cs 36:41 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S6_cs 36:41 , 0b100101, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S6_cs 36:41 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S6_cs 36:41 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S6_cs 36:41 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M1S6_cs 36:41 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S6_cs 36:41 , 0b100110, 1 , (def_IS7C == 1); # cfg_M1S6_cs 36:41 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S6_cs 42:47 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S7_cs 42:47 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S7_cs 42:47 , 0b101101, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S7_cs 42:47 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S7_cs 42:47 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S7_cs 42:47 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M1S7_cs 42:47 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S7_cs 42:47 , 0b101110, 1 , (def_IS7C == 1); # cfg_M1S7_cs 42:47 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S7_cs } ########################### # MBA timer values # ########################### # eventually these timer settings will need to be generated from attributes # but for the 2/12 initfile these are coded the same as the ddr3_1600_10_10_10_2N dial for vbu testing # MBA_TMR0Q mba01 timer settings #< B0.C0.M00A.CENTAUR.MBU.MBA23.MBA_SRQ.MBA_TMR0Q(0:63) = 0x4479976DB5447445 #> B0.C0.M00A.CENTAUR.MBU.MBA23.MBA_SRQ.MBA_TMR0Q(0:63) = 0x4479996DB5447445 # scom 0x0301040B { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:3 , 0b0100 + def_margin2 , 1 , any; # RRSMSR_dly is 4 for all cfgs 1 D 4:7 , 0b0100 + def_margin2 , 1 , any; # RRSMDR_dly is 4 for all cfgs 2 D 8:11 , 0b0111 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 1066) || (CENTAUR.ATTR_MSS_FREQ == 1333) || (CENTAUR.ATTR_MSS_FREQ == 1600); # RRDM_dly 3 D 8:11 , 0b1000 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 1866) || (CENTAUR.ATTR_MSS_FREQ == 2133); # RRDM_dly 3 D 8:11 , 0b1001 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 2400); # RRDM_dly 3 D # fails will 0 margin 12:15 12:15 , 0b0111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWSMSR_dly 4 12:15 , 0b1000 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys8 == 1); # RWSMSR_dly 4 12:15 , 0b1001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys9 == 1); # RWSMSR_dly 4 12:15 , 0b1010 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys10 == 1); # RWSMSR_dly 4 12:15 , 0b1011 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys11 == 1); # RWSMSR_dly 4 12:15 , 0b1100 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys12 == 1); # RWSMSR_dly 4 12:15 , 0b1101 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys13 == 1); # RWSMSR_dly 4 12:15 , 0b1110 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys14 == 1); # RWSMSR_dly 4 12:15 , 0b1111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys15 == 1); # RWSMSR_dly 4 16:19 , 0b0111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWSMDR_dly 5 16:19 , 0b1000 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys8 == 1); # RWSMDR_dly 5 16:19 , 0b1001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys9 == 1); # RWSMDR_dly 5 16:19 , 0b1010 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys10 == 1); # RWSMDR_dly 5 16:19 , 0b1011 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys11 == 1); # RWSMDR_dly 5 16:19 , 0b1100 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys12 == 1); # RWSMDR_dly 5 16:19 , 0b1101 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys13 == 1); # RWSMDR_dly 5 16:19 , 0b1110 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys14 == 1); # RWSMDR_dly 5 16:19 , 0b1111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys15 == 1); # RWSMDR_dly 5 20:23 , 0b0111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWDM_dly 6 20:23 , 0b1000 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys8 == 1); # RWDM_dly 6 20:23 , 0b1001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys9 == 1); # RWDM_dly 6 20:23 , 0b1010 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys10 == 1); # RWDM_dly 6 20:23 , 0b1011 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys11 == 1); # RWDM_dly 6 20:23 , 0b1100 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys12 == 1); # RWDM_dly 6 20:23 , 0b1101 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys13 == 1); # RWDM_dly 6 20:23 , 0b1110 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys14 == 1); # RWDM_dly 6 20:23 , 0b1111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys15 == 1); # RWDM_dly 6 24:29 , 0b010011 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys19 == 1); # WRSMSR_dly 7 24:29 , 0b010100 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys20 == 1); # WRSMSR_dly 7 24:29 , 0b010101 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys21 == 1); # WRSMSR_dly 7 24:29 , 0b010111 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys23 == 1); # WRSMSR_dly 7 24:29 , 0b011000 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys24 == 1); # WRSMSR_dly 7 24:29 , 0b011001 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys25 == 1); # WRSMSR_dly 7 24:29 , 0b011010 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys26 == 1); # WRSMSR_dly 7 24:29 , 0b011011 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys27 == 1); # WRSMSR_dly 7 24:29 , 0b011100 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys28 == 1); # WRSMSR_dly 7 24:29 , 0b011101 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys29 == 1); # WRSMSR_dly 7 24:29 , 0b011110 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys30 == 1); # WRSMSR_dly 7 24:29 , 0b011111 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys31 == 1); # WRSMSR_dly 7 24:29 , 0b100000 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys32 == 1); # WRSMSR_dly 7 24:29 , 0b100001 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys33 == 1); # WRSMSR_dly 7 30:35 , 0b010111 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys23 == 1); # WRSMDR_dly 8 30:35 , 0b011000 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys24 == 1); # WRSMDR_dly 8 30:35 , 0b011001 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys25 == 1); # WRSMDR_dly 8 30:35 , 0b011010 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys26 == 1); # WRSMDR_dly 8 30:35 , 0b011011 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys27 == 1); # WRSMDR_dly 8 30:35 , 0b011100 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys28 == 1); # WRSMDR_dly 8 30:35 , 0b011101 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys29 == 1); # WRSMDR_dly 8 30:35 , 0b011110 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys30 == 1); # WRSMDR_dly 8 30:35 , 0b011111 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys31 == 1); # WRSMDR_dly 8 30:35 , 0b100000 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys32 == 1); # WRSMDR_dly 8 30:35 , 0b100001 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys33 == 1); # WRSMDR_dly 8 36:39 , 0b0100 + def_margin2 , 1 , (def_mba_tmr0q_WRDM_dlys4 == 1); # WRDM_dly 9 36:39 , 0b0101 + def_margin2 , 1 , (def_mba_tmr0q_WRDM_dlys5 == 1); # WRDM_dly 9 36:39 , 0b0110 + def_margin2 , 1 , (def_mba_tmr0q_WRDM_dlys6 == 1); # WRDM_dly 9 36:39 , 0b0111 + def_margin2 , 1 , (def_mba_tmr0q_WRDM_dlys7 == 1); # WRDM_dly 9 36:39 , 0b1000 + def_margin2 , 1 , (def_mba_tmr0q_WRDM_dlys8 == 1); # WRDM_dly 9 40:43 , 0b0100 + def_margin2 , 1 , any; # WWSMSR_dly is 4 for all cfgs 10 D 44:47 , 0b0100 + def_margin2 , 1 , any; # WWSMDR_dly is 4 for all cfgs 11 D 48:51 , 0b0111 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 1066) || (CENTAUR.ATTR_MSS_FREQ == 1333) || (CENTAUR.ATTR_MSS_FREQ == 1600); # WWDM_dly 12 D 48:51 , 0b1000 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 1866) || (CENTAUR.ATTR_MSS_FREQ == 2133); # WWDM_dly 12 D 48:51 , 0b1001 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 2400); # WWDM_dly 12 D 52:55 , 0b0100 + def_margin2 , 1 , any; # RROP_dly is 4 for all cfgs 13 D 56:59 , 0b0100 + def_margin2 , 1 , any; # WWOP_dly is 4 for all cfgs 14 D 60:63 , ATTR_EFF_DRAM_TRRD , 1 , any; # TMR0Q_Trrd } # MBA_TMR1Q mba01 timer settings # scom 0x0301040C { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:6 , 0b0011010 , 1 , (def_mba_tmr1q_cfg_trap26 == 1); # cfg_trap 16 0:6 , 0b0011011 , 1 , (def_mba_tmr1q_cfg_trap27 == 1); # cfg_trap 16 0:6 , 0b0011100 , 1 , (def_mba_tmr1q_cfg_trap28 == 1); # cfg_trap 16 0:6 , 0b0100000 , 1 , (def_mba_tmr1q_cfg_trap32 == 1); # cfg_trap 16 0:6 , 0b0100001 , 1 , (def_mba_tmr1q_cfg_trap33 == 1); # cfg_trap 16 0:6 , 0b0100101 , 1 , (def_mba_tmr1q_cfg_trap37 == 1); # cfg_trap 16 0:6 , 0b0100110 , 1 , (def_mba_tmr1q_cfg_trap38 == 1); # cfg_trap 16 0:6 , 0b0100111 , 1 , (def_mba_tmr1q_cfg_trap39 == 1); # cfg_trap 16 0:6 , 0b0101000 , 1 , (def_mba_tmr1q_cfg_trap40 == 1); # cfg_trap 16 0:6 , 0b0101010 , 1 , (def_mba_tmr1q_cfg_trap42 == 1); # cfg_trap 16 0:6 , 0b0101011 , 1 , (def_mba_tmr1q_cfg_trap43 == 1); # cfg_trap 16 0:6 , 0b0101100 , 1 , (def_mba_tmr1q_cfg_trap44 == 1); # cfg_trap 16 0:6 , 0b0101110 , 1 , (def_mba_tmr1q_cfg_trap46 == 1); # cfg_trap 16 7:13 , 0b0011110 , 1 , (def_mba_tmr1q_cfg_twap30 == 1); # cfg_twap 17 7:13 , 0b0100000 , 1 , (def_mba_tmr1q_cfg_twap32 == 1); # cfg_twap 17 7:13 , 0b0100010 , 1 , (def_mba_tmr1q_cfg_twap34 == 1); # cfg_twap 17 7:13 , 0b0100101 , 1 , (def_mba_tmr1q_cfg_twap37 == 1); # cfg_twap 17 7:13 , 0b0100111 , 1 , (def_mba_tmr1q_cfg_twap39 == 1); # cfg_twap 17 7:13 , 0b0101010 , 1 , (def_mba_tmr1q_cfg_twap42 == 1); # cfg_twap 17 7:13 , 0b0101100 , 1 , (def_mba_tmr1q_cfg_twap44 == 1); # cfg_twap 17 7:13 , 0b0101110 , 1 , (def_mba_tmr1q_cfg_twap46 == 1); # cfg_twap 17 7:13 , 0b0110000 , 1 , (def_mba_tmr1q_cfg_twap48 == 1); # cfg_twap 17 7:13 , 0b0110001 , 1 , (def_mba_tmr1q_cfg_twap49 == 1); # cfg_twap 17 7:13 , 0b0110011 , 1 , (def_mba_tmr1q_cfg_twap51 == 1); # cfg_twap 17 7:13 , 0b0110101 , 1 , (def_mba_tmr1q_cfg_twap53 == 1); # cfg_twap 17 14:19 , 0b0001111 , 1 , (ATTR_EFF_DRAM_TFAW == 16); # cfg_tfaw # HW278587 if tfaw is 16 set it to 15 14:19 , ATTR_EFF_DRAM_TFAW, 1 , (ATTR_EFF_DRAM_TFAW != 16); # cfg_tfaw # otherwise use the attribute value 20:23 , 0b0000 , 1 , (def_mba_tmr1q_RRSBG_dlys0 == 1); # RRSBG_dly 19 20:23 , 0b0101 , 1 , (def_mba_tmr1q_RRSBG_dlys5 == 1); # RRSBG_dly 19 20:23 , 0b0110 , 1 , (def_mba_tmr1q_RRSBG_dlys6 == 1); # RRSBG_dly 19 24:28 , 0b00000 , 1 , (def_mba_tmr1q_WRSBG_dlys0 == 1); # WRSBG_dly 20 24:28 , 0b11010 , 1 , (def_mba_tmr1q_WRSBG_dlys26 == 1); # WRSBG_dly 20 24:28 , 0b11011 , 1 , (def_mba_tmr1q_WRSBG_dlys27 == 1); # WRSBG_dly 20 24:28 , 0b11100 , 1 , (def_mba_tmr1q_WRSBG_dlys28 == 1); # WRSBG_dly 20 24:28 , 0b11101 , 1 , (def_mba_tmr1q_WRSBG_dlys29 == 1); # WRSBG_dly 20 24:28 , 0b11110 , 1 , (def_mba_tmr1q_WRSBG_dlys30 == 1); # WRSBG_dly 20 24:28 , 0b11111 , 1 , (def_mba_tmr1q_WRSBG_dlys31 == 1); # WRSBG_dly 20 # 24:28 , 0b00000 , 1 , (def_mba_tmr1q_WRSBG_dlys33 == 1); # WRSBG_dly ## 2133 and 2400 DRM not supported 20 # 24:28 , 0b00000 , 1 , (def_mba_tmr1q_WRSBG_dlys34 == 1); # WRSBG_dly ## 2133 and 2400 DRM not supported 20 # 24:28 , 0b00000 , 1 , (def_mba_tmr1q_WRSBG_dlys36 == 1); # WRSBG_dly ## 2133 and 2400 DRM not supported 20 # 24:28 , 0b00000 , 1 , (def_mba_tmr1q_WRSBG_dlys37 == 1); # WRSBG_dly ## 2133 and 2400 DRM not supported 20 } # 1333Mbps RDIMM WL = Setting + 7 = CWL + AL[CL-1] + 1= 16 #putscom cen.mba 301040a 30 6 001001 -ib -pall -call # 1600Mbps RDIMM WL = Setting + 7 = CWL + AL[CL-1] + 1= 19 #putscom cen.mba 301040a 30 6 001100 -ib -pall -call # 1333Mbps CDIMM WL = Setting + 7 = CWL + AL[CL-1] = 15 #putscom cen.mba 301040a 30 6 001000 -ib -pall -call # 1600Mbps CDIMM WL = Setting + 7 = CWL + AL[CL-1] = 18 #putscom cen.mba 301040a 30 6 001011 -ib -pall -call define def_WLO = ((ATTR_VPD_WLO[0] & 0x07) - (((ATTR_VPD_WLO[0] & 0x0F) >> 3) * 8)); define def_WL_AL0 = (ATTR_EFF_DRAM_CWL - 7); define def_WL_AL_MINUS1 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 1 - 7); define def_WL_AL_MINUS2 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 2 - 7); define def_RDODT_start_udimm = (ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_CWL + 1); define def_RDODT_start_rdimm = (ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_CWL + 2); define def_RDODT_start_lrdimm = (ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_CWL + 6); define def_RDODT_duration = (5); # MBA_DSM0Q mba01 data state machine settings #< B0.C0.M00A.CENTAUR.MBU.MBA01.MBA_SRQ.MBA_DSM0Q(0:63) = 0x0870466094038800 #> B0.C0.M00A.CENTAUR.MBU.MBA01.MBA_SRQ.MBA_DSM0Q(0:63) = 0x08704660A4838800 scom 0x0301040A { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:5 , def_RDODT_start_udimm , 1 , (ATTR_EFF_DIMM_TYPE == 2); # CFG_RODT_start_dly 21 0:5 , def_RDODT_start_rdimm , 1 , (ATTR_EFF_DIMM_TYPE == 1); # CFG_RODT_start_dly 21 0:5 , def_RDODT_start_lrdimm , 1 , (ATTR_EFF_DIMM_TYPE == 3); # CFG_RODT_start_dly 21 6:11 , def_RDODT_start_udimm + def_RDODT_duration , 1 , (ATTR_EFF_DIMM_TYPE == 2); # CFG_RODT_end_dly 22 6:11 , def_RDODT_start_rdimm + def_RDODT_duration , 1 , (ATTR_EFF_DIMM_TYPE == 1); # CFG_RODT_end_dly 22 6:11 , def_RDODT_start_lrdimm + def_RDODT_duration , 1 , (ATTR_EFF_DIMM_TYPE == 3); # CFG_RODT_end_dly 22 12:17 , 0b000000 , 1 , any; # CFG_WODT_start_dly is 0 for all cfgs 23 D 18:23 , 0b000101 , 1 , any; # CFG_WODT_end_dly is 5 for all cfgs 24 D 24:29 , 0b011000 , 1 , any; # wrdone_dly is 24 for all cfgs 25 D 30:35 , def_WL_AL0 + def_WLO , 1 , (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 0)); # wrdata_dly 30:35 , def_WL_AL0 , 1 , ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_DRAM_AL == 0)); # wrdata_dly 30:35 , def_WL_AL_MINUS1 + def_WLO , 1 , (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 1)); # wrdata_dly 30:35 , def_WL_AL_MINUS1 , 1 , ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_DRAM_AL == 1)); # wrdata_dly 30:35 , def_WL_AL_MINUS2 + def_WLO , 1 , (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 2)); # wrdata_dly 30:35 , def_WL_AL_MINUS2 , 1 , ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_DRAM_AL == 2)); # wrdata_dly 36:41 , 0b001100 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly12 == 1); # rdtag_dly 27 36:41 , 0b001101 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly13 == 1); # rdtag_dly 27 36:41 , 0b001110 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly14 == 1); # rdtag_dly 27 36:41 , 0b001111 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly15 == 1); # rdtag_dly 27 36:41 , 0b010000 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly16 == 1); # rdtag_dly 27 36:41 , 0b010001 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly17 == 1); # rdtag_dly 27 36:41 , 0b010010 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly18 == 1); # rdtag_dly 27 36:41 , 0b010011 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly19 == 1); # rdtag_dly 27 36:41 , 0b010100 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly20 == 1); # rdtag_dly 27 36:41 , 0b010101 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly21 == 1); # rdtag_dly 27 36:41 , 0b010110 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly22 == 1); # rdtag_dly 27 36:41 , 0b010111 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly23 == 1); # rdtag_dly 27 36:41 , 0b011000 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly24 == 1); # rdtag_dly 27 36:41 , 0b011001 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly25 == 1); # rdtag_dly 27 36:41 , 0b011010 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly26 == 1); # rdtag_dly 27 36:41 , 0b011011 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly27 == 1); # rdtag_dly 27 36:41 , 0b011100 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly28 == 1); # rdtag_dly 27 36:41 , 0b011101 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly29 == 1); # rdtag_dly 27 43:48 , def_RDODT_start_udimm + def_RDODT_duration - 2 , 1 , (ATTR_EFF_DIMM_TYPE == 2); # CFG_RODT_BC4_END_DLY 28 43:48 , def_RDODT_start_rdimm + def_RDODT_duration - 2 , 1 , (ATTR_EFF_DIMM_TYPE == 1); # CFG_RODT_BC4_END_DLY 28 43:48 , def_RDODT_start_lrdimm + def_RDODT_duration - 2 , 1 , (ATTR_EFF_DIMM_TYPE == 3); # CFG_RODT_BC4_END_DLY 28 49:54 , 0b000011 , 1 , any; # CFG_WODT_BC4_END_DLY is 3 for all cfgs 29 D } ## Refresh Interval Calculuation ## refresh_interval = ((ATTR_EFF_DRAM_TRFI/(def_num_ranks))/8); #define def_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); define def_mba01_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1]); define def_mba23_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); define def_mba01_refresh_interval = ((ATTR_EFF_DRAM_TRFI)/(8*def_mba01_num_ranks)); define def_mba23_refresh_interval = ((ATTR_EFF_DRAM_TRFI)/(8*def_mba23_num_ranks)); # mulitply by 1.1 to give it 10% margin define def_refresh_check_interval = ((ATTR_EFF_DRAM_TRFI/8) + ((ATTR_EFF_DRAM_TRFI/8)/10)); # same for both mba01 and mba23 # MBAREF0Q mba01 refresh settings # scom 0x03010432 { bits , scom_data , ATTR_FUNCTIONAL, expr; 4:7 , 0b0111 , 1 , any; # MBAREF0Q_refresh priority threshold is 0x7 for all cfgs 30 ?# refresh interval = tREFI(7.8) / # ranks per port / DRAM clk(ns) / 0.008 8:18 , def_mba01_refresh_interval, 1 , ATTR_CHIP_UNIT_POS == 0; # see calculation above 8:18 , def_mba23_refresh_interval, 1 , ATTR_CHIP_UNIT_POS == 1; # see calculation above 19:29 , 0b00011000010, 1 , any; # MBAREF0Q_refresh reset interval set to 194 decimal 32 ? !!FIXME 30:39 , ATTR_EFF_DRAM_TRFC, 1 , any; # MBAREF0Q_cfg_trfc 33 40:49 , 0b0000100000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly32 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 40:49 , 0b0000110000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly48 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 40:49 , 0b0001000000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly64 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 50:60 , def_refresh_check_interval, 1 , any; # MBAREF0Q_refresh check intveral set to 780 decimal 35 } # MBAPC0Q power control settings reg 1 # scom 0x03010434 { bits , scom_data , ATTR_FUNCTIONAL, expr; 2 , 0b0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 0); # cfg_min_max_domains 36 2 , 0b1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED != 0); # cfg_min_max_domains 36 # 3:5 , 0b001 , 1 , any; # cfg_min_max_domains 36 6:10 , 0b00100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail - performance enhancemnt 6:10 , 0b00011 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail - performance enhancemnt 6:10 , 0b00101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b00100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b00110 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b00101 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b00111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b00110 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b01000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b00111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b01101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b01100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b10000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b01111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b10100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b10011 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b10111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b10110 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b11010 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b11001 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b11101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 6:10 , 0b11100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 11:15 , 0b00011 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly3 == 1); # MBARPC0Q_cfg_pup_pup 37 11:15 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly4 == 1); # MBARPC0Q_cfg_pup_pup 37 11:15 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly5 == 1); # MBARPC0Q_cfg_pup_pup 37 11:15 , 0b00110 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly6 == 1); # MBARPC0Q_cfg_pup_pup 37 16:20 , 0b00011 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly3 == 1); # MBARPC0Q_cfg_pup_pdn 38 16:20 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly4 == 1); # MBARPC0Q_cfg_pup_pdn 38 16:20 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly5 == 1); # MBARPC0Q_cfg_pup_pdn 38 16:20 , 0b00110 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly6 == 1); # MBARPC0Q_cfg_pup_pdn 38 22 , 0b0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 0); 22 , 0b1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED != 0); 23:32 , 0b0000000011, 1 , any; # Set min doman reduction time to 30.7 us (10.245us * 3) 42 , 0b1 , 1 , any; # Force SpareCKE sync 43 , 0b1 , 1 , any; # Use 1 in 8k 2:1 cycle pulses for min domain reduction time interval } # had to shifts the data to be able to get it into the proper positions define shift_pwr_map1 = (ATTR_VPD_CKE_PWR_MAP >> 60); define shift_pwr_map2 = (ATTR_VPD_CKE_PWR_MAP >> 56); define shift_pwr_map3 = (ATTR_VPD_CKE_PWR_MAP >> 52); define shift_pwr_map4 = (ATTR_VPD_CKE_PWR_MAP >> 48); define shift_pwr_map5 = (ATTR_VPD_CKE_PWR_MAP >> 44); define shift_pwr_map6 = (ATTR_VPD_CKE_PWR_MAP >> 40); define shift_pwr_map7 = (ATTR_VPD_CKE_PWR_MAP >> 36); define shift_pwr_map8 = (ATTR_VPD_CKE_PWR_MAP >> 32); define shift_pwr_map9 = (ATTR_VPD_CKE_PWR_MAP >> 28); define shift_pwr_map10 = (ATTR_VPD_CKE_PWR_MAP >> 24); define shift_pwr_map11 = (ATTR_VPD_CKE_PWR_MAP >> 20); define shift_pwr_map12 = (ATTR_VPD_CKE_PWR_MAP >> 16); define shift_pwr_map13 = (ATTR_VPD_CKE_PWR_MAP >> 12); define shift_pwr_map14 = (ATTR_VPD_CKE_PWR_MAP >> 8); define shift_pwr_map15 = (ATTR_VPD_CKE_PWR_MAP >> 4); # MBAPC1Q power control settings reg 1 # scom 0x03010435 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:3 , shift_pwr_map1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk0_rd_cke 36 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 0:3 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 0:3 , 0x9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 0:3 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 0:3 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); # cfg_mrnk0_rd_cke 36 4:7 , shift_pwr_map2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 4:7 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk1_rd_cke 36 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 4:7 , 0xE , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 4:7 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 4:7 , 0x5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 4:7 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 4:7 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 4:7 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 4:7 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 4:7 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); 8:11 , shift_pwr_map3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk2_rd_cke 36 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 8:11 , 0x9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 8:11 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 8:11 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 8:11 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 8:11 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 8:11 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); 12:15 , shift_pwr_map4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk3_rd_cke 36 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 12:15 , 0x5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 12:15 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 12:15 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 12:15 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 12:15 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 12:15 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); 16:19 , shift_pwr_map5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk4_rd_cke 36 16:19 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 16:19 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 16:19 , 0xA , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 16:19 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 16:19 , 0x3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 16:19 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 16:19 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 16:19 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 16:19 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); 20:23 , shift_pwr_map6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk5_rd_cke 36 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 20:23 , 0xB , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 20:23 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 20:23 , 0x9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 20:23 , 0x3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 20:23 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 20:23 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 20:23 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 20:23 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); } scom 0x03010435 { bits , scom_data , ATTR_FUNCTIONAL, expr; 24:27 , shift_pwr_map7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk6_rd_cke 37 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 24:27 , 0xA , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 24:27 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 24:27 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 24:27 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); 28:31 , shift_pwr_map8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk7_rd_cke 37 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 28:31 , 0x9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 28:31 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 28:31 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 28:31 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); 32:35 , shift_pwr_map9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk0_wr_cke 38 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 32:35 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 32:35 , 0xA , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 32:35 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 32:35 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 32:35 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 32:35 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 32:35 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 36:39 , shift_pwr_map10, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 32:35 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); # cfg_mrnk0_wr_cke 38 36:39 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); 36:39 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 36:39 , 0xE , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 36:39 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 36:39 , 0x6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 36:39 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 36:39 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 36:39 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 36:39 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 36:39 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 36:39 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 36:39 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 36:39 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 36:39 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); 40:43 , shift_pwr_map11, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk2_wr_cke 38 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 40:43 , 0xA , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 40:43 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 40:43 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 40:43 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 40:43 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 40:43 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); 44:47 , shift_pwr_map12, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk3_wr_cke 38 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 44:47 , 0x6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 44:47 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 44:47 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 44:47 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 44:47 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 44:47 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); } scom 0x03010435 { bits , scom_data , ATTR_FUNCTIONAL, expr; 48:51 , shift_pwr_map13, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk4_wr_cke 38 48:51 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 48:51 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 48:51 , 0x6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 48:51 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 48:51 , 0x3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 48:51 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 48:51 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 48:51 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 48:51 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); 52:55 , shift_pwr_map14, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk5_wr_cke 38 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 52:55 , 0xB , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 52:55 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 52:55 , 0x5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 52:55 , 0x3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 52:55 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 52:55 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 52:55 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 52:55 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); 56:59 , shift_pwr_map15, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk6_wr_cke 38 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 56:59 , 0x6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 56:59 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 56:59 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 56:59 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); 60:63 , ATTR_VPD_CKE_PWR_MAP, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk7_wr_cke 38 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); 60:63 , 0x5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); 60:63 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); 60:63 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); 60:63 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); } ########################### # MBA CKE mapping tables # ########################### # use prim map A for 1b, 1c # MBAREF1Q MBA01 Rank-to-primary-CKE mapping table # scom 0x03010433 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:15 , ATTR_VPD_CKE_PRI_MAP[0], 1 , any; # from VPD now 16:31 , ATTR_VPD_CKE_PRI_MAP[1], 1 , any; # from VPD now } #define def_zqcal_timebase_in_ms=(16384*(1/CENTAUR.ATTR_MSS_FREQ)*.001) define def_zq_intv_sel10 = (ATTR_EFF_ZQCAL_INTERVAL / 16384); define def_zq_intv_sel11 = (ATTR_EFF_ZQCAL_INTERVAL / 16777216); #define def_memcal_timebase_in_ms=(16384*(1/CENTAUR.ATTR_MSS_FREQ)*.001) define def_mem_intv_sel10 = (ATTR_EFF_MEMCAL_INTERVAL / 16384); define def_mem_intv_sel11 = (ATTR_EFF_MEMCAL_INTERVAL / 16777216); # ATTR_EFF_MEMCAL_INTERVAL are in clock cycles # ATTR_EFF_ZQCAL_INTERVAL are in clock cycles #ATTR_EFF_MEMCAL_INTERVAL u32 0x027b9fba #ATTR_EFF_ZQCAL_INTERVAL u32 0x008798a # MBA_CAL0Q (this timer to be used for zq cal) # scom 0x0301040F { bits , scom_data , ATTR_FUNCTIONAL, expr; 0 , 0b0 , 1 , any; #disable timer initially 1:2 , 0b10 , 1 , (def_zq_intv_sel10 < 512); #timebase; use 16384 cycle timebase if less than max of 512 1:2 , 0b11 , 1 , (def_zq_intv_sel10 > 511); #timebase; use 16777216 cycle timebase if greater than max of 512 3:11 , def_zq_intv_sel10, 1 , (def_zq_intv_sel10 < 512); #interval timer; computed using zq cal interval attribute; zq_intv=zq_cal_interval_attr/zqcal_timebase_in_ms (assumes attribute defined in milliseconds) 3:11 , 0b000000001 , 1 , (def_zq_intv_sel10 > 511) && (def_zq_intv_sel11 == 0); #interval timer; computed using zq cal interval attribute; zq_intv=zq_cal_interval_attr/zqcal_timebase_in_ms (assumes attribute defined in milliseconds) 3:11 , def_zq_intv_sel11, 1 , (def_zq_intv_sel10 > 511) && (def_zq_intv_sel11 > 0); #interval timer; computed using zq cal interval attribute; zq_intv=zq_cal_interval_attr/zqcal_timebase_in_ms (assumes attribute defined in milliseconds) 12 , 0b1 , 1 , any; #enable for type1 13:16 , 0b0100 , 1 , any; #select external zq cal for type1 17 , 0b1 , 1 , any; #wait for done from DDR for type1 18 , 0b0 , 1 , any; #disable type2 timer 19:22 , 0b0000 , 1 , any; #type2 cal type 23 , 0b0 , 1 , any; #disable type2 done 24 , 0b0 , 1 , any; #disable type3 timer 25:28 , 0b0000 , 1 , any; #type3 cal type 29 , 0b0 , 1 , any; #disable type3 done 30:38 , 0b000000000 , 1 , any; #set timer to 0 for z sync 39:46 , 0b01000000 , 1 , any; #reset tmr 47:48 , 0b00 , 1 , any; #reset tb 49 , 0b0 , 1 , any; #disable for soft reset on cal timeout 50 , 0b1 , 1 , any; #use single rank mode 51 , 0b0 , 1 , any; #cal0_pare_err 52 , 0b0 , 1 , any; #1hot_sm_err 53:55 , 0b000 , 1 , any; #cal_single_port_mode off 56:63 , 0b00000000 , 1 , any; #reserved } # MBA_CAL1Q (this timer to be used for mem cal) # scom 0x03010410 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0 , 0b0 , 1 , any; #disable timer initially 1:2 , 0b10 , 1 , (def_mem_intv_sel10 < 512); #timebase; use 16384 cycle timebase if less than max of 512 1:2 , 0b11 , 1 , (def_mem_intv_sel10 > 511); #timebase; use 16777216 cycle timebase if greater than max of 512 3:11 , def_mem_intv_sel10 , 1 , (def_mem_intv_sel10 < 512); #interval timer; computed using zq cal interval attribute; mem_intv=mem_cal_interval_attr/memcal_timebase_in_ms (assumes attribute defined in milliseconds) 3:11 , 0b000000001 , 1 , (def_mem_intv_sel10 > 511) && (def_mem_intv_sel11 == 0); #interval timer; computed using zq cal interval attribute; mem_intv=mem_cal_interval_attr/memcal_timebase_in_ms (assumes attribute defined in milliseconds) 3:11 , def_mem_intv_sel11 , 1 , (def_mem_intv_sel10 > 511) && (def_mem_intv_sel11 > 0); #interval timer; computed using zq cal interval attribute; mem_intv=mem_cal_interval_attr/memcal_timebase_in_ms (assumes attribute defined in milliseconds) 12 , 0b1 , 1 , any; #enable for type1 13:16 , 0b0011 , 1 , any; #select Periodic Calbration: Run SysClk, DQS and Read Eye all in parallel for type 17 , 0b1 , 1 , any; #wait for done from DDR for type1 18 , 0b0 , 1 , any; #disable type2 timer 19:22 , 0b0000 , 1 , any; #type2 cal type 23 , 0b0 , 1 , any; #disable type2 done 24 , 0b0 , 1 , any; #disable type3 timer 25:28 , 0b0000 , 1 , any; #type3 cal type 29 , 0b0 , 1 , any; #disable type3 done 30:38 , 0b000000000 , 1 , any; #set timer to 0 for z sync 39 , 0b0 , 1 , any; #use single rank mode 40:63 , 0b000000000000000000000000 , 1 , any; #reserved to 0 } # MBA_CAL3Q (this timer to be used for mem cal) # scom 0x03010412 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:1 , 0b11 , 1 , any; #cfg_internal_zq_tb RW Internal ZQ time base 2:9 , 0b11111111 , 1 , any; #cfg_internal_zq_length RW Number of internal ZQ time bases required to meet max internal zq length 10:11 , 0b11 , 1 , any; #cfg_external_zq_tb RW External ZQ time base 12:19 , 0b11111111 , 1 , any; #cfg_external_zq_length RW Number of external ZQ time bases required to meet max external zq length 20:21 , 0b11 , 1 , any; #cfg_rdclk_sysclk_tb RW Readclk/Sysclk time base 22:29 , 0b11111111 , 1 , any; #cfg_rdclk_sysclk_length RW Number of Readclk/sysclk time bases required to meet max rdclk length 30:31 , 0b11 , 1 , any; #cfg_dqs_alignment_tb RW Dqs alignment time base 32:39 , 0b11111111 , 1 , any; #cfg_dqs_alignment_length RW Number of Dqs alignment time bases required to meet max dqs alignment length 40:41 , 0b11 , 1 , any; #cfg_mpr_readeye_tb RW Readeye time base 42:49 , 0b11111111 , 1 , any; #cfg_mpr_readeye_length RW Number of readeye time bases required to meet max external zq length 50:51 , 0b11 , 1 , any; #cfg_all_periodic_tb RW All Periodics time base 52:59 , 0b11111111 , 1 , any; #cfg_all_periodic_length RW Number of all_periodic time bases required to meet max calibration length for all periodic calibration ( in parallel ) } ########################################################################################### # MBA MCBIST SETUP SECTION # ########################################################################################### ################################### # MCBIST Memory Register ################################### # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBMR0Q_Q(0:63) (scomdef) # Setup subtest tests # Setup subtest 0 is a write with fixed data # Setup subtest 1 is a read with fixed data scom 0x030106A8 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:2 , 0b000, 1 ,any; # cfg_test00_op_type is a write 3 , 0b0, 1 ,any; # cfg_test00_compl_1st_cmd 4 , 0b0, 1 ,any; # cfg_test00_compl_2nd_cmd 5 , 0b0, 1 ,any; # cfg_test00_compl_3rd_cmd 6:7 , 0b00, 1 ,any; # cfg_test00_addr_mode 8:10 , 0b000, 1 ,any; # cfg_test00_data_mode 11 , 0b0 , 1 ,any; # cfg_test00_done 12:13 , 0b00, 1 ,any; # cfg_test00_data_sel 14:15 , 0b00, 1 ,any; # cfg_test00_addr_sel 16:18 , 0b001, 1 ,any; # cfg_test01_op_type is a read 19 , 0b0, 1 ,any; # cfg_test01_compl_1st_cmd 20 , 0b0, 1 ,any; # cfg_test01_compl_2nd_cmd 21 , 0b0, 1 ,any; # cfg_test01_compl_3rd_cmd 22:23 , 0b00, 1 ,any; # cfg_test01_addr_mode 24:26 , 0b000, 1 ,any; # cfg_test01_data_mode 27 , 0b1 , 1 ,any; # cfg_test01_done is set 28:29 , 0b00, 1 ,any; # cfg_test01_data_sel 30:31 , 0b00, 1 ,any; # cfg_test01_addr_sel 32:34 , 0b000, 1 ,any; # cfg_test02_op_type 35 , 0b0, 1 ,any; # cfg_test02_compl_1st_cmd 36 , 0b0, 1 ,any; # cfg_test02_compl_2nd_cmd 37 , 0b0, 1 ,any; # cfg_test02_compl_3rd_cmd 38:39 , 0b00, 1 ,any; # cfg_test02_addr_mode 40:42 , 0b000, 1 ,any; # cfg_test02_data_mode 43 , 0b0 , 1 ,any; # cfg_test02_done 44:45 , 0b00, 1 ,any; # cfg_test02_data_sel 46:47 , 0b00, 1 ,any; # cfg_test02_addr_sel 48:50 , 0b000, 1 ,any; # cfg_test03_op_type 51 , 0b0, 1 ,any; # cfg_test03_compl_1st_cmd 52 , 0b0, 1 ,any; # cfg_test03_compl_2nd_cmd 53 , 0b0, 1 ,any; # cfg_test03_compl_3rd_cmd 54:55 , 0b00, 1 ,any; # cfg_test03_addr_mode 56:58 , 0b000, 1 ,any; # cfg_test03_data_mode 59 , 0b0 , 1 ,any; # cfg_test03_done 60:61 , 0b00, 1 ,any; # cfg_test03_data_sel 62:63 , 0b00, 1 ,any; # cfg_test03_addr_sel } ################################### # MCBIST Fixed data pattern ################################### # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFD[0-7]Q_Q(0:63) (scomdef) # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDQ_Q(0:63) (scomdef) # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDSPQ_Q(0:63) (scomdef) scom 0x030106BE { bits , scom_data , ATTR_FUNCTIONAL ,expr; 0:63 , 0x1111111111111111, 1 ,any; # Fixed data burst 0 } scom 0x030106BF { bits , scom_data , ATTR_FUNCTIONAL ,expr; 0:63 , 0x2222222222222222, 1 ,any; # Fixed data burst 1 } scom 0x030106C0 { bits , scom_data , ATTR_FUNCTIONAL ,expr; 0:63 , 0x3333333333333333, 1 ,any; # Fixed data burst 2 } scom 0x030106C1 { bits , scom_data , ATTR_FUNCTIONAL ,expr; 0:63 , 0x4444444444444444, 1 ,any; # Fixed data burst 3 } scom 0x030106C2 { bits , scom_data , ATTR_FUNCTIONAL ,expr; 0:63 , 0x5555555555555555, 1 ,any; # Fixed data burst 4 } scom 0x030106C3 { bits , scom_data , ATTR_FUNCTIONAL ,expr; 0:63 , 0x6666666666666666, 1 ,any; # Fixed data burst 5 } scom 0x030106C4 { bits , scom_data , ATTR_FUNCTIONAL ,expr; 0:63 , 0x7777777777777777, 1 ,any; # Fixed data burst 6 } scom 0x030106C5 { bits , scom_data , ATTR_FUNCTIONAL ,expr; 0:63 , 0x8888888888888888, 1 ,any; # Fixed data burst 7 } scom 0x030106C6 { bits , scom_data , ATTR_FUNCTIONAL ,expr; 0:63 , 0x9999999999999999, 1 ,any; # Fixed data burst 0-7 ECC bits } scom 0x030106C7 { bits , scom_data , ATTR_FUNCTIONAL ,expr; 0:63 , 0xAAAAAAAAAAAAAAAA, 1 ,any; # Fixed data burst 0-7 SPARE bits } ################################### # MCBIST Fixed Addr A0 Start/End ################################### # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBSAARA0Q_Q (scomdef) # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBSEARA0Q_Q (scomdef) # scom 0x030106D0 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:35 , 0x000000000 , 1 , any; # A0 start address 36:37 , 0b00 , 1 , any; # A0 start address } scom 0x030106D2 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:3 , 0x0 , 1 , any ; # A0 End address 4:15 , 0xFFF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total22_max22) ; # A0 End address 4:15 , 0x7FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total23_max23) ||(def_mcb_addr_total22_max23) ; # A0 End address 4:15 , 0x3FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total24_max24) ||(def_mcb_addr_total23_max24) ||(def_mcb_addr_total22_max24) ; # A0 End address 4:15 , 0x1FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total25_max25) ||(def_mcb_addr_total24_max25) ||(def_mcb_addr_total23_max25) ||(def_mcb_addr_total22_max25) ; # A0 End address 4:15 , 0x0FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total26_max26) ||(def_mcb_addr_total25_max26) ||(def_mcb_addr_total24_max26) ||(def_mcb_addr_total23_max26) ; # A0 End address 4:15 , 0x07F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total27_max27) ||(def_mcb_addr_total26_max27) ||(def_mcb_addr_total25_max27) ||(def_mcb_addr_total24_max27) ; # A0 End address 4:15 , 0x03F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total28_max28) ||(def_mcb_addr_total27_max28) ||(def_mcb_addr_total26_max28) ||(def_mcb_addr_total25_max28) ||(def_mcb_addr_total28_max29) ; # A0 End address 4:15 , 0x01F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total27_max29) ||(def_mcb_addr_total26_max29) ; # A0 End address 4:15 , 0x00F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total28_max30) ||(def_mcb_addr_total27_max30) ; # A0 End address 4:15 , 0x007 , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total28_max31) ; # A0 End address 4:15 , 0x7FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total22_max22) ; # A0 End address 4:15 , 0x3FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total23_max23) ||(def_mcb_addr_total22_max23) ; # A0 End address 4:15 , 0x1FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total24_max24) ||(def_mcb_addr_total23_max24) ||(def_mcb_addr_total22_max24) ; # A0 End address 4:15 , 0x0FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total25_max25) ||(def_mcb_addr_total24_max25) ||(def_mcb_addr_total23_max25) ||(def_mcb_addr_total22_max25) ; # A0 End address 4:15 , 0x07F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total26_max26) ||(def_mcb_addr_total25_max26) ||(def_mcb_addr_total24_max26) ||(def_mcb_addr_total23_max26) ; # A0 End address 4:15 , 0x03F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total27_max27) ||(def_mcb_addr_total26_max27) ||(def_mcb_addr_total25_max27) ||(def_mcb_addr_total24_max27) ; # A0 End address 4:15 , 0x01F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total28_max28) ||(def_mcb_addr_total27_max28) ||(def_mcb_addr_total26_max28) ||(def_mcb_addr_total25_max28) ||(def_mcb_addr_total28_max29) ; # A0 End address 4:15 , 0x00F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total27_max29) ||(def_mcb_addr_total26_max29) ; # A0 End address 4:15 , 0x007 , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total28_max30) ||(def_mcb_addr_total27_max30) ; # A0 End address 4:15 , 0x003 , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total28_max31) ; # A0 End address 4:15 , 0x3FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total22_max22) ; # A0 End address 4:15 , 0x1FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total23_max23) ||(def_mcb_addr_total22_max23) ; # A0 End address 4:15 , 0x0FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total24_max24) ||(def_mcb_addr_total23_max24) ||(def_mcb_addr_total22_max24) ; # A0 End address 4:15 , 0x07F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total25_max25) ||(def_mcb_addr_total24_max25) ||(def_mcb_addr_total23_max25) ||(def_mcb_addr_total22_max25) ; # A0 End address 4:15 , 0x03F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total26_max26) ||(def_mcb_addr_total25_max26) ||(def_mcb_addr_total24_max26) ||(def_mcb_addr_total23_max26) ; # A0 End address 4:15 , 0x01F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total27_max27) ||(def_mcb_addr_total26_max27) ||(def_mcb_addr_total25_max27) ||(def_mcb_addr_total24_max27) ; # A0 End address 4:15 , 0x00F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total28_max28) ||(def_mcb_addr_total27_max28) ||(def_mcb_addr_total26_max28) ||(def_mcb_addr_total25_max28) ||(def_mcb_addr_total28_max29) ; # A0 End address 4:15 , 0x007 , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total27_max29) ||(def_mcb_addr_total26_max29) ; # A0 End address 4:15 , 0x003 , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total28_max30) ||(def_mcb_addr_total27_max30) ; # A0 End address 4:15 , 0x001 , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total28_max31) ; # A0 End address 4:15 , 0x000 , 1 , ((ATTR_EFF_SCHMOO_TEST_VALID != 1) || (ATTR_EFF_SCHMOO_TEST_VALID == 1 && ATTR_EFF_SCHMOO_ADDR_MODE == 0)); # A0 End address 16:35 , 0x00000 , 1 , ((ATTR_EFF_SCHMOO_TEST_VALID != 1) || (ATTR_EFF_SCHMOO_TEST_VALID == 1 && ATTR_EFF_SCHMOO_ADDR_MODE == 0)); # A0 End address 16:35 , 0xFFFFF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1 && ATTR_EFF_SCHMOO_ADDR_MODE != 0); # A0 End address 36:37 , 0b11 , 1 , any; # A0 End address } ################################### # MCBIST Addr Gen Cfg Reg ################################### # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBAGRAQ_Q (scomdef) # scom 0x030106D6 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:5 , 0b000000 , 1 , any; # A0 cfg_fixed_width_a0 24:25 , 0b10 , 1 , any; # A0 setup only A0 address gen } ###### ############################################ # MCBIST Port A Socket 0 Addr Map Reg 0 ############################################ # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBAMR0A0Q_Q (scomdef) # scom 0x030106C8 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:5 , 0b000000 , 1 , any ; #cfg_a0map_mrank0 Master Rank Bit 0 (MSB) 6:11 , 0b000000 , 1 , ((def_mcb_mrank1_unset) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 6:11 , 0b000010 , 1 , ((def_mcb_addr_row17_col12_bnk16_mrank1_2 ) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 6:11 , 0b000011 , 1 , (((def_mcb_addr_row17_col11_bnk16_mrank1_3 ) ||(def_mcb_addr_row16_col12_bnk16_mrank1_3 ) ||(def_mcb_addr_row17_col12_bnk16_mrank1_3 ) ||( def_mcb_addr_row17_col12_bnk8_mrank1_3 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 6:11 , 0b000100 , 1 , (((def_mcb_addr_row17_col10_bnk16_mrank1_4 ) ||(def_mcb_addr_row16_col11_bnk16_mrank1_4 ) ||(def_mcb_addr_row17_col11_bnk16_mrank1_4 ) ||(def_mcb_addr_row15_col12_bnk16_mrank1_4 ) ||(def_mcb_addr_row16_col12_bnk16_mrank1_4 ) ||(def_mcb_addr_row17_col12_bnk16_mrank1_4 ) ||( def_mcb_addr_row17_col11_bnk8_mrank1_4 ) ||( def_mcb_addr_row16_col12_bnk8_mrank1_4 ) ||( def_mcb_addr_row17_col12_bnk8_mrank1_4 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 6:11 , 0b000101 , 1 , (((def_mcb_addr_row16_col10_bnk16_mrank1_5 ) ||(def_mcb_addr_row17_col12_bnk16_mrank1_5 ) ||(def_mcb_addr_row17_col10_bnk16_mrank1_5 ) ||(def_mcb_addr_row15_col11_bnk16_mrank1_5 ) ||(def_mcb_addr_row16_col11_bnk16_mrank1_5 ) ||(def_mcb_addr_row17_col11_bnk16_mrank1_5 ) ||(def_mcb_addr_row14_col12_bnk16_mrank1_5 ) ||(def_mcb_addr_row15_col12_bnk16_mrank1_5 ) ||(def_mcb_addr_row16_col12_bnk16_mrank1_5 ) ||( def_mcb_addr_row17_col10_bnk8_mrank1_5 ) ||( def_mcb_addr_row16_col11_bnk8_mrank1_5 ) ||( def_mcb_addr_row17_col11_bnk8_mrank1_5 ) ||( def_mcb_addr_row15_col12_bnk8_mrank1_5 ) ||( def_mcb_addr_row16_col12_bnk8_mrank1_5 ) ||( def_mcb_addr_row17_col12_bnk8_mrank1_5 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 6:11 , 0b000110 , 1 , (((def_mcb_addr_row15_col10_bnk16_mrank1_6 ) ||(def_mcb_addr_row17_col11_bnk16_mrank1_6 )||(def_mcb_addr_row16_col12_bnk16_mrank1_6 )||( def_mcb_addr_row17_col12_bnk8_mrank1_6 ) ||(def_mcb_addr_row16_col10_bnk16_mrank1_6 ) ||(def_mcb_addr_row17_col10_bnk16_mrank1_6 ) ||(def_mcb_addr_row14_col11_bnk16_mrank1_6 ) ||(def_mcb_addr_row15_col11_bnk16_mrank1_6 ) ||(def_mcb_addr_row16_col11_bnk16_mrank1_6 ) ||(def_mcb_addr_row14_col12_bnk16_mrank1_6 ) ||(def_mcb_addr_row15_col12_bnk16_mrank1_6 ) ||( def_mcb_addr_row16_col10_bnk8_mrank1_6 ) ||( def_mcb_addr_row17_col10_bnk8_mrank1_6 ) ||( def_mcb_addr_row14_col11_bnk8_mrank1_6 ) ||( def_mcb_addr_row15_col11_bnk8_mrank1_6 ) ||( def_mcb_addr_row16_col11_bnk8_mrank1_6 ) ||( def_mcb_addr_row17_col11_bnk8_mrank1_6 ) ||( def_mcb_addr_row14_col12_bnk8_mrank1_6 ) ||( def_mcb_addr_row15_col12_bnk8_mrank1_6 ) ||( def_mcb_addr_row16_col12_bnk8_mrank1_6 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 6:11 , 0b000111 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank1_7 ) ||(def_mcb_addr_row17_col10_bnk16_mrank1_7 )||(def_mcb_addr_row16_col11_bnk16_mrank1_7 )||(def_mcb_addr_row15_col12_bnk16_mrank1_7 )||( def_mcb_addr_row17_col11_bnk8_mrank1_7 )||( def_mcb_addr_row16_col12_bnk8_mrank1_7 )||(def_mcb_addr_row15_col10_bnk16_mrank1_7 ) ||(def_mcb_addr_row16_col10_bnk16_mrank1_7 ) ||(def_mcb_addr_row14_col11_bnk16_mrank1_7 ) ||(def_mcb_addr_row15_col11_bnk16_mrank1_7 ) ||(def_mcb_addr_row14_col12_bnk16_mrank1_7 ) ||( def_mcb_addr_row15_col10_bnk8_mrank1_7 ) ||( def_mcb_addr_row16_col10_bnk8_mrank1_7 ) ||( def_mcb_addr_row17_col10_bnk8_mrank1_7 ) ||( def_mcb_addr_row15_col11_bnk8_mrank1_7 ) ||( def_mcb_addr_row16_col11_bnk8_mrank1_7 ) ||( def_mcb_addr_row14_col12_bnk8_mrank1_7 ) ||( def_mcb_addr_row15_col12_bnk8_mrank1_7 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 6:11 , 0b001000 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank1_8 ) ||(def_mcb_addr_row16_col10_bnk16_mrank1_8 )||(def_mcb_addr_row15_col11_bnk16_mrank1_8 )||(def_mcb_addr_row14_col12_bnk16_mrank1_8 )||( def_mcb_addr_row17_col10_bnk8_mrank1_8 )||( def_mcb_addr_row16_col11_bnk8_mrank1_8 )||( def_mcb_addr_row15_col12_bnk8_mrank1_8 ) ||(def_mcb_addr_row15_col10_bnk16_mrank1_8 ) ||(def_mcb_addr_row14_col11_bnk16_mrank1_8 ) ||( def_mcb_addr_row14_col10_bnk8_mrank1_8 ) ||( def_mcb_addr_row15_col10_bnk8_mrank1_8 ) ||( def_mcb_addr_row16_col10_bnk8_mrank1_8 ) ||( def_mcb_addr_row14_col11_bnk8_mrank1_8 ) ||( def_mcb_addr_row15_col11_bnk8_mrank1_8 ) ||( def_mcb_addr_row14_col12_bnk8_mrank1_8 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 6:11 , 0b001001 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank1_9 ) ||(def_mcb_addr_row15_col10_bnk16_mrank1_9 )||(def_mcb_addr_row14_col11_bnk16_mrank1_9 )||( def_mcb_addr_row16_col10_bnk8_mrank1_9 )||( def_mcb_addr_row15_col11_bnk8_mrank1_9 )||( def_mcb_addr_row14_col12_bnk8_mrank1_9 )||( def_mcb_addr_row14_col10_bnk8_mrank1_9 ) ||( def_mcb_addr_row15_col10_bnk8_mrank1_9 ) ||( def_mcb_addr_row14_col11_bnk8_mrank1_9 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 6:11 , 0b001010 , 1 , (((def_mcb_addr_row14_col10_bnk8_mrank1_10) ||(def_mcb_addr_row14_col10_bnk16_mrank1_10)||( def_mcb_addr_row15_col10_bnk8_mrank1_10)||( def_mcb_addr_row14_col11_bnk8_mrank1_10)) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 6:11 , 0b001011 , 1 , (( def_mcb_addr_row14_col10_bnk8_mrank1_11) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 } scom 0x030106C8 { bits , scom_data , ATTR_FUNCTIONAL, expr; 12:17 , 0b000000 , 1 , ((def_mcb_mrank2_unset)); #cfg_a0map_mrank2 Master Rank Rank Bit 2 12:17 , 0b000011 , 1 , ((def_mcb_addr_row17_col12_bnk16_mrank2_3 ) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 12:17 , 0b000100 , 1 , (((def_mcb_addr_row17_col11_bnk16_mrank2_4 ) ||(def_mcb_addr_row16_col12_bnk16_mrank2_4 ) ||(def_mcb_addr_row17_col12_bnk16_mrank2_4 ) ||( def_mcb_addr_row17_col12_bnk8_mrank2_4 )) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 12:17 , 0b000101 , 1 , (((def_mcb_addr_row17_col10_bnk16_mrank2_5 ) ||(def_mcb_addr_row16_col11_bnk16_mrank2_5 ) ||(def_mcb_addr_row17_col11_bnk16_mrank2_5 ) ||(def_mcb_addr_row15_col12_bnk16_mrank2_5 ) ||(def_mcb_addr_row16_col12_bnk16_mrank2_5 ) ||(def_mcb_addr_row17_col12_bnk16_mrank2_5 ) ||( def_mcb_addr_row17_col11_bnk8_mrank2_5 ) ||( def_mcb_addr_row16_col12_bnk8_mrank2_5 ) ||( def_mcb_addr_row17_col12_bnk8_mrank2_5 )) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 12:17 , 0b000110 , 1 , (((def_mcb_addr_row16_col10_bnk16_mrank2_6 ) ||(def_mcb_addr_row17_col12_bnk16_mrank2_6 ) ||(def_mcb_addr_row17_col10_bnk16_mrank2_6 ) ||(def_mcb_addr_row15_col11_bnk16_mrank2_6 ) ||(def_mcb_addr_row16_col11_bnk16_mrank2_6 ) ||(def_mcb_addr_row17_col11_bnk16_mrank2_6 ) ||(def_mcb_addr_row14_col12_bnk16_mrank2_6 ) ||(def_mcb_addr_row15_col12_bnk16_mrank2_6 ) ||(def_mcb_addr_row16_col12_bnk16_mrank2_6 ) ||( def_mcb_addr_row17_col10_bnk8_mrank2_6 ) ||( def_mcb_addr_row16_col11_bnk8_mrank2_6 ) ||( def_mcb_addr_row17_col11_bnk8_mrank2_6 ) ||( def_mcb_addr_row15_col12_bnk8_mrank2_6 ) ||( def_mcb_addr_row16_col12_bnk8_mrank2_6 ) ||( def_mcb_addr_row17_col12_bnk8_mrank2_6 )) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 12:17 , 0b000111 , 1 , (((def_mcb_addr_row15_col10_bnk16_mrank2_7 ) ||(def_mcb_addr_row17_col11_bnk16_mrank2_7 )||(def_mcb_addr_row16_col12_bnk16_mrank2_7 )||( def_mcb_addr_row17_col12_bnk8_mrank2_7 ) ||(def_mcb_addr_row16_col10_bnk16_mrank2_7 ) ||(def_mcb_addr_row17_col10_bnk16_mrank2_7 ) ||(def_mcb_addr_row14_col11_bnk16_mrank2_7 ) ||(def_mcb_addr_row15_col11_bnk16_mrank2_7 ) ||(def_mcb_addr_row16_col11_bnk16_mrank2_7 ) ||(def_mcb_addr_row14_col12_bnk16_mrank2_7 ) ||(def_mcb_addr_row15_col12_bnk16_mrank2_7 ) ||( def_mcb_addr_row16_col10_bnk8_mrank2_7 ) ||( def_mcb_addr_row17_col10_bnk8_mrank2_7 ) ||( def_mcb_addr_row14_col11_bnk8_mrank2_7 ) ||( def_mcb_addr_row15_col11_bnk8_mrank2_7 ) ||( def_mcb_addr_row16_col11_bnk8_mrank2_7 ) ||( def_mcb_addr_row17_col11_bnk8_mrank2_7 ) ||( def_mcb_addr_row14_col12_bnk8_mrank2_7 ) ||( def_mcb_addr_row15_col12_bnk8_mrank2_7 ) ||( def_mcb_addr_row16_col12_bnk8_mrank2_7 )) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 12:17 , 0b001000 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank2_8 ) ||(def_mcb_addr_row17_col10_bnk16_mrank2_8 )||(def_mcb_addr_row16_col11_bnk16_mrank2_8 )||(def_mcb_addr_row15_col12_bnk16_mrank2_8 )||( def_mcb_addr_row17_col11_bnk8_mrank2_8 )||( def_mcb_addr_row16_col12_bnk8_mrank2_8 ) ||(def_mcb_addr_row15_col10_bnk16_mrank2_8 ) ||(def_mcb_addr_row16_col10_bnk16_mrank2_8 ) ||(def_mcb_addr_row14_col11_bnk16_mrank2_8 ) ||(def_mcb_addr_row15_col11_bnk16_mrank2_8 ) ||(def_mcb_addr_row14_col12_bnk16_mrank2_8 ) ||( def_mcb_addr_row15_col10_bnk8_mrank2_8 ) ||( def_mcb_addr_row16_col10_bnk8_mrank2_8 ) ||( def_mcb_addr_row17_col10_bnk8_mrank2_8 ) ||( def_mcb_addr_row15_col11_bnk8_mrank2_8 ) ||( def_mcb_addr_row16_col11_bnk8_mrank2_8 ) ||( def_mcb_addr_row14_col12_bnk8_mrank2_8 ) ||( def_mcb_addr_row15_col12_bnk8_mrank2_8 )) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 12:17 , 0b001001 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank2_9 ) ||(def_mcb_addr_row16_col10_bnk16_mrank2_9 )||(def_mcb_addr_row15_col11_bnk16_mrank2_9 )||(def_mcb_addr_row14_col12_bnk16_mrank2_9 )||( def_mcb_addr_row17_col10_bnk8_mrank2_9 )||( def_mcb_addr_row16_col11_bnk8_mrank2_9 ) ||( def_mcb_addr_row15_col12_bnk8_mrank2_9 ) ||(def_mcb_addr_row15_col10_bnk16_mrank2_9 ) ||(def_mcb_addr_row14_col11_bnk16_mrank2_9 ) ||( def_mcb_addr_row14_col10_bnk8_mrank2_9 ) ||( def_mcb_addr_row15_col10_bnk8_mrank2_9 ) ||( def_mcb_addr_row16_col10_bnk8_mrank2_9 ) ||( def_mcb_addr_row14_col11_bnk8_mrank2_9 ) ||( def_mcb_addr_row15_col11_bnk8_mrank2_9 ) ||( def_mcb_addr_row14_col12_bnk8_mrank2_9 )) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 12:17 , 0b001010 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank2_10) ||(def_mcb_addr_row15_col10_bnk16_mrank2_10)||(def_mcb_addr_row14_col11_bnk16_mrank2_10)||( def_mcb_addr_row16_col10_bnk8_mrank2_10)||( def_mcb_addr_row15_col11_bnk8_mrank2_10)||( def_mcb_addr_row14_col12_bnk8_mrank2_10) ||( def_mcb_addr_row14_col10_bnk8_mrank2_10) ||( def_mcb_addr_row15_col10_bnk8_mrank2_10) ||( def_mcb_addr_row14_col11_bnk8_mrank2_10)) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 12:17 , 0b001011 , 1 , (((def_mcb_addr_row14_col10_bnk8_mrank2_11) ||(def_mcb_addr_row14_col10_bnk16_mrank2_11)||( def_mcb_addr_row15_col10_bnk8_mrank2_11)||( def_mcb_addr_row14_col11_bnk8_mrank2_11)) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 12:17 , 0b001100 , 1 , (( def_mcb_addr_row14_col10_bnk8_mrank2_12) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 } scom 0x030106C8 { bits , scom_data , ATTR_FUNCTIONAL, expr; 18:23 , 0b000000 , 1 , ((def_mcb_mrank3_unset) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 18:23 , 0b000100 , 1 , ((def_mcb_addr_row17_col12_bnk16_mrank3_4 ) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 18:23 , 0b000101 , 1 , (((def_mcb_addr_row17_col11_bnk16_mrank3_5 ) ||(def_mcb_addr_row16_col12_bnk16_mrank3_5 ) ||(def_mcb_addr_row17_col12_bnk16_mrank3_5 ) ||( def_mcb_addr_row17_col12_bnk8_mrank3_5 )) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 18:23 , 0b000110 , 1 , (((def_mcb_addr_row17_col10_bnk16_mrank3_6 ) ||(def_mcb_addr_row16_col11_bnk16_mrank3_6 ) ||(def_mcb_addr_row17_col11_bnk16_mrank3_6 ) ||(def_mcb_addr_row15_col12_bnk16_mrank3_6 ) ||(def_mcb_addr_row16_col12_bnk16_mrank3_6 ) ||(def_mcb_addr_row17_col12_bnk16_mrank3_6 ) ||( def_mcb_addr_row17_col11_bnk8_mrank3_6 ) ||( def_mcb_addr_row16_col12_bnk8_mrank3_6 ) ||( def_mcb_addr_row17_col12_bnk8_mrank3_6 )) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 18:23 , 0b000111 , 1 , (((def_mcb_addr_row16_col10_bnk16_mrank3_7 ) ||(def_mcb_addr_row17_col12_bnk16_mrank3_7 ) ||(def_mcb_addr_row17_col10_bnk16_mrank3_7 ) ||(def_mcb_addr_row15_col11_bnk16_mrank3_7 ) ||(def_mcb_addr_row16_col11_bnk16_mrank3_7 ) ||(def_mcb_addr_row17_col11_bnk16_mrank3_7 ) ||(def_mcb_addr_row14_col12_bnk16_mrank3_7 ) ||(def_mcb_addr_row15_col12_bnk16_mrank3_7 ) ||(def_mcb_addr_row16_col12_bnk16_mrank3_7 ) ||( def_mcb_addr_row17_col10_bnk8_mrank3_7 ) ||( def_mcb_addr_row16_col11_bnk8_mrank3_7 ) ||( def_mcb_addr_row17_col11_bnk8_mrank3_7 ) ||( def_mcb_addr_row15_col12_bnk8_mrank3_7 ) ||( def_mcb_addr_row16_col12_bnk8_mrank3_7 ) ||( def_mcb_addr_row17_col12_bnk8_mrank3_7 )) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 18:23 , 0b001000 , 1 , (((def_mcb_addr_row15_col10_bnk16_mrank3_8 ) ||(def_mcb_addr_row17_col11_bnk16_mrank3_8 )||(def_mcb_addr_row16_col12_bnk16_mrank3_8 )||( def_mcb_addr_row17_col12_bnk8_mrank3_8 ) ||(def_mcb_addr_row16_col10_bnk16_mrank3_8 ) ||(def_mcb_addr_row17_col10_bnk16_mrank3_8 ) ||(def_mcb_addr_row14_col11_bnk16_mrank3_8 ) ||(def_mcb_addr_row15_col11_bnk16_mrank3_8 ) ||(def_mcb_addr_row16_col11_bnk16_mrank3_8 ) ||(def_mcb_addr_row14_col12_bnk16_mrank3_8 ) ||(def_mcb_addr_row15_col12_bnk16_mrank3_8 ) ||( def_mcb_addr_row16_col10_bnk8_mrank3_8 ) ||( def_mcb_addr_row17_col10_bnk8_mrank3_8 ) ||( def_mcb_addr_row14_col11_bnk8_mrank3_8 ) ||( def_mcb_addr_row15_col11_bnk8_mrank3_8 ) ||( def_mcb_addr_row16_col11_bnk8_mrank3_8 ) ||( def_mcb_addr_row17_col11_bnk8_mrank3_8 ) ||( def_mcb_addr_row14_col12_bnk8_mrank3_8 ) ||( def_mcb_addr_row15_col12_bnk8_mrank3_8 ) ||( def_mcb_addr_row16_col12_bnk8_mrank3_8 )) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 18:23 , 0b001001 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank3_9 ) ||(def_mcb_addr_row17_col10_bnk16_mrank3_9 )||(def_mcb_addr_row16_col11_bnk16_mrank3_9 )||(def_mcb_addr_row15_col12_bnk16_mrank3_9 )||( def_mcb_addr_row17_col11_bnk8_mrank3_9 )||( def_mcb_addr_row16_col12_bnk8_mrank3_9 ) ||(def_mcb_addr_row15_col10_bnk16_mrank3_9 ) ||(def_mcb_addr_row16_col10_bnk16_mrank3_9 ) ||(def_mcb_addr_row14_col11_bnk16_mrank3_9 ) ||(def_mcb_addr_row15_col11_bnk16_mrank3_9 ) ||(def_mcb_addr_row14_col12_bnk16_mrank3_9 ) ||( def_mcb_addr_row15_col10_bnk8_mrank3_9 ) ||( def_mcb_addr_row16_col10_bnk8_mrank3_9 ) ||( def_mcb_addr_row17_col10_bnk8_mrank3_9 ) ||( def_mcb_addr_row15_col11_bnk8_mrank3_9 ) ||( def_mcb_addr_row16_col11_bnk8_mrank3_9 ) ||( def_mcb_addr_row14_col12_bnk8_mrank3_9 ) ||( def_mcb_addr_row15_col12_bnk8_mrank3_9 )) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 18:23 , 0b001010 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank3_10) ||(def_mcb_addr_row16_col10_bnk16_mrank3_10)||(def_mcb_addr_row15_col11_bnk16_mrank3_10)||(def_mcb_addr_row14_col12_bnk16_mrank3_10)||( def_mcb_addr_row17_col10_bnk8_mrank3_10)||( def_mcb_addr_row16_col11_bnk8_mrank3_10)||( def_mcb_addr_row15_col12_bnk8_mrank3_10) ||(def_mcb_addr_row15_col10_bnk16_mrank3_10) ||(def_mcb_addr_row14_col11_bnk16_mrank3_10) ||( def_mcb_addr_row14_col10_bnk8_mrank3_10) ||( def_mcb_addr_row15_col10_bnk8_mrank3_10) ||( def_mcb_addr_row16_col10_bnk8_mrank3_10) ||( def_mcb_addr_row14_col11_bnk8_mrank3_10) ||( def_mcb_addr_row15_col11_bnk8_mrank3_10) ||( def_mcb_addr_row14_col12_bnk8_mrank3_10)) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 18:23 , 0b001011 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank3_11) ||(def_mcb_addr_row15_col10_bnk16_mrank3_11)||(def_mcb_addr_row14_col11_bnk16_mrank3_11)||( def_mcb_addr_row16_col10_bnk8_mrank3_11)||( def_mcb_addr_row15_col11_bnk8_mrank3_11)||( def_mcb_addr_row14_col12_bnk8_mrank3_11) ||( def_mcb_addr_row14_col10_bnk8_mrank3_11) ||( def_mcb_addr_row15_col10_bnk8_mrank3_11) ||( def_mcb_addr_row14_col11_bnk8_mrank3_11)) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 18:23 , 0b001100 , 1 , (((def_mcb_addr_row14_col10_bnk8_mrank3_12) ||(def_mcb_addr_row14_col10_bnk16_mrank3_12)||( def_mcb_addr_row15_col10_bnk8_mrank3_12)||( def_mcb_addr_row14_col11_bnk8_mrank3_12)) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 18:23 , 0b001101 , 1 , (( def_mcb_addr_row14_col10_bnk8_mrank3_13) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 } scom 0x030106C8 { bits , scom_data , ATTR_FUNCTIONAL, expr; 24:29 , 0b000000 , 1 , ((def_mcb_srank0_unset) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) 24:29 , 0b000101 , 1 , ((def_mcb_addr_col12_bnk16_srank0_5 ) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) 24:29 , 0b000110 , 1 , (((def_mcb_addr_col11_bnk16_srank0_6 ) ||(def_mcb_addr_col12_bnk16_srank0_6 ) ||( def_mcb_addr_col12_bnk8_srank0_6 )) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) 24:29 , 0b000111 , 1 , (((def_mcb_addr_col10_bnk16_srank0_7 ) ||(def_mcb_addr_col11_bnk16_srank0_7 ) ||(def_mcb_addr_col12_bnk16_srank0_7 ) ||( def_mcb_addr_col11_bnk8_srank0_7 ) ||( def_mcb_addr_col12_bnk8_srank0_7 )) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) 24:29 , 0b001000 , 1 , (((def_mcb_addr_col10_bnk16_srank0_8 ) ||(def_mcb_addr_col11_bnk16_srank0_8 ) ||(def_mcb_addr_col12_bnk16_srank0_8 ) ||( def_mcb_addr_col10_bnk8_srank0_8 ) ||( def_mcb_addr_col11_bnk8_srank0_8 ) ||( def_mcb_addr_col12_bnk8_srank0_8 )) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) 24:29 , 0b001001 , 1 , (((def_mcb_addr_col10_bnk16_srank0_9 ) ||(def_mcb_addr_col11_bnk16_srank0_9 ) ||( def_mcb_addr_col10_bnk8_srank0_9 ) ||( def_mcb_addr_col11_bnk8_srank0_9 ) ||( def_mcb_addr_col12_bnk8_srank0_9 )) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) 24:29 , 0b001010 , 1 , ((( def_mcb_addr_col10_bnk8_srank0_10) ||( def_mcb_addr_col11_bnk8_srank0_10) ||(def_mcb_addr_col10_bnk16_srank0_10) ||( def_mcb_addr_col10_bnk8_srank0_11)) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) 30:35 , 0b000000 , 1 , ((def_mcb_srank1_unset) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 30:35 , 0b000110 , 1 , ((def_mcb_addr_col12_bnk16_srank1_6 ) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 30:35 , 0b000111 , 1 , (((def_mcb_addr_col11_bnk16_srank1_7 ) ||(def_mcb_addr_col12_bnk16_srank1_7 ) ||( def_mcb_addr_col12_bnk8_srank1_7 )) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 30:35 , 0b001000 , 1 , (((def_mcb_addr_col10_bnk16_srank1_8 ) ||(def_mcb_addr_col11_bnk16_srank1_8 ) ||(def_mcb_addr_col12_bnk16_srank1_8 ) ||( def_mcb_addr_col11_bnk8_srank1_8 ) ||( def_mcb_addr_col12_bnk8_srank1_8 )) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 30:35 , 0b001001 , 1 , (((def_mcb_addr_col10_bnk16_srank1_9 ) ||(def_mcb_addr_col11_bnk16_srank1_9 ) ||(def_mcb_addr_col12_bnk16_srank1_9 ) ||( def_mcb_addr_col10_bnk8_srank1_9 ) ||( def_mcb_addr_col11_bnk8_srank1_9 ) ||( def_mcb_addr_col12_bnk8_srank1_9 )) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 30:35 , 0b001010 , 1 , (((def_mcb_addr_col10_bnk16_srank1_10) ||(def_mcb_addr_col11_bnk16_srank1_10) ||( def_mcb_addr_col10_bnk8_srank1_10) ||( def_mcb_addr_col11_bnk8_srank1_10) ||( def_mcb_addr_col12_bnk8_srank1_10)) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 30:35 , 0b001011 , 1 , (((def_mcb_addr_col10_bnk16_srank1_11) ||( def_mcb_addr_col10_bnk8_srank1_11) ||( def_mcb_addr_col11_bnk8_srank1_11)) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 30:35 , 0b001100 , 1 , (( def_mcb_addr_col10_bnk8_srank1_12) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 } scom 0x030106C8 { bits , scom_data , ATTR_FUNCTIONAL, expr; 36:41 , 0b000000 , 1 , ((def_mcb_srank2_unset) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 36:41 , 0b000111 , 1 , ((def_mcb_addr_col12_bnk16_srank2_7 ) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 36:41 , 0b001000 , 1 , (((def_mcb_addr_col11_bnk16_srank2_8 ) ||(def_mcb_addr_col12_bnk16_srank2_8 ) ||( def_mcb_addr_col12_bnk8_srank2_8 )) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 36:41 , 0b001001 , 1 , (((def_mcb_addr_col10_bnk16_srank2_9 ) ||(def_mcb_addr_col11_bnk16_srank2_9 ) ||(def_mcb_addr_col12_bnk16_srank2_9 ) ||( def_mcb_addr_col11_bnk8_srank2_9 ) ||( def_mcb_addr_col12_bnk8_srank2_9 )) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 36:41 , 0b001010 , 1 , (((def_mcb_addr_col10_bnk16_srank2_10) ||(def_mcb_addr_col11_bnk16_srank2_10) ||(def_mcb_addr_col12_bnk16_srank2_10) ||( def_mcb_addr_col10_bnk8_srank2_10) ||( def_mcb_addr_col11_bnk8_srank2_10) ||( def_mcb_addr_col12_bnk8_srank2_10) ||(def_mcb_addr_col10_bnk16_srank2_11)) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 36:41 , 0b001011 , 1 , (((def_mcb_addr_col11_bnk16_srank2_11) ||( def_mcb_addr_col10_bnk8_srank2_11) ||( def_mcb_addr_col11_bnk8_srank2_11) ||( def_mcb_addr_col12_bnk8_srank2_11)) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 36:41 , 0b001100 , 1 , (((def_mcb_addr_col10_bnk16_srank2_12) ||( def_mcb_addr_col10_bnk8_srank2_12) ||( def_mcb_addr_col11_bnk8_srank2_12)) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 36:41 , 0b001101 , 1 , (( def_mcb_addr_col10_bnk8_srank2_13) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 42:47 , 0b011011 , 1 , (def_mcb_addr_bank3_27 == 1); #cfg_a0map_bank3 DRAM Bank Address Bit 3 (MSB) 42:47 , 0b011010 , 1 , (def_mcb_addr_bank3_26 == 1); #cfg_a0map_bank3 DRAM Bank Address Bit 3 (MSB) 42:47 , 0b011001 , 1 , (def_mcb_addr_bank3_25 == 1); #cfg_a0map_bank3 DRAM Bank Address Bit 3 (MSB) 42:47 , 0b000000 , 1 , (def_mcb_addr_unset_bank3 == 1); #cfg_a0map_bank3 DRAM Bank Address Bit 3 (MSB) 48:53 , 0b011100 , 1 , (def_mcb_addr_bank2_28 == 1); #cfg_a0map_bank2 DRAM Bank Address Bit 2 (MSB) 48:53 , 0b011011 , 1 , (def_mcb_addr_bank2_27 == 1); #cfg_a0map_bank2 DRAM Bank Address Bit 2 (MSB) 48:53 , 0b011010 , 1 , (def_mcb_addr_bank2_26 == 1); #cfg_a0map_bank2 DRAM Bank Address Bit 2 (MSB) 54:59 , 0b011101 , 1 , (def_mcb_addr_bank1_29 == 1); #cfg_a0map_bank1 DRAM Bank Address Bit 1 54:59 , 0b011100 , 1 , (def_mcb_addr_bank1_28 == 1); #cfg_a0map_bank1 DRAM Bank Address Bit 1 54:59 , 0b011011 , 1 , (def_mcb_addr_bank1_27 == 1); #cfg_a0map_bank1 DRAM Bank Address Bit 1 } scom 0x030106C9 { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:5 , 0b011110 , 1 , (def_mcb_addr_bank0_30 == 1); #cfg_a0map_bank0 DRAM Bank Address Bit 0 0:5 , 0b011101 , 1 , (def_mcb_addr_bank0_29 == 1); #cfg_a0map_bank0 DRAM Bank Address Bit 0 0:5 , 0b011100 , 1 , (def_mcb_addr_bank0_28 == 1); #cfg_a0map_bank0 DRAM Bank Address Bit 0 6:11 , 0b001011 , 1 , (def_mcb_addr_row16_11 == 1); #cfg_a0map_row16 DRAM Row Address Bit16 (MSB) 6:11 , 0b001010 , 1 , (def_mcb_addr_row16_10 == 1); #cfg_a0map_row16 DRAM Row Address Bit16 (MSB) 6:11 , 0b001001 , 1 , (def_mcb_addr_row16_9 == 1); #cfg_a0map_row16 DRAM Row Address Bit16 (MSB) 6:11 , 0b001000 , 1 , (def_mcb_addr_row16_8 == 1); #cfg_a0map_row16 DRAM Row Address Bit16 (MSB) 6:11 , 0b000000 , 1 , (def_mcb_addr_unset_row16 == 1); #cfg_a0map_row16 DRAM Row Address Bit16 (MSB) 12:17 , 0b001100 , 1 , (def_mcb_addr_row15_12 == 1); #cfg_a0map_row15 DRAM Row Address Bit15 12:17 , 0b001011 , 1 , (def_mcb_addr_row15_11 == 1); #cfg_a0map_row15 DRAM Row Address Bit15 12:17 , 0b001010 , 1 , (def_mcb_addr_row15_10 == 1); #cfg_a0map_row15 DRAM Row Address Bit15 12:17 , 0b001001 , 1 , (def_mcb_addr_row15_9 == 1); #cfg_a0map_row15 DRAM Row Address Bit15 12:17 , 0b000000 , 1 , (def_mcb_addr_unset_row15 == 1); #cfg_a0map_row15 DRAM Row Address Bit15 18:23 , 0b001101 , 1 , (def_mcb_addr_row14_13 == 1); #cfg_a0map_row14 DRAM Row Address Bit 14 18:23 , 0b001100 , 1 , (def_mcb_addr_row14_12 == 1); #cfg_a0map_row14 DRAM Row Address Bit 14 18:23 , 0b001011 , 1 , (def_mcb_addr_row14_11 == 1); #cfg_a0map_row14 DRAM Row Address Bit 14 18:23 , 0b001010 , 1 , (def_mcb_addr_row14_10 == 1); #cfg_a0map_row14 DRAM Row Address Bit 14 18:23 , 0b000000 , 1 , (def_mcb_addr_unset_row14 == 1); #cfg_a0map_row14 DRAM Row Address Bit 14 24:29 , 0b001110 , 1 , (def_mcb_addr_row13_14 == 1); #cfg_a0map_row13 DRAM Row Address Bit 13 24:29 , 0b001101 , 1 , (def_mcb_addr_row13_13 == 1); #cfg_a0map_row13 DRAM Row Address Bit 13 24:29 , 0b001100 , 1 , (def_mcb_addr_row13_12 == 1); #cfg_a0map_row13 DRAM Row Address Bit 13 24:29 , 0b001011 , 1 , (def_mcb_addr_row13_11 == 1); #cfg_a0map_row13 DRAM Row Address Bit 13 30:35 , 0b001111 , 1 , (def_mcb_addr_row12_15 == 1); #cfg_a0map_row12 DRAM Row Address Bit 12 30:35 , 0b001110 , 1 , (def_mcb_addr_row12_14 == 1); #cfg_a0map_row12 DRAM Row Address Bit 12 30:35 , 0b001101 , 1 , (def_mcb_addr_row12_13 == 1); #cfg_a0map_row12 DRAM Row Address Bit 12 30:35 , 0b001100 , 1 , (def_mcb_addr_row12_12 == 1); #cfg_a0map_row12 DRAM Row Address Bit 12 36:41 , 0b010000 , 1 , (def_mcb_addr_row11_16 == 1); #cfg_a0map_row11 DRAM Row Address Bit 11 36:41 , 0b001111 , 1 , (def_mcb_addr_row11_15 == 1); #cfg_a0map_row11 DRAM Row Address Bit 11 36:41 , 0b001110 , 1 , (def_mcb_addr_row11_14 == 1); #cfg_a0map_row11 DRAM Row Address Bit 11 36:41 , 0b001101 , 1 , (def_mcb_addr_row11_13 == 1); #cfg_a0map_row11 DRAM Row Address Bit 11 42:47 , 0b010001 , 1 , (def_mcb_addr_row10_17 == 1); #cfg_a0map_row10 DRAM Row Address Bit 10 42:47 , 0b010000 , 1 , (def_mcb_addr_row10_16 == 1); #cfg_a0map_row10 DRAM Row Address Bit 10 42:47 , 0b001111 , 1 , (def_mcb_addr_row10_15 == 1); #cfg_a0map_row10 DRAM Row Address Bit 10 42:47 , 0b001110 , 1 , (def_mcb_addr_row10_14 == 1); #cfg_a0map_row10 DRAM Row Address Bit 10 48:53 , 0b010010 , 1 , (def_mcb_addr_row9_18 == 1); #cfg_a0map_row9 DRAM Row Address Bit 9 48:53 , 0b010001 , 1 , (def_mcb_addr_row9_17 == 1); #cfg_a0map_row9 DRAM Row Address Bit 9 48:53 , 0b010000 , 1 , (def_mcb_addr_row9_16 == 1); #cfg_a0map_row9 DRAM Row Address Bit 9 48:53 , 0b001111 , 1 , (def_mcb_addr_row9_15 == 1); #cfg_a0map_row9 DRAM Row Address Bit 9 54:59 , 0b010011 , 1 , (def_mcb_addr_row8_19 == 1); #cfg_a0map_row8 DRAM Row Address Bit 8 54:59 , 0b010010 , 1 , (def_mcb_addr_row8_18 == 1); #cfg_a0map_row8 DRAM Row Address Bit 8 54:59 , 0b010001 , 1 , (def_mcb_addr_row8_17 == 1); #cfg_a0map_row8 DRAM Row Address Bit 8 54:59 , 0b010000 , 1 , (def_mcb_addr_row8_16 == 1); #cfg_a0map_row8 DRAM Row Address Bit 8 } scom 0x030106CA { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:5 , 0b010100 , 1 , (def_mcb_addr_row7_20 == 1); #cfg_a0map_row7 DRAM Row Address Bit 7 0:5 , 0b010011 , 1 , (def_mcb_addr_row7_19 == 1); #cfg_a0map_row7 DRAM Row Address Bit 7 0:5 , 0b010010 , 1 , (def_mcb_addr_row7_18 == 1); #cfg_a0map_row7 DRAM Row Address Bit 7 0:5 , 0b010001 , 1 , (def_mcb_addr_row7_17 == 1); #cfg_a0map_row7 DRAM Row Address Bit 7 6:11 , 0b010101 , 1 , (def_mcb_addr_row6_21 == 1); #cfg_a0map_row6 DRAM Row Address Bit 6 6:11 , 0b010100 , 1 , (def_mcb_addr_row6_20 == 1); #cfg_a0map_row6 DRAM Row Address Bit 6 6:11 , 0b010011 , 1 , (def_mcb_addr_row6_19 == 1); #cfg_a0map_row6 DRAM Row Address Bit 6 6:11 , 0b010010 , 1 , (def_mcb_addr_row6_18 == 1); #cfg_a0map_row6 DRAM Row Address Bit 6 12:17 , 0b010110 , 1 , (def_mcb_addr_row5_22 == 1); #cfg_a0map_row5 DRAM Row Address Bit 5 12:17 , 0b010101 , 1 , (def_mcb_addr_row5_21 == 1); #cfg_a0map_row5 DRAM Row Address Bit 5 12:17 , 0b010100 , 1 , (def_mcb_addr_row5_20 == 1); #cfg_a0map_row5 DRAM Row Address Bit 5 12:17 , 0b010011 , 1 , (def_mcb_addr_row5_19 == 1); #cfg_a0map_row5 DRAM Row Address Bit 5 18:23 , 0b010111 , 1 , (def_mcb_addr_row4_23 == 1); #cfg_a0map_row4 DRAM Row Address Bit 4 18:23 , 0b010110 , 1 , (def_mcb_addr_row4_22 == 1); #cfg_a0map_row4 DRAM Row Address Bit 4 18:23 , 0b010101 , 1 , (def_mcb_addr_row4_21 == 1); #cfg_a0map_row4 DRAM Row Address Bit 4 18:23 , 0b010100 , 1 , (def_mcb_addr_row4_20 == 1); #cfg_a0map_row4 DRAM Row Address Bit 4 24:29 , 0b011000 , 1 , (def_mcb_addr_row3_24 == 1); #cfg_a0map_row3 DRAM Row Address Bit 3 24:29 , 0b010111 , 1 , (def_mcb_addr_row3_23 == 1); #cfg_a0map_row3 DRAM Row Address Bit 3 24:29 , 0b010110 , 1 , (def_mcb_addr_row3_22 == 1); #cfg_a0map_row3 DRAM Row Address Bit 3 24:29 , 0b010101 , 1 , (def_mcb_addr_row3_21 == 1); #cfg_a0map_row3 DRAM Row Address Bit 3 30:35 , 0b011001 , 1 , (def_mcb_addr_row2_25 == 1); #cfg_a0map_row2 DRAM Row Address Bit 2 30:35 , 0b011000 , 1 , (def_mcb_addr_row2_24 == 1); #cfg_a0map_row2 DRAM Row Address Bit 2 30:35 , 0b010111 , 1 , (def_mcb_addr_row2_23 == 1); #cfg_a0map_row2 DRAM Row Address Bit 2 30:35 , 0b010110 , 1 , (def_mcb_addr_row2_22 == 1); #cfg_a0map_row2 DRAM Row Address Bit 2 36:41 , 0b011010 , 1 , (def_mcb_addr_row1_26 == 1); #cfg_a0map_row1 DRAM Row Address Bit 1 36:41 , 0b011001 , 1 , (def_mcb_addr_row1_25 == 1); #cfg_a0map_row1 DRAM Row Address Bit 1 36:41 , 0b011000 , 1 , (def_mcb_addr_row1_24 == 1); #cfg_a0map_row1 DRAM Row Address Bit 1 36:41 , 0b010111 , 1 , (def_mcb_addr_row1_23 == 1); #cfg_a0map_row1 DRAM Row Address Bit 1 42:47 , 0b011011 , 1 , (def_mcb_addr_row0_27 == 1); #cfg_a0map_row0 DRAM Row Address Bit 0 42:47 , 0b011010 , 1 , (def_mcb_addr_row0_26 == 1); #cfg_a0map_row0 DRAM Row Address Bit 0 42:47 , 0b011001 , 1 , (def_mcb_addr_row0_25 == 1); #cfg_a0map_row0 DRAM Row Address Bit 0 42:47 , 0b011000 , 1 , (def_mcb_addr_row0_24 == 1); #cfg_a0map_row0 DRAM Row Address Bit 0 48:53 , 0b000000 , 1 , (def_mcb_addr_unset_col13 == 1); #cfg_a0map_col13 DRAM Column Address Bit 13 (MSB) 48:53 , 0b011101 , 1 , (def_mcb_addr_col13_29 == 1); #cfg_a0map_col13 DRAM Column Address Bit 13 (MSB) 54:59 , 0b000000 , 1 , (def_mcb_addr_unset_col11 == 1); #cfg_a0map_col11 DRAM Column Address Bit 11 54:59 , 0b011110 , 1 , (def_mcb_addr_col11_30 == 1); #cfg_a0map_col11 DRAM Column Address Bit 11 } scom 0x030106CB { bits , scom_data , ATTR_FUNCTIONAL, expr; 0:5 , 0b011111 , 1 , any; #cfg_a0map_col9 DRAM Column Address Bit 9 6:11 , 0b100000 , 1 , any; #cfg_a0map_col8 DRAM Column Address Bit 8 12:17 , 0b100001 , 1 , any; #cfg_a0map_col7 DRAM Column Address Bit 7 18:23 , 0b100010 , 1 , any; #cfg_a0map_col6 DRAM Column Address Bit 6 24:29 , 0b100011 , 1 , any; #cfg_a0map_col5 DRAM Column Address Bit 5 30:35 , 0b100100 , 1 , any; #cfg_a0map_col4 DRAM Column Address Bit 4 36:41 , 0b100101 , 1 , any; #cfg_a0map_col3 DRAM Column Address Bit 3 # 42:47 , 0b100101 , 1 , any; #cfg_a0map_col2 DRAM Column Address Bit 2 Map to an Unused Address bit if NOT fixed BL= 4 42:47 , 0b000000 , 1 , any; #cfg_a0map_col2 DRAM Column Address Bit 2 Map to an Unused Address bit if NOT fixed BL= 4 }