#-- $Id: cen.dmi.scom.initfile,v 1.20 2013/12/04 17:43:33 jgrell Exp $ #################################################################### ## ## Auto-genrated by fig2scominit.pl ## Based on SETUP_ID_MODE DMI_BUS_TR_HW ## from ../../logic/mesa_sim/fusion/run/IODNC_MB_TOP.IODNC_MB_TOP.figdb ## ## Created on Tue Nov 26 11:34:19 CST 2013, by jgrell #################################################################### ## -- CHANGE HISTORY: ## -------------------------------------------------------------------------------- ## -- VersionID: |Author: | Date: | Comment: ## -- -----------|---------|--------|------------------------------------------------- ## -- jgr13112600| jgr |11-26-13| CYC rx_ds_timeout_sel setting changed to 111 ## -- jgr13102800| jgr |10-28-13| zcal address fix and rx_ds_timeout_sel change (110 -> 111) ## -- jgr13082100| jgr |08-21-13| Added tx_zcal inits so they can be removed from scan ## -- jfg13072400| jfg |07-24-13| HW253558: change pgooddly to MAX from lab feedback ## -- mbs13071200| mbs |07-12-13| Disable recal adjustment for allv1 (DFE bug) ## -- mbs13071100| mbs |07-11-13| Updates for HW239870 and HW258990 ## -- jgr13041800| jgr |04-18-13| Added rx_max_ber_check_count setting to 0x03 ## -- smr13032500| SMR |03-25-13| Changed rx_dyn_recal_overall_timeout_sel init to 0b100 & rx_sls_timeout_sel init to 0b110 ## -- jgr13031300| jgr |03-13-13| Added missing entries from rel 0128 ## -- mbs13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) ## -- mbs13011000| mbs |01-10-13| Added rx_prot_speed_slct and rx_c4_sel ## -- smr12112700| SMR |11-27-12| Added rx_dyn_recal_overall_timeout_sel init to 0b001 ## -- jfg12112101| jfg |11-21-12| Added Zcal inits ## -- jfg12112100| jfg |11-21-12| Added CU pll modes ## -- 12111300| berger |11-13-12| Updated with HW eyeopt and recal settings ## -- 12101900| berger |10-19-12| Updated Z DMI mirror pattern ## -- 12062500| SMR |06-25-12| HW210654: Added rx_sls_timeout_sel default of 1 ## -- 12041000| berger |04-10-12| Added Z specific settings (scramble tap points, start/end/width id's) ## -- 12021601|mbs |02-16-12| Broke Centaur rx 6 pack into 4 and 2 ## -- 11012500| mbs |01-25-12| Swizzle and typo fixes for HW191494, HW191518, HW188304 ## -- 12011800| RJR |01-18-12| Added RX_CTL2_REGS FILE REFERENCES Issue HW164277 ## -- 11121500| thomsen |12-15-11| Added Per-Pack GCR SCOM Addresses for Regchk (HW188381,HW182867) ## -- | | | Removed 0x0000040000000000 from TX address definitions since it is in the lower level figtree files (HW187781,HW187893) ## -- 11120700| mbs |12-07-11| Fixed RX mirror prbs swizzle for Centaur (HW187542) ## -- 11120500| thomsen |12-05-11| Changed TX.TXCTL.TX_CTL_REGS.base_addr from all 0's to 0x000004.... to set group address to TX ## -- 11111702| jg |11-17-11| HW184269: Changed swizzle for Centaur ## -- 11102100| SMR |10-21-11| HW181193: Added rx_dyn_rpr_enc_bad_data_lane_width register ## -- 11092900| SMR |09-29-11| HW171978: Added dyn rpr error tallying defaults ## -- 11050300| SMR |05-02-11| Added tx_max_bad_lanes ## -- 11032200| jg |02-17-11| Added RX PLLREG register offsets ## -- 11022800| thomsen |02-28-11| Fixed RX/TX scramble tap pattern match problem between driver and receiver. Also fixed in iodpv_mc_wrap.fig. ## -- 11021700| thomsen |02-17-11| Fixed RX_BUS_WIDTH from 24 to 17 ## -- 11021600| thomsen |02-16-11| Added Per-Bus, Per-Lane and Per-Group GCR SCOM addresses so Regchk would pass ## -- 11020200| thomsen |02-02-11| Added RX & TX scramble/descramble tap ID settings ## -- 11012500| berger |01-25-11| added TX lane disable and rx_bus_width fields, added missing SETUP_ID fields ## -- 11010600| berger |01-06-11| added lane disable and max bad lane ## -- 11010400| thomsen |01-04-11| Changed TX_BUS_WIDTH from 17 to 24 ## -- 10121600| thomsen |12-16-10| Added RX_FENCE ## -- 10121300| thomsen |12-13-10| Swapped DMI_BUS END_LANE_ID values per HW133020 ## -- 10120800| thomsen |12-08-10| Added TX_BUS_WIDTH and Z support ## -- 10112900| thomsen |11-29-10| Fixed BUS_ID's and GROUP_ID's for TX ## -- 10102600| thomsen |10-26-10| Initial version ## -------------------------------------------------------------------------------- SyntaxVersion = 1 #################################################################### # Define File #################################################################### include edi.io.define define def_IS_HW = SYS.ATTR_IS_SIMULATION == 0; define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1; #BUSCTL.BUS_CTL_REGS.TX_IMPCAL_P_4X_PB scom 0x800F1C000201043F { bits, scom_data, expr; tx_zcal_p_4x, 0b00100, any; } #BUSCTL.BUS_CTL_REGS.TX_IMPCAL_SWO2_PB scom 0x800F2C000201043F { bits, scom_data, expr; tx_zcal_sm_max_val, 0b1000110, any; tx_zcal_sm_min_val, 0b0010101 , def_IS_HW; tx_zcal_sm_min_val, 0b0010110 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG scom 0x800AF0000201043F { bits, scom_data, expr; rx_max_ber_check_count, 0b00000011 , def_IS_HW; rx_max_ber_check_count, 0b00000000 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP scom 0x800B78000201043F { bits, scom_data, expr; rx_amin_cfg, 0b111 , def_IS_HW; rx_amin_cfg, 0b000 , def_IS_VBU; rx_anap_cfg, 0b10 , def_IS_HW; rx_anap_cfg, 0b00 , def_IS_VBU; rx_h1_cfg, 0b01 , def_IS_HW; rx_h1_cfg, 0b00 , def_IS_VBU; rx_peak_cfg, 0b10 , def_IS_HW; rx_peak_cfg, 0b00 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP scom 0x800B80000201043F { bits, scom_data, expr; rx_ber_cfg, 0b100 , def_IS_HW; rx_ber_cfg, 0b000 , def_IS_VBU; rx_dac_bo_cfg, 0b101 , def_IS_HW; rx_dac_bo_cfg, 0b000 , def_IS_VBU; rx_ddc_cfg, 0b10 , def_IS_HW; rx_ddc_cfg, 0b00 , def_IS_VBU; rx_init_tmr_cfg, 0b111 , def_IS_HW; rx_init_tmr_cfg, 0b000 , def_IS_VBU; rx_prot_cfg, 0b10 , def_IS_HW; rx_prot_cfg, 0b00 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG scom 0x800A18000201043F { bits, scom_data, expr; rx_dyn_recal_overall_timeout_sel, 0b100, any; } #RX.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_TIMEOUTS_PP scom 0x800B40000201043F { bits, scom_data, expr; rx_dyn_recal_interval_timeout_sel, 0b101, any; } #RX.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG scom 0x8009D8000201043F { bits, scom_data, expr; rx_dyn_rpr_bad_lane_max, 0b0001111, any; rx_dyn_rpr_enc_bad_data_lane_width, 0b101, any; rx_dyn_rpr_err_cntr1_duration, 0b0111, any; } #RX.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG scom 0x800AE0000201043F { bits, scom_data, expr; rx_dyn_rpr_bad_bus_max, 0b0111111, any; rx_dyn_rpr_err_cntr2_duration, 0b0111, any; } #RX.RXCTL.RX_CTL_REGS.RX_EO_CONVERGENCE_PG scom 0x800A80000201043F { bits, scom_data, expr; rx_eo_converged_end_count, 0b0111 , def_IS_HW; rx_eo_converged_end_count, 0b0011 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG scom 0x800A38000201043F { bits, scom_data, expr; rx_eo_enable_ber_test, 0b1 , def_IS_HW; rx_eo_enable_ber_test, 0b0 , def_IS_VBU; rx_eo_enable_ctle_cal, 0b1 , def_IS_HW; rx_eo_enable_ctle_cal, 0b0 , def_IS_VBU; rx_eo_enable_ddc, 0b1 , def_IS_HW; rx_eo_enable_ddc, 0b0 , def_IS_VBU; rx_eo_enable_dfe_h1_cal, 0b1 , def_IS_HW; rx_eo_enable_dfe_h1_cal, 0b0 , def_IS_VBU; rx_eo_enable_final_l2u_adj, 0b1, any; rx_eo_enable_h1ap_tweak, 0b1 , def_IS_HW; rx_eo_enable_h1ap_tweak, 0b0 , def_IS_VBU; rx_eo_enable_latch_offset_cal, 0b1 , def_IS_HW; rx_eo_enable_latch_offset_cal, 0b0 , def_IS_VBU; rx_eo_enable_result_check, 0b1 , def_IS_HW; rx_eo_enable_result_check, 0b0 , def_IS_VBU; rx_eo_enable_vga_cal, 0b1 , def_IS_HW; rx_eo_enable_vga_cal, 0b0 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_FENCE_PG scom 0x8009A8000201043F { bits, scom_data, expr; rx_fence, 0b1, any; } #RX.RXCTL.RX_CTL_REGS.RX_ID1_PG scom 0x800850000201043F { bits, scom_data, expr; rx_bus_id, 0b000000, any; rx_group_id, 0b000000, any; } #RX.RXCTL.RX_CTL_REGS.RX_ID2_PG scom 0x800858000201043F { bits, scom_data, expr; rx_last_group_id, 0b000000, any; } #RX.RXCTL.RX_CTL_REGS.RX_ID3_PG scom 0x800860000201043F { bits, scom_data, expr; rx_end_lane_id, 0b0010000, any; rx_start_lane_id, 0b0000000, any; } #RX.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG scom 0x800928000201043F { bits, scom_data, expr; rx_lane_disabled_vec_0_15, 0b0000000000000000, any; } #RX.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG scom 0x800930000201043F { bits, scom_data, expr; rx_lane_disabled_vec_16_31, 0b0111111111111111, any; } #RX.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG scom 0x8009C0000201043F { bits, scom_data, expr; rx_c4_sel, 0b00 , def_IS_HW; rx_c4_sel, 0b11 , def_IS_VBU; rx_prot_speed_slct, 0b1 , def_IS_HW; rx_prot_speed_slct, 0b0 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG scom 0x800AB8000201043F { bits, scom_data, expr; rx_rc_enable_ber_test, 0b1 , def_IS_HW; rx_rc_enable_ber_test, 0b0 , def_IS_VBU; rx_rc_enable_ctle_cal, 0b1 , def_IS_HW; rx_rc_enable_ctle_cal, 0b0 , def_IS_VBU; rx_rc_enable_ddc, 0b1 , def_IS_HW; rx_rc_enable_ddc, 0b0 , def_IS_VBU; rx_rc_enable_dfe_h1_cal, 0b0, any; rx_rc_enable_h1ap_tweak, 0b0, any; rx_rc_enable_latch_offset_cal, 0b1 , def_IS_HW; rx_rc_enable_latch_offset_cal, 0b0 , def_IS_VBU; rx_rc_enable_result_check, 0b1 , def_IS_HW; rx_rc_enable_result_check, 0b0 , def_IS_VBU; rx_rc_enable_vga_cal, 0b1 , def_IS_HW; rx_rc_enable_vga_cal, 0b0 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO1_PP scom 0x800B90000201043F { bits, scom_data, expr; rx_recal_timeout_sel_b, 0b0110 , def_IS_HW; rx_recal_timeout_sel_b, 0b1000 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP scom 0x800B98000201043F { bits, scom_data, expr; rx_recal_timeout_sel_g, 0b0111 , def_IS_HW; rx_recal_timeout_sel_g, 0b0100 , def_IS_VBU; rx_recal_timeout_sel_h, 0b1011 , def_IS_HW; rx_recal_timeout_sel_h, 0b1000 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP scom 0x800BA0000201043F { bits, scom_data, expr; rx_recal_timeout_sel_i, 0b1011 , def_IS_HW; rx_recal_timeout_sel_i, 0b1000 , def_IS_VBU; rx_recal_timeout_sel_j, 0b1011 , def_IS_HW; rx_recal_timeout_sel_j, 0b1000 , def_IS_VBU; rx_recal_timeout_sel_k, 0b1011 , def_IS_HW; rx_recal_timeout_sel_k, 0b1000 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP scom 0x800B60000201043F { bits, scom_data, expr; rx_servo_timeout_sel_b, 0b1010 , def_IS_HW; rx_servo_timeout_sel_b, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_d, 0b1010 , def_IS_HW; rx_servo_timeout_sel_d, 0b1000 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP scom 0x800B68000201043F { bits, scom_data, expr; rx_servo_timeout_sel_g, 0b0111 , def_IS_HW; rx_servo_timeout_sel_g, 0b0100 , def_IS_VBU; rx_servo_timeout_sel_h, 0b1011 , def_IS_HW; rx_servo_timeout_sel_h, 0b1000 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP scom 0x800B70000201043F { bits, scom_data, expr; rx_servo_timeout_sel_i, 0b1011 , def_IS_HW; rx_servo_timeout_sel_i, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_j, 0b1101 , def_IS_HW; rx_servo_timeout_sel_j, 0b1000 , def_IS_VBU; rx_servo_timeout_sel_k, 0b1101 , def_IS_HW; rx_servo_timeout_sel_k, 0b1000 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG scom 0x800910000201043F { bits, scom_data, expr; rx_eo_amp_timeout_sel, 0b111 , def_IS_HW; rx_eo_amp_timeout_sel, 0b110 , def_IS_VBU; rx_eo_ctle_timeout_sel, 0b111 , def_IS_HW; rx_eo_ctle_timeout_sel, 0b110 , def_IS_VBU; rx_eo_ddc_timeout_sel, 0b111 , def_IS_HW; rx_eo_ddc_timeout_sel, 0b110 , def_IS_VBU; rx_eo_h1ap_timeout_sel, 0b111 , def_IS_HW; rx_eo_h1ap_timeout_sel, 0b110 , def_IS_VBU; rx_eo_offset_timeout_sel, 0b111 , def_IS_HW; rx_eo_offset_timeout_sel, 0b110 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG scom 0x800898000201043F { bits, scom_data, expr; rx_ds_bl_timeout_sel, 0b101 , def_IS_HW; rx_ds_bl_timeout_sel, 0b001 , def_IS_VBU; rx_ds_timeout_sel, 0b111, any; rx_sls_timeout_sel, 0b110, any; rx_wt_timeout_sel, 0b111 , def_IS_HW; rx_wt_timeout_sel, 0b011 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG scom 0x800998000201043F { bits, scom_data, expr; rx_rx_bus_width, 0b0010001, any; rx_tx_bus_width, 0b0011000, any; } #RX.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG scom 0x800958000201043F { bits, scom_data, expr; rx_wtr_max_bad_lanes, 0b00010, any; } #RX.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG scom 0x800A30000201043F { bits, scom_data, expr; rx_wt_cu_pll_pgooddly, 0b110 , def_IS_HW; rx_wt_cu_pll_pgooddly, 0b000 , def_IS_VBU; rx_wt_cu_pll_reset, 0b0 , def_IS_HW; rx_wt_cu_pll_reset, 0b1 , def_IS_VBU; } #RX.RXPACKS#0.RXPACK_DEFAULT.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B0000201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX.RXPACKS#0.RXPACK_DEFAULT.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B0010201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX.RXPACKS#0.RXPACK_DEFAULT.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B0060201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b110, any; } #RX.RXPACKS#0.RXPACK_DEFAULT.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B0050201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b101, any; } #RX.RXPACKS#1.RXPACK_DEFAULT.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B0040201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b100, any; } #RX.RXPACKS#1.RXPACK_DEFAULT.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B0030201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b011, any; } #RX.RXPACKS#1.RXPACK_DEFAULT.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B0020201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b010, any; } #RX.RXPACKS#1.RXPACK_DEFAULT.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B0070201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b111, any; } #RX.RXPACKS#2.RXPACK_DEFAULT.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B0080201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX.RXPACKS#2.RXPACK_DEFAULT.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B0090201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b111, any; } #RX.RXPACKS#2.RXPACK_DEFAULT.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00E0201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b010, any; } #RX.RXPACKS#2.RXPACK_DEFAULT.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00A0201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b110, any; } #RX.RXPACKS#3.RXPACK_DEFAULT.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00C0201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b100, any; } #RX.RXPACKS#3.RXPACK_DEFAULT.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00D0201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b011, any; } #RX.RXPACKS#3.RXPACK_DEFAULT.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00B0201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b101, any; } #RX.RXPACKS#3.RXPACK_DEFAULT.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00F0201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b001, any; } #RX.RXPACKS#4.RXPACK_4.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B0100201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #RX.RXPACKS#4.RXPACK_4.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B0110201043F { bits, scom_data, expr; rx_prbs_tap_id, 0b000, any; } #TX.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG scom 0x800CC4000201043F { bits, scom_data, expr; tx_drv_clk_pattern_gcrmsg, 0b00, any; } #TX.TXCTL.TX_CTL_REGS.TX_DYN_RECAL_TIMEOUTS_PP scom 0x800EAC000201043F { bits, scom_data, expr; tx_dyn_recal_interval_timeout_sel, 0b101, any; } #TX.TXCTL.TX_CTL_REGS.TX_ID1_PG scom 0x800C94000201043F { bits, scom_data, expr; tx_bus_id, 0b000000, any; tx_group_id, 0b100000, any; } #TX.TXCTL.TX_CTL_REGS.TX_ID2_PG scom 0x800C9C000201043F { bits, scom_data, expr; tx_last_group_id, 0b100000, any; } #TX.TXCTL.TX_CTL_REGS.TX_ID3_PG scom 0x800CA4000201043F { bits, scom_data, expr; tx_end_lane_id, 0b0010111, any; tx_start_lane_id, 0b0000000, any; } #TX.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG scom 0x800D1C000201043F { bits, scom_data, expr; tx_lane_disabled_vec_0_15, 0b0000000000000000, any; } #TX.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG scom 0x800D24000201043F { bits, scom_data, expr; tx_lane_disabled_vec_16_31, 0b0000000011111111, any; } #TX.TXCTL.TX_CTL_REGS.TX_MODE_PG scom 0x800C1C000201043F { bits, scom_data, expr; tx_max_bad_lanes, 0b00010, any; } #TX.TXPACKS#0.TXPACK_0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434000201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX.TXPACKS#0.TXPACK_0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434010201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX.TXPACKS#0.TXPACK_0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434020201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b010, any; } #TX.TXPACKS#1.TXPACK_1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434040201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b100, any; } #TX.TXPACKS#1.TXPACK_1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434030201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b011, any; } #TX.TXPACKS#1.TXPACK_1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434050201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b101, any; } #TX.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434060201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b110, any; } #TX.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434070201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b111, any; } #TX.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434080201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434090201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340A0201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b010, any; } #TX.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340B0201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b011, any; } #TX.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340C0201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b011, any; } #TX.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340D0201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b010, any; } #TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340E0201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x8004340F0201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } #TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434100201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b111, any; } #TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434110201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b110, any; } #TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434120201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b101, any; } #TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434130201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b100, any; } #TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434140201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b011, any; } #TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434150201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b010, any; } #TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434160201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b001, any; } #TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL scom 0x800434170201043F { bits, scom_data, expr; tx_prbs_tap_id, 0b000, any; } ###################################### ## END OF FILE #######################################