#-- $Id: cen.dmi.custom.scom.initfile,v 1.21 2014/02/20 15:19:02 garyp Exp $
#-- CHANGE HISTORY:
#--------------------------------------------------------------------------------
#-- Version:|Author: | Date:  | Comment:
#-- --------|--------|--------|--------------------------------------------------
#--     1.21|garyp   |02/19/14|Added rx_min_eye_width and rx_min_eye_height for manufacturing and lab thresholding
#--     1.20|jgrell  |02/14/14|Corrected FIR_ACTION1 and FIR_MASK settings for SW245013
#--     1.19|jgrell  |02/12/14|Added FIR_ACTION1 setting and changed FIR_MASK setting for SW245013
#--                           |Added rx_wt_lane_disabled=1 on lane 17 for SW244284
#--     1.18|jgrell  |11/21/13|Added rx_trc_grp setting at the request of Yuen Tschang
#--                           |Set rx_eo_ddc_timeout_sel to 110 for DD2
#--     1.17|jgrell  |10/29/13|Changed rx_ds_timeout_sel setting to 111
#--     1.16|jgrell  |10/28/13|Re-enabled recal bits for DD2+ hw
#--     1.15|jgrell  |09/24/13|Changed "1" expression to "any"
#--     1.13|jgrell  |09/17/13|Added DD2 specific inits
#--     1.11|jgrell  |09/12/13|Re-added "Override" scoms
#--     1.10|jgrell  |08/21/13|Removed "Override" scoms
#--     1.9 |jgrell  |06/27/13|Removed previous change and will debug
#--     1.8 |jgrell  |06/25/13|Added DFE override settings and updated sls and dyn_recal_overall timeout settings
#--     1.7 |jgrell  |04/18/13|Added EC level control of the Recal DFE, DDC, and CTLE enable bits. ('0' when EC < 20)
#--     1.6 |jgrell  |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab.
#--     1.5 |thomsen |03/07/13|Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab.
#--         |        |        |Fixed address typo on tx_clk_invert entry
#--     1.4 |thomsen |02/26/13|Fixed typo on lane 22 tx_lane_invert
#--     1.3 |thomsen |02/18/13|Renamed HW_EXPRESS and VBU_EXPRESS to def_IS_HW & def_IS_VBU. Added target comments, changed to attribute method of setting tx_lane_invert's and added tx_clk_invert
#--     1.2 |berger  |02/01/13|Removed a handful of settings already in the base file, added sim attr for MSB swap and lane invert
#--     1.1 |thomsen |01/23/13|Created initial version
#-- --------|--------|--------|--------------------------------------------------
#--------------------------------------------------------------------------------
# End of revision history
#--------------------------------------------------------------------------------
#-- TARGETS:
#-- SYS. Chiplet target
#-- TGT1. Proc target
#-- TGT2. Connected Chiplet target
#-- TGT3. Connected Proc target

#--Master list of variables that can be used in this file is at:
#--<Attribute Definition Location>

SyntaxVersion = 1

#-- -----------------------------------------------------------------------------
#--******************************************************************************
#-- -----------------------------------------------------------------------------
#--
#-- Includes
#-- Note:  Must include the path to the .define file.
#-- -----------------------------------------------------------------------------
#--******************************************************************************
#-- -----------------------------------------------------------------------------
include edi.io.define

#-- -----------------------------------------------------------------------------
#--******************************************************************************
#-- -----------------------------------------------------------------------------
#--
#-- Defines
#--
#-- -----------------------------------------------------------------------------
#--******************************************************************************
#-- -----------------------------------------------------------------------------
define def_IS_HW  = (SYS.ATTR_IS_SIMULATION == 0);
define def_IS_VBU = (SYS.ATTR_IS_SIMULATION == 1);

define def_all_lanes=11111;

#--*****************
#-- set rx_min_eye_width and rx_min_eye_height if in manufacturing mode
#--*****************
scom 0x800.0b(rx_result_chk_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
        bits,                         	scom_data, 	expr;
    rx_min_eye_width, SYS.ATTR_MNFG_DMI_MIN_EYE_WIDTH,              ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
    rx_min_eye_height, SYS.ATTR_MNFG_DMI_MIN_EYE_HEIGHT,            ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
}




#--***********************************************************************************
#-------------------------------------------------------------------------------------
#     __                        ____                             __  __
#    / /   ____ _____  ___     / __ \____ _      _____  _____   / / / /___
#   / /   / __ `/ __ \/ _ \   / /_/ / __ \ | /| / / _ \/ ___/  / / / / __ \
#  / /___/ /_/ / / / /  __/  / ____/ /_/ / |/ |/ /  __/ /     / /_/ / /_/ /
# /_____/\__,_/_/ /_/\___/  /_/    \____/|__/|__/\___/_/      \____/ .___/
#                                                                 /_/
#-------------------------------------------------------------------------------------
#--***********************************************************************************

# rx_lane_pdwn
#scom 0x800.0b(rx_mode_pl)(rx_grp0)(def_all_lanes).0x(cn_gcr_addr){
#    bits,            scom_data;
#    rx_lane_pdwn,    0b0;
#}

# tx_lane_pdwn
#scom 0x800.0b(tx_mode_pl)(tx_grp0)(def_all_lanes).0x(cn_gcr_addr){
#    bits,            scom_data;
#    tx_lane_pdwn,    0b0;
#}
#--***********************************************************************************
#-------------------------------------------------------------------------------------
#   _______  __    __    ___    _   ________   _____   ___    ____________  ______
#  /_  __/ |/ /   / /   /   |  / | / / ____/  /  _/ | / / |  / / ____/ __ \/_  __/
#   / /  |   /   / /   / /| | /  |/ / __/     / //  |/ /| | / / __/ / /_/ / / /
#  / /  /   |   / /___/ ___ |/ /|  / /___   _/ // /|  / | |/ / /___/ _, _/ / /
# /_/  /_/|_|  /_____/_/  |_/_/ |_/_____/  /___/_/ |_/  |___/_____/_/ |_| /_/
#                                        figlet -fslant
#-------------------------------------------------------------------------------------
#--***********************************************************************************

# These need to come as attributes from the MRW rather than be hardcoded here
#define  def_EI_TX_LANE_INVERT_VEC_CEN4 = 0x60003500;  # MSBSWAP=0 ON TULETA
#define  def_EI_TX_LANE_INVERT_VEC_CEN5 = 0x7FE4FF00;  # MSBSWAP=1 ON TULETA
#define  def_EI_TX_LANE_INVERT_VEC_CEN6 = 0xED937F00;  # MSBSWAP=1 ON TULETA
#define  def_EI_TX_LANE_INVERT_VEC_CEN7 = 0xFFF4FF00;  # MSBSWAP=1 ON TULETA

# These only do a scom if the invert attribute is set (saves scom's). The default scanflush value of tx_lane_invert for each lane is '0'.
# Lane 0
# scom 0x800404000201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_0).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x80000000) > 0;
}
# Lane 1
# 0x800404010201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_1).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x40000000) > 0;
}
# Lane 2
# 0x800404020201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_2).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x20000000) > 0;
}
# Lane 3
# 0x800404030201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_3).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x10000000) > 0;
}
# Lane 4
# 0x800404040201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_4).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x08000000) > 0;
}
# Lane 5
# 0x800404050201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_5).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x04000000) > 0;
}
# Lane 6
# 0x800404060201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_6).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x02000000) > 0;
}
# Lane 7
# 0x800404070201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_7).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x01000000) > 0;
}
# Lane 8
# 0x800404080201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_8).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00800000) > 0;
}
# Lane 9
# 0x800404090201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_9).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00400000) > 0;
}
# Lane 10
# 0x8004040A0201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_10).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00200000) > 0;
}
# Lane 11
# 0x8004040B0201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_11).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00100000) > 0;
}
# Lane 12
# 0x8004040C0201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_12).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00080000) > 0;
}
# Lane 13
# 0x8004040D0201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_13).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00040000) > 0;
}
# Lane 14
# 0x8004040E0201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_14).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00020000) > 0;
}
# Lane 15
# 0x8004040F0201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_15).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00010000) > 0;
}
# Lane 16
# 0x800404100201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_16).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00008000) > 0;
}
# Lane 17
# 0x800404110201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_17).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00004000) > 0;
}
# Lane 18
# 0x800404120201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_18).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00002000) > 0;
}
# Lane 19
# 0x800404130201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_19).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00001000) > 0;
}
# Lane 20
# 0x800404140201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_20).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000800) > 0;
}
# Lane 21
# 0x800404150201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_21).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000400) > 0;
}
# Lane 22
# 0x800404160201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_22).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000200) > 0;
}
# Lane 23
# 0x800404170201043F
scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_23).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000100) > 0;
}

#--***********************************************************************************
#-------------------------------------------------------------------------------------
#   _______  __    ________    __ __    ____                     __ 
#  /_  __/ |/ /   / ____/ /   / //_/   /  _/___ _   _____  _____/ /_
#   / /  |   /   / /   / /   / ,<      / // __ \ | / / _ \/ ___/ __/
#  / /  /   |   / /___/ /___/ /| |   _/ // / / / |/ /  __/ /  / /_  
# /_/  /_/|_|   \____/_____/_/ |_|  /___/_/ /_/|___/\___/_/   \__/  

#                                        figlet -fslant
#-------------------------------------------------------------------------------------
#--***********************************************************************************
# CLK Lane (assigned to bit 31 of TX Lane Invert Attribute)
# 0x800???7008010C3F 
scom 0x800.0b(tx_clk_mode_pg)(tx_grp0)(lane_22).0x(cn_gcr_addr) {
bits,            scom_data, expr;
tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000001) > 0;
}

#--***********************************************************************************
#-------------------------------------------------------------------------------------
#     __  ________ ____     _____
#    /  |/  / ___// __ )   / ___/      ______ _____
#   / /|_/ /\__ \/ __  |   \__ \ | /| / / __ `/ __ \
#  / /  / /___/ / /_/ /   ___/ / |/ |/ / /_/ / /_/ /
# /_/  /_//____/_____/   /____/|__/|__/\__,_/ .___/
#                                         /_/
#                                        figlet -fslant
#-------------------------------------------------------------------------------------
#--***********************************************************************************

# TX_MSBSWAP setting via manaual SCOM overrides
# ./iotk put tx_msbswap=1 (only when p# mod 4 = 3 for centaur or mcs mod 4 = 0, ie. grp0)
# 0x800C1C000201043F
scom 0x800.0b(tx_mode_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr) {
bits,                     scom_data;
tx_msbswap,               (ATTR_EI_BUS_TX_MSBSWAP & 0x01);
}

#--**************************************************************************************************************
#----------------------------------------------------------------------------------------------------------------
#    ________________     ____        ________             ____             _ __           __  ___           __  
#   / ____/ ____/ __ \   / __ )__  __/ __/ __/__  _____   / __ \____ ______(_) /___  __   /  |/  /___ ______/ /__
#  / / __/ /   / /_/ /  / __  / / / / /_/ /_/ _ \/ ___/  / /_/ / __ `/ ___/ / __/ / / /  / /|_/ / __ `/ ___/ //_/
# / /_/ / /___/ _, _/  / /_/ / /_/ / __/ __/  __/ /     / ____/ /_/ / /  / / /_/ /_/ /  / /  / / /_/ (__  ) ,<   
# \____/\____/_/ |_|  /_____/\__,_/_/ /_/  \___/_/     /_/    \__,_/_/  /_/\__/\__, /  /_/  /_/\__,_/____/_/|_|  
#                                                                             /____/                             
#----------------------------------------------------------------------------------------------------------------
#--**************************************************************************************************************
# HW242564: Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab.
# 0x800???0002011E3F
# This is applied to all configured clkgrp's via chiplet targetting
scom 0x800.0b(rx_fir1_mask_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
bits,                             scom_data;
rx_pg_fir_err_mask_gcr_buff,      0b1;
}
scom 0x800.0b(tx_fir_mask_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr) {
bits,                             scom_data;
tx_pg_fir_err_mask_gcr_buff,      0b1;
}
scom 0x800.0b(rx_fir_mask_pb)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
bits,                             scom_data;
rx_pb_fir_err_mask_gcr_buff0,    0b1;
rx_pb_fir_err_mask_gcr_buff1,    0b1;
rx_pb_fir_err_mask_gcr_buff2,    0b1;
}

# Mask off all rx and tx parity errors in the fir register
# SCOM_FIR_MASK_PB: setting from SW245013
scom 0x02010403 {
scom_data;
0xDFFFFFFFFFFF0000;
}

# SCOM_FIR_ACTION1_PB: setting from SW245013
scom 0x02010407 {
scom_data;
0xFFDFFFFFFFFFC000;
}

#--**************************************************************************************************************
#----------------------------------------------------------------------------------------------------------------
# Recal  (and part of DMI DFE Override)
#----------------------------------------------------------------------------------------------------------------
#--**************************************************************************************************************
# HW235842 and HW244323

scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
bits,                         	scom_data, 	expr;
rx_rc_enable_dfe_h1_cal,      	0b0,       	ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0 || ATTR_DMI_DFE_OVERRIDE==1;
rx_rc_enable_ddc,		0b0,		ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0;
rx_rc_enable_ctle_cal,		0b0,		ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0;
rx_rc_enable_h1ap_tweak,        0b0,            ATTR_DMI_DFE_OVERRIDE==1;
}

#--***********************************************************************************
#-------------------------------------------------------------------------------------
# DMI DFE Override  (HW244323)
#-------------------------------------------------------------------------------------
#--***********************************************************************************

#scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0)(lane_na).0x(dmi0_gcr_addr) {
#bits,                         	scom_data, 	expr;
#rx_rc_enable_dfe_h1_cal,      	0b0,       	ATTR_DMI_DFE_OVERRIDE==1;
#rx_rc_enable_h1ap_tweak,        0b0,            ATTR_DMI_DFE_OVERRIDE==1;
#}

scom 0x800.0b(rx_eo_step_cntl_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
bits,                         	scom_data, 	expr;
rx_eo_enable_dfe_h1_cal,      	0b0,       	ATTR_DMI_DFE_OVERRIDE==1;
rx_eo_enable_h1ap_tweak,      	0b0,       	ATTR_DMI_DFE_OVERRIDE==1;
}

scom 0x800.0b(rx_amax_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
bits,                         	scom_data, 	expr;
rx_amax_high,		      	0b01101110,	ATTR_DMI_DFE_OVERRIDE==1;
rx_amax_low,		      	0b01010000,	ATTR_DMI_DFE_OVERRIDE==1;
}

scom 0x800.0b(rx_amp_val_pl)(rx_grp0)(def_all_lanes).0x(cn_gcr_addr) {
bits,                         	scom_data, 	expr;
rx_amp_gain,		      	0b1001,		ATTR_DMI_DFE_OVERRIDE==1;
}

#--***********************************************************************************
#-------------------------------------------------------------------------------------
#-- DD2 Centaur
#-------------------------------------------------------------------------------------
#--***********************************************************************************

scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
    bits,                   	  scom_data,		expr;
    rx_sls_timeout_sel_dd2,       0b1010,		ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1;
    rx_ds_bl_timeout_sel_dd2,     0b101,		ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1;
    rx_cl_timeout_sel_dd2,        0b010,		ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1;
    rx_wt_timeout_sel_dd2,        0b111,		ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1;
    rx_ds_timeout_sel_dd2,        0b111,		ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1;
}

scom 0x800.0b(rx_trace_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
    bits,             scom_data,	expr;
    rx_trc_grp,       0b000000,		ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1;
}

scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
    bits,                   	  scom_data,		expr;
    rx_eo_ddc_timeout_sel,        0b110,		ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1;
}


#--**************************************************************************************************************
#----------------------------------------------------------------------------------------------------------------
# Power Down & Disable Unused Lanes
#----------------------------------------------------------------------------------------------------------------
#--**************************************************************************************************************

scom 0x800.0b(rx_mode_pl)(rx_grp0)(lane_17).0x(cn_gcr_addr) {
bits,                         	scom_data;
rx_lane_pdwn,			0b1;
}

scom 0x800.0b(rx_wt_status_pl)(rx_grp0)(lane_17).0x(cn_gcr_addr) {
bits,                         	scom_data;
rx_wt_lane_disabled,		0b1;
}

############################################################################################
# END OF FILE
############################################################################################