ATTR_PROC_PSI_BRIDGE_BAR_ENABLE
TARGET_TYPE_PROC_CHIP
PSI Bridge BAR enable
creator: platform
consumer: proc_setup_bars
firmware notes: none
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR
TARGET_TYPE_PROC_CHIP
PSI Bridge BAR base address value
creator: platform
consumer: proc_setup_bars
firmware notes:
64-bit address representing BAR RA
NOTE: BAR register covers RA 14:43
NOTE: Implied size of 1MB
uint64
ATTR_PROC_FSP_BAR_ENABLE
TARGET_TYPE_PROC_CHIP
FSP BAR enable
creator: platform
consumer: proc_setup_bars
firmware notes: none
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_PROC_FSP_BAR_BASE_ADDR
TARGET_TYPE_PROC_CHIP
FSP BAR base address value
creator: platform
consumer: proc_setup_bars
firmware notes:
64-bit address representing BAR RA
NOTE: BAR register covers RA 14:43
uint64
ATTR_PROC_FSP_BAR_SIZE
TARGET_TYPE_PROC_CHIP
FSP BAR size value
creator: platform
consumer: proc_setup_bars
firmware notes: none
uint64
4_GB = 0x0000000100000000,
2_GB = 0x0000000080000000,
1_GB = 0x0000000040000000,
512_MB = 0x0000000020000000,
256_MB = 0x0000000010000000,
128_MB = 0x0000000008000000,
64_MB = 0x0000000004000000,
32_MB = 0x0000000002000000,
16_MB = 0x0000000001000000,
8_MB = 0x0000000000800000,
4_MB = 0x0000000000400000,
2_MB = 0x0000000000200000,
1_MB = 0x0000000000100000
ATTR_PROC_FSP_MMIO_MASK_SIZE
TARGET_TYPE_PROC_CHIP
FSP MMIO mask size value
creator: platform
consumer: proc_setup_bars
firmware notes:
AND mask applied to RA 32:35 when transmitting address to FSP
NOTE: RA 14:31 are always replaced with zero
uint64
4_GB = 0x0000000100000000,
2_GB = 0x0000000080000000,
1_GB = 0x0000000040000000,
512_MB = 0x0000000020000000,
256_MB = 0x0000000010000000
ATTR_PROC_INTP_BAR_ENABLE
TARGET_TYPE_PROC_CHIP
INTP BAR enable
creator: platform
consumer: proc_setup_bars
firmware notes: none
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_PROC_INTP_BAR_BASE_ADDR
TARGET_TYPE_PROC_CHIP
INTP BAR base address value
creator: platform
consumer: proc_setup_bars
firmware notes:
64-bit address representing BAR RA
NOTE: BAR register covers RA 14:43
NOTE: Implied size of 1MB
uint64
ATTR_PROC_AS_MMIO_BAR_ENABLE
TARGET_TYPE_PROC_CHIP
AS MMIO BAR enable
creator: platform
consumer: proc_setup_bars
firmware notes: none
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_PROC_AS_MMIO_BAR_BASE_ADDR
TARGET_TYPE_PROC_CHIP
AS MMIO BAR base address value
creator: platform
consumer: proc_setup_bars
firmware notes:
64-bit address representing BAR RA
NOTE: BAR register covers RA 14:51
uint64
ATTR_PROC_AS_MMIO_BAR_SIZE
TARGET_TYPE_PROC_CHIP
AS MMIO BAR size value
creator: platform
consumer: proc_setup_bars
firmware notes: none
uint64
2_MB = 0x0000000000200000,
1_MB = 0x0000000000100000,
512_KB = 0x0000000000080000,
256_KB = 0x0000000000040000
ATTR_PROC_NX_MMIO_BAR_ENABLE
TARGET_TYPE_PROC_CHIP
NX MMIO BAR enable
creator: platform
consumer: proc_setup_bars
firmware notes: none
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_PROC_NX_MMIO_BAR_BASE_ADDR
TARGET_TYPE_PROC_CHIP
NX MMIO BAR base address value
creator: platform
consumer: proc_setup_bars
firmware notes:
64-bit address representing BAR RA
NOTE: BAR register covers RA 14:51
uint64
ATTR_PROC_NX_MMIO_BAR_SIZE
TARGET_TYPE_PROC_CHIP
NX MMIO BAR size value
creator: platform
consumer: proc_setup_bars
firmware notes: none
uint64
16_GB = 0x0000000400000000,
16_MB = 0x0000000001000000,
1_MB = 0x0000000000100000,
64_KB = 0x0000000000010000,
4_KB = 0x0000000000001000
ATTR_PROC_PCIE_BAR_ENABLE
TARGET_TYPE_PROC_CHIP
PCIE BAR enable
creator: platform
consumer: proc_setup_bars
firmware notes:
first dimension: PCIE unit number (0:2)
second dimension: BAR number (0:2)
uint8
DISABLE = 0x0, ENABLE = 0x1
3,3
ATTR_PROC_PCIE_BAR_BASE_ADDR
TARGET_TYPE_PROC_CHIP
PCIE BAR base address value
creator: platform
consumer: proc_setup_bars
firmware notes:
64-bit address representing BAR RA
first dimension: PCIE unit number (0:2)
second dimension: BAR number (0:2)
NOTE: BAR0/1 registers cover RA 14:47
NOTE: BAR2 registers covers RA 14:51
uint64
3,3
ATTR_PROC_PCIE_BAR_SIZE
TARGET_TYPE_PROC_CHIP
PCIE BAR size value
creator: platform
consumer: proc_setup_bars
firmware notes:
first dimension: PCIE unit number (0:2)
second dimension: BAR number (0:2)
NOTE: supported BAR0/1 sizes are from 64KB-1PB
NOTE: only supported BAR2 size is 4KB
uint64
1_PB = 0x0004000000000000,
512_TB = 0x0002000000000000,
256_TB = 0x0001000000000000,
128_TB = 0x0000800000000000,
64_TB = 0x0000400000000000,
32_TB = 0x0000200000000000,
16_TB = 0x0000100000000000,
8_TB = 0x0000080000000000,
4_TB = 0x0000040000000000,
2_TB = 0x0000020000000000,
1_TB = 0x0000010000000000,
512_GB = 0x0000008000000000,
256_GB = 0x0000004000000000,
128_GB = 0x0000002000000000,
64_GB = 0x0000001000000000,
32_GB = 0x0000000800000000,
16_GB = 0x0000000400000000,
8_GB = 0x0000000200000000,
4_GB = 0x0000000100000000,
2_GB = 0x0000000080000000,
1_GB = 0x0000000040000000,
512_MB = 0x0000000020000000,
256_MB = 0x0000000010000000,
128_MB = 0x0000000008000000,
64_MB = 0x0000000004000000,
32_MB = 0x0000000002000000,
16_MB = 0x0000000001000000,
8_MB = 0x0000000000800000,
4_MB = 0x0000000000400000,
2_MB = 0x0000000000200000,
1_MB = 0x0000000000100000,
512_KB = 0x0000000000080000,
256_KB = 0x0000000000040000,
128_KB = 0x0000000000020000,
64_KB = 0x0000000000010000,
4_KB = 0x0000000000001000
3,3