ATTR_SPD_DRAM_DEVICE_TYPE TARGET_TYPE_DIMM DRAM Device Type. Located in DDR3/DDR4 SPD byte 2. uint8 DDR3 = 0x0b, DDR4 = 0x0c ATTR_SPD_MODULE_TYPE TARGET_TYPE_DIMM Module Type. Located in DDR3 SPD byte 3, bits 3-0. Note that CDIMM designation here is obsolete. See ATTR_SPD_CUSTOM uint8 CDIMM = 0x00, RDIMM = 0x01, UDIMM = 0x02, LRDIMM = 0x0b ATTR_SPD_CUSTOM TARGET_TYPE_DIMM Module Type is CUSTOM Located in DDR3 SPD byte 3, bit 7. (Most significant bit) If bit 7 (reserved) is a '1' then this attribute value should be set to YES uint8 NO = 0x0, YES = 0x1 ATTR_SPD_SDRAM_BANKS TARGET_TYPE_DIMM Number of banks. Located in DDR3 SPD byte 4, bits 6-4. uint8 B8 = 0x00, B16 = 0x01, B32 = 0x02, B64 = 0x03 ATTR_SPD_SDRAM_DENSITY TARGET_TYPE_DIMM DRAM Density. Located in DDR3 SPD byte 4, bits 3-0. uint8 D256MB = 0x00, D512Mb = 0x01, D1GB = 0x02, D2GB = 0x03, D4GB = 0x04, D8GB = 0x05, D16GB = 0x06 ATTR_SPD_SDRAM_ROWS TARGET_TYPE_DIMM Number of Rows. Located in DDR3 SPD byte 5, bits 5-3. uint8 R12 = 0x00, R13 = 0x01, R14 = 0x02, R15 = 0x03, R16 = 0x04 ATTR_SPD_SDRAM_COLUMNS TARGET_TYPE_DIMM Number of Columns. Located in DDR3 SPD byte 5, bits 2-0. uint8 C9 = 0x00, C10 = 0x01, C11 = 0x02, C12 = 0x03 ATTR_SPD_MODULE_NOMINAL_VOLTAGE TARGET_TYPE_DIMM Nominal voltage (bitmap). Located in DDR3 SPD byte 6, bits 2-0. uint8 NOTOP1_5 = 0x01, OP1_35 = 0x02, OP1_2X = 0x04 ATTR_SPD_NUM_RANKS TARGET_TYPE_DIMM Number of ranks. Located in DDR3 SPD byte 7, bits 5-3. uint8 R1 = 0x00, R2 = 0x01, R3 = 0x02, R4 = 0x03 ATTR_SPD_DRAM_WIDTH TARGET_TYPE_DIMM DRAM Width. Located in DDR3 SPD byte 7, bits 2-0. uint8 W4 = 0x00, W8 = 0x01, W16 = 0x02, W32 = 0x03 ATTR_SPD_MODULE_MEMORY_BUS_WIDTH TARGET_TYPE_DIMM Module Memory Bus Width. Located in DDR3 SPD byte 8, bits 2-0. uint8 W8 = 0x00, W16 = 0x01, W32 = 0x02, W64 = 0x03 ATTR_SPD_FTB_DIVIDEND TARGET_TYPE_DIMM Fine Timebase Dividend. Located in DDR3 SPD byte 9, bits 7-4. uint8 ATTR_SPD_FTB_DIVISOR TARGET_TYPE_DIMM Fine Timebase Divisor. Located in DDR3 SPD byte 9, bits 3-0. uint8 ATTR_SPD_MTB_DIVIDEND TARGET_TYPE_DIMM Medium Timebase Dividend. Located in DDR3 SPD byte 10. uint8 ATTR_SPD_MTB_DIVISOR TARGET_TYPE_DIMM Medium Timebase Divisor. Located in DDR3 SPD byte 11. uint8 ATTR_SPD_TCKMIN TARGET_TYPE_DIMM Minimum cycle time (tCKmin). Located in DDR3 SPD byte 12. uint8 ATTR_SPD_CAS_LATENCIES_SUPPORTED TARGET_TYPE_DIMM CAS Latencies supported (bitmap). Located in DDR3 SPD byte 14 (LSB) and byte 15. uint32 CL_18 = 0x00004000, CL_17 = 0x00002000, CL_16 = 0x00001000, CL_15 = 0x00000800, CL_14 = 0x00000400, CL_13 = 0x00000200, CL_12 = 0x00000100, CL_11 = 0x00000080, CL_10 = 0x00000040, CL_9 = 0x00000020, CL_8 = 0x00000010, CL_7 = 0x00000008, CL_6 = 0x00000004, CL_5 = 0x00000002, CL_4 = 0x00000001 ATTR_SPD_TAAMIN TARGET_TYPE_DIMM Minimum CAS Latency Time (tAAmin). Located in DDR3 SPD byte 16. uint8 ATTR_SPD_TWRMIN TARGET_TYPE_DIMM Minimum Write Recovery Time (tWRmin). Located in DDR3 SPD byte 17. uint8 ATTR_SPD_TRCDMIN TARGET_TYPE_DIMM Minimum RAS# to CAS# Delay Time (tRCDmin). Located in DDR3 SPD byte 18. uint8 ATTR_SPD_TRRDMIN TARGET_TYPE_DIMM Minimum Row Active to Row Active Delay Time (tRRDmin). Located in DDR3 SPD byte 19. uint8 ATTR_SPD_TRPMIN TARGET_TYPE_DIMM Minimum Row Precharge Delay Time (tRPmin). Located in DDR3 SPD byte 20. uint8 ATTR_SPD_TRASMIN TARGET_TYPE_DIMM Minimum Active to Precharge Delay Time (tRASmin). Located in DDR3 SPD byte 21, bits 3-0 and byte 22 (LSB). uint32 ATTR_SPD_TRCMIN TARGET_TYPE_DIMM Minimum Active to Active/Refresh Delay Time (tRCmin). Located in DDR3 SPD byte 21, bits 7-4 and byte 23 (LSB). uint32 ATTR_SPD_TRFCMIN TARGET_TYPE_DIMM Minimum Refresh Recovery Delay Time (tRFCmin). Located in DDR3 SPD byte 24 (LSB) and byte 25. uint32 ATTR_SPD_TWTRMIN TARGET_TYPE_DIMM Minimum Internal Write to Read Command Delay Time (tWTRmin). Located in DDR3 SPD byte 26. uint8 ATTR_SPD_TRTPMIN TARGET_TYPE_DIMM Minimum Internal Read to Precharge Command Delay Time (tRTPmin). Located in DDR3 SPD byte 27. uint8 ATTR_SPD_TFAWMIN TARGET_TYPE_DIMM Minimum Four Activate Window Delay Time (tFAWmin). Located in DDR3 SPD byte 28, bits 3-0 and byte 29 (LSB). uint32 ATTR_SPD_SDRAM_OPTIONAL_FEATURES TARGET_TYPE_DIMM SDRAM Optional Features (bitmap). Located in DDR3 SPD byte 30. uint8 DLL_OFF = 0x80, RZQ7 = 0x02, RZQ6 = 0x01 ATTR_SPD_SDRAM_THERMAL_AND_REFRESH_OPTIONS TARGET_TYPE_DIMM SDRAM Thermal and Refresh Options (bitmap). Located in DDR3 SPD byte 31. uint8 PASR = 0x80, ODTS = 0x08, ASR = 0x05, ETRR = 0x02, ETR = 0x01 ATTR_SPD_MODULE_THERMAL_SENSOR TARGET_TYPE_DIMM Module Thermal Sensor. Located in DDR3 SPD byte 32. uint8 PRESENT = 0x80, ACCURACY_MASK = 0x7F ATTR_SPD_SDRAM_DEVICE_TYPE TARGET_TYPE_DIMM SDRAM Device Type. Located in DDR3 SPD byte 33, bit 7. uint8 STANDARD_MONOLITHIC = 0x00, NON_STANDARD = 0x80 ATTR_SPD_SDRAM_DEVICE_TYPE_SIGNAL_LOADING TARGET_TYPE_DIMM SDRAM Device Type Signal Loading for stacked DRAMs. Located in DDR3 SPD byte 33, bits 1-0. uint8 NOT_SPECIFIED = 0x00, MULTI_LOAD_STACK = 0x01, SINGLE_LOAD_STACK = 0x02 ATTR_SPD_SDRAM_DIE_COUNT TARGET_TYPE_DIMM SDRAM Device Type Die Count. Located in DDR3 SPD byte 33, bits 6-4. uint8 ATTR_SPD_FINE_OFFSET_TCKMIN TARGET_TYPE_DIMM Fine Offset for SDRAM Minimum Cycle Time (tCKmin). Located in DDR3 SPD byte 34. uint8 ATTR_SPD_FINE_OFFSET_TAAMIN TARGET_TYPE_DIMM Fine Offset for Minimum CAS Latency Time (tAAmin). Located in DDR3 SPD byte 35. uint8 ATTR_SPD_FINE_OFFSET_TRCDMIN TARGET_TYPE_DIMM Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin). Located in DDR3 SPD byte 36. uint8 ATTR_SPD_FINE_OFFSET_TRPMIN TARGET_TYPE_DIMM Fine Offset for Minimum Row Precharge Delay Time (tRPmin). Located in DDR3 SPD byte 37. uint8 ATTR_SPD_FINE_OFFSET_TRCMIN TARGET_TYPE_DIMM Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin). Located in DDR3 SPD byte 38. uint8 ATTR_SPD_NUM_OF_REGISTERS_USED_ON_RDIMM TARGET_TYPE_DIMM Number of Registers used on RDIMM. Located in DDR3 SPD byte 63 bits 1-0. uint8 ATTR_SPD_MODULE_SPECIFIC_SECTION TARGET_TYPE_DIMM Module Specific Section. Located in DDR3 SPD bytes 60d - 116d. uint8 57 ATTR_SPD_MODULE_ID_MODULE_MANUFACTURERS_JEDEC_ID_CODE TARGET_TYPE_DIMM Module ID: Module Manufacturer's JEDEC ID Code. Located in DDR3 SPD bytes 117 (LSB) to 118. uint32 ATTR_SPD_MODULE_ID_MODULE_MANUFACTURING_LOCATION TARGET_TYPE_DIMM Module ID: Module Manufacturing Location. Located in DDR3 SPD byte 119. uint8 ATTR_SPD_MODULE_ID_MODULE_MANUFACTURING_DATE TARGET_TYPE_DIMM Module ID: Module Manufacturing Date. Located in DDR3 SPD bytes 120 (BCD year) to byte 121 (BCD week) (LSB). uint32 ATTR_SPD_MODULE_ID_MODULE_SERIAL_NUMBER TARGET_TYPE_DIMM Module ID: Module Serial Number. Located in DDR3 SPD bytes 122 (LSB) to 125. uint32 ATTR_SPD_CYCLICAL_REDUNDANCY_CODE TARGET_TYPE_DIMM Cyclical Redundancy Code. Located in DDR3 SPD bytes 126 (LSB) to 127. uint32 ATTR_SPD_MODULE_PART_NUMBER TARGET_TYPE_DIMM Module Part Number. Located in DDR3 SPD bytes 128 - 145. uint8 18 ATTR_SPD_MODULE_REVISION_CODE TARGET_TYPE_DIMM Module Revision Code. Located in DDR3 SPD bytes 146 (LSB) to 147. uint32 ATTR_SPD_DRAM_MANUFACTURER_JEDEC_ID_CODE TARGET_TYPE_DIMM DRAM Manufacturer JEDEC ID Code. Located in DDR3 SPD bytes 148 (LSB) to 149. uint32 ATTR_SPD_BAD_DQ_DATA TARGET_TYPE_DIMM Bad DQ pin data stored in DIMM SPD. This data is in a special format. This must only be called by a firmware HWP that knows how to decode the data. HWP/PLAT firmware that needs to get/set the Bad DQ Bitmap from a Centaur DQ point of view must call the dimmBadDqBitmapAccessHwp HWP. uint8 80 ATTR_VPD_DRAM_ADDRESS_MIRRORING TARGET_TYPE_DIMM The C-DIMM ranks that have address mirroring. This data is in the Record:VSPD, Keyword:AM field in C-DIMM VPD. This attribute is only valid for C-DIMMs, an error should be returned if queried from IS-DIMMs. Note: Muliple ranks can be mirrored. uint8 RANK0_MIRRORED = 0x08, RANK1_MIRRORED = 0x04, RANK2_MIRRORED = 0x02, RANK3_MIRRORED = 0x01