ATTR_CEN_DQ_TO_DIMM_CONN_DQ
TARGET_TYPE_DIMM
Centaur DQ to DIMM connector DQ mapping.
Uint8 value for each Centaur DQ (0-79).
The value is the corresponding DIMM Connector DQ.
Therefore if (data[2] == 60) then Centaur DQ 2 maps to DIMM DQ 60
If the logical DIMM is on a Centaur-DIMM then the value is the same as the
array index because there is no DIMM connector.
If the logical DIMM is an IS-DIMM then the value depends on board wiring.
uint8
80
ATTR_MBA_PORT
TARGET_TYPE_DIMM
MBA Chiplet port this DIMM is connected to
uint8
ATTR_MBA_DIMM
TARGET_TYPE_DIMM
MBA port DIMM number of this DIMM
uint8
ATTR_BAD_DQ_BITMAP
TARGET_TYPE_DIMM
Bad DQ bitmap from a Centaur:MBA point of view.
The data is a 10 byte bitmap for each of 4 possible ranks.
The bad DQ data is stored in DIMM SPD, it is stored in a special format
and is translated to a DIMM Connector point of view for IS-DIMMs.
All of these details are hidden from the user of this attribute.
uint8
4 10
ATTR_VPD_DIMM_SPARE
TARGET_TYPE_DIMM
Spare DRAM availability for each rank on the DIMM.
There are 8 DQ lines to spare DRAMs.
- NO_SPARE: No spare DRAMs
- LOW_NIBBLE: x4 DRAMs in use, one spare DRAM connected to SP_DQ0-3
- HIGH_NIBBLE: x4 DRAMs in use, one spare DRAM connected to SP_DQ4-7
- FULL_BYTE: Either
1/ x4 DRAMs in use, two spare DRAMs connected to SP_DQ0-7
2/ x8 DRAMs in use, one spare DRAM connected to SP_DQ0-7
For C-DIMMs, this is in a VPD field : Record:VSPD, Keyword:AM
For IS-DIMMs, the platform should return 0 indicating
no spares for any rank.
The top 2 bits are for rank 0 e.g:
if (((val AND 0xc0) >> 6) ==
ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE) {...}
The next 2 bits are for rank 1 e.g:
if (((val AND 0x30) >> 4) ==
ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE) {...}
The next 2 bits are for rank 2 e.g:
if (((val AND 0x0c) >> 2) ==
ENUM_ATTR_VPD_DIMM_SPARE_HIGH_NIBBLE) {...}
The bottom 2 bits are for rank 3 e.g:
if ((val AND 0x03) ==
ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE) {...}
uint8
NO_SPARE = 0x00,
LOW_NIBBLE = 0x01,
HIGH_NIBBLE = 0x02,
FULL_BYTE = 0x03