ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, it sets Safe mode throttles using sys attributes ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP and ATTR_MRW_MEM_THROTTLE_DENOMINATOR. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, it allow RCE to be reported even if we also have chip marks or symbol marks in place. MBSTR(60)=1 and MBSECC(16)=1, DD2 is set. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_ENABLE_PAGE_MODE_FOR_RRQ TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, it allows super fast read to go faster. MBA_RRQ0Q(57) cfg_rrq_opp_page_mode_en RW DD2 is set. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. For HW259719. If true, Trace LCL_CLK_GATE_CTRL will be enabled. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_ENABLE_NM_CHANGE_AFTER_SYNC TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. IF TRUE, ENABLE NM change after sync. This fix that is going into DD2 (to use values in N/M shadow registers when a sync command is seen), we should be able to change M to a different value if we wanted to without any issues. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. IF TRUE, Enable ROW HAMMER ENHANCEMENT FOR DD2. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE TARGET_TYPE_MEMBUF_CHIP Returns true if the chip needs to fix the fir_mask register in the DDRPHY. This is for HW217419. True if: Centaur EC 10 ENUM_ATTR_NAME_CENTAUR 0x10 EQUAL ATTR_CENTAUR_EC_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL TARGET_TYPE_MEMBUF_CHIP Controls the ddr_phy_reset procedure. When set to TRUE, the procedure will continue with processing other DP18 blocks, if one fails. In DD2, this attribute must be set to false so that the failing hardware (centaur) is marked as bad and not the DIMM. Set by firwmare using the EC level or by a MRW ENUM_ATTR_NAME_CENTAUR 0x10 EQUAL ATTR_CENTAUR_EC_MSS_READ_PHASE_SELECT_RESET TARGET_TYPE_MEMBUF_CHIP If true, then training and periodic training needs to make adjustments to the read phase select. In DD2, this is expected to be fixed. ENUM_ATTR_NAME_CENTAUR 0x10 EQUAL ATTR_CENTAUR_EC_CHECK_L4_CACHE_ENABLE_UNKNOWN TARGET_TYPE_MEMBUF_CHIP If true then mss_get_cen_ecid needs to read an ECBIT from the ECID in order to determine if the L4 Cache Enable data in the ECID is in an unknown state. This is true for Centaur 1.* ENUM_ATTR_NAME_CENTAUR 0x20 LESS_THAN ATTR_MSS_DISABLE1_REG_FIXED TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If false, then draminit_training will also set the wrclk registers to disable appropriate dqs based on the bad bit map attribute and the swizzle(board dependent). If true, draminit_training will just do the default disable0 and disable1 registers. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_MSS_DISABLE1_RDCLK_REG_FIXED TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If false, then draminit_training will also set the rdclk registers to disable appropriate dqs based on the bad bit map attribute and the swizzle(board dependent). If true, draminit_training will just do the default disable0 and disable1 registers. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_ECID_CONTAINS_PORT_LOGIC_BAD_INDICATION TARGET_TYPE_MEMBUF_CHIP If true then mss_get_cen_ecid reads the ECID bits to determine if logic on either of the ports are good. For DD2, these bits are not used for this purpose and so the check is not made. This is true for Centaur 1.* ENUM_ATTR_NAME_CENTAUR 0x20 LESS_THAN ATTR_CENTAUR_EC_MCBIST_RANDOM_DATA_GEN TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If false, this will enable the power bus ECC and FIFO mode workarounds of DD1.x for Random Data . ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_MCBIST_TRAP_RESET TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If false, work around for error trap reset logic which clears trap registers will be enabled. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If false, this will enable workaround for start and end counters for Random Addressing. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_SCOM_PARITY_ERROR_HW244827_FIXED TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If false, draminit_mc will execute a putscom to clear the scom parity error fir for all densities on DD1.X parts. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_HW217608_MBSPA_0_CMD_COMPLETE_ATTN_FIXED TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, MBSPA bit 8 is masked, and MBSPA bit 0 is unmasked and configured to report when maint cmd either stops clean or stops on error. Otherwise, MBSPA bit 0 is masked, and MBSPA bit 8 is unmasked. NOTE: For DD1 when using MBSPA bit 8, a scan init is needed to enable the WAT workaround allows bit 8 to report when maint cmd either stops clean or stops on error. The scan init is enabled for DD1 and disabled for DD2, but does not use this same attribute. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_USE_FIRST_SUPPLIER_FOR_INVALID_MODULE_ID TARGET_TYPE_MEMBUF_CHIP The getMBvpdSlopeInterceptData Attribute Accessor returns power data from the MW (master) and MV (supplier) Centaur DIMM VPD. For MV attributes, the Attribute Accessor finds the Manufacturer-ID from JEDEC SPD (#I) and then matches it to a Supplier-ID in the array of supplier entries in the MV field . For Centaur DD 1.X chips, the Manufacturer-ID may be invalid. The getMBvpdSlopeInterceptData Attribute Accessor, if it does not find a matching Supplier-ID in MV, will return the data for the first supplier on Centaur DD 1.X chips. This is true for Centaur 1.* ENUM_ATTR_NAME_CENTAUR 0x20 LESS_THAN ATTR_CENTAUR_EC_ENABLE_SAFEMODE_THROTTLE TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, this will enable safe mode throttle values to be set during the IPL in mss_thermal_init. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_DD2_FIR_BIT_DEFN_CHANGES TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, mss_unmask_errors.C will use the DD2 FIR bit definitions when setting FIR action regs and masks. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_RDCLK_PR_UPDATE_HW236658_FIXED TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If false, draminit_mc will execute a putscom to set bit 52 (PER_RDCLK_UPDATE_DISABLE) of DP18 Read Diag Cfg 5 on DD1.X parts. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CENTAUR_EC_DD2_ENABLE_EXIT_POINT_1 TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, exit point 1 will be enabled if any mark in markstore. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL