ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL
TARGET_TYPE_MEMBUF_CHIP
Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. For HW259719. If true, Trace LCL_CLK_GATE_CTRL will be enabled.
ENUM_ATTR_NAME_CENTAUR
0x20
GREATER_THAN_OR_EQUAL
ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE
TARGET_TYPE_MEMBUF_CHIP
Returns true if the chip needs to fix the fir_mask register in the DDRPHY. This is for HW217419.
True if: Centaur EC 10
ENUM_ATTR_NAME_CENTAUR
0x10
EQUAL
ATTR_CENTAUR_EC_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL
TARGET_TYPE_MEMBUF_CHIP
Controls the ddr_phy_reset procedure. When set to TRUE, the procedure will continue with processing other DP18 blocks, if one fails. In DD2, this attribute must be set to false so that the failing hardware (centaur) is marked as bad and not the DIMM. Set by firwmare using the EC level or by a MRW
ENUM_ATTR_NAME_CENTAUR
0x10
EQUAL
ATTR_CENTAUR_EC_MSS_READ_PHASE_SELECT_RESET
TARGET_TYPE_MEMBUF_CHIP
If true, then training and periodic training needs to make adjustments to the read phase select.
In DD2, this is expected to be fixed.
ENUM_ATTR_NAME_CENTAUR
0x10
EQUAL
ATTR_CENTAUR_EC_CHECK_L4_CACHE_ENABLE_UNKNOWN
TARGET_TYPE_MEMBUF_CHIP
If true then mss_get_cen_ecid needs to read an ECBIT from the ECID in
order to determine if the L4 Cache Enable data in the ECID is in an
unknown state.
This is true for Centaur 1.*
ENUM_ATTR_NAME_CENTAUR
0x20
LESS_THAN
ATTR_MSS_DISABLE1_REG_FIXED
TARGET_TYPE_MEMBUF_CHIP
Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If false, then draminit_training will also set the wrclk registers to disable appropriate dqs based on the bad bit map attribute and the swizzle(board dependent). If true, draminit_training will just do the default disable0 and disable1 registers.
ENUM_ATTR_NAME_CENTAUR
0x20
GREATER_THAN_OR_EQUAL