# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PCIE.rule $
#
# OpenPOWER HostBoot Project
#
# COPYRIGHT International Business Machines Corp. 2012,2014
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

################################################################################
# PCIE Chiplet Registers
################################################################################

rule PcieChipletFir
{
  CHECK_STOP:
     (PCIE_CHIPLET_CS_FIR       & `1EE0000000000000`) & ~PCIE_CHIPLET_FIR_MASK;
  RECOVERABLE:
    ((PCIE_CHIPLET_RE_FIR >> 2) & `1EE0000000000000`) & ~PCIE_CHIPLET_FIR_MASK;
};

group gPcieChipletFir filter singlebit
{
    /** PCIE_CHIPLET_FIR[3]
     *  Attention from LFIR
     */
    (PcieChipletFir, bit(3)) ? analyze(gPcieLFir);

    /** PCIE_CHIPLET_FIR[4|5|6]
     *  Attention from PCICLOCKFIR (0-2)
     */
    (PcieChipletFir, bit(4|5|6)) ? defaultMaskedError;

    /** PCIE_CHIPLET_FIR[8]
     *  Attention from PBFFIR
     */
    #PBFFIR has been masked. Retaining the register for FFDC purpose.
    (PcieChipletFir, bit(8)) ? defaultMaskedError;

    /** PCIE_CHIPLET_FIR[9|10]
     *  Attention from IOPCIFIR (0-1)
     */
    (PcieChipletFir, bit(9|10)) ? analyze(gIopPciFir);
};

rule PcieChipletSpa
{
    SPECIAL: PCIE_CHIPLET_SPA & ~PCIE_CHIPLET_SPA_MASK;
};

group gPcieChipletSpa filter singlebit
{
    /** PCIE_CHIPLET_SPA[0]
     *  Attention from PBFFIR
     */
    (PcieChipletSpa, bit(0)) ? defaultMaskedError;
};

################################################################################
# PCIE Chiplet LFIR
################################################################################
# based on p8dd1_mss_FFDC_59.xls
################################################################################

rule PcieLFir
{
  CHECK_STOP:  PCIE_LFIR & ~PCIE_LFIR_MASK & ~PCIE_LFIR_ACT0 & ~PCIE_LFIR_ACT1;
  RECOVERABLE: PCIE_LFIR & ~PCIE_LFIR_MASK & ~PCIE_LFIR_ACT0 &  PCIE_LFIR_ACT1;
};

group gPcieLFir filter singlebit
{
    /** PCIE_LFIR[0]
     *  CFIR internal parity error
     */
    (PcieLFir, bit(0)) ? SelfHighThr32PerDay;

    /** PCIE_LFIR[1]
     *  Local errors from GPIO (PCB error)
     */
    (PcieLFir, bit(1)) ? defaultMaskedError;

    /** PCIE_LFIR[2]
     *  Local errors from CC (PCB error)
     */
    (PcieLFir, bit(2)) ? defaultMaskedError;

    /** PCIE_LFIR[3]
     *  Local errors from CC (OPCG, parity, scan collision, ...)
     */
    (PcieLFir, bit(3)) ? callout2ndLvlMedThr32NoGard;

    /** PCIE_LFIR[4]
     *  Local errors from PSC (PCB error)
     */
    (PcieLFir, bit(4)) ? defaultMaskedError;

    /** PCIE_LFIR[5]
     *  Local errors from PSC (parity error)
     */
    (PcieLFir, bit(5)) ? defaultMaskedError;

    /** PCIE_LFIR[6]
     *  Local errors from Thermal (parity error)
     */
    (PcieLFir, bit(6)) ? defaultMaskedError;

    /** PCIE_LFIR[7]
     *  Local errors from Thermal (PCB error)
     */
    (PcieLFir, bit(7)) ? defaultMaskedError;

    /** PCIE_LFIR[8|9]
     *  Local errors from Thermal (Trip error)
     */
    (PcieLFir, bit(8|9)) ? defaultMaskedError;

    /** PCIE_LFIR[10|11]
     *  Local errors from Trace Array ( error)
     */
    (PcieLFir, bit(10|11)) ? defaultMaskedError;

    /** PCIE_LFIR[12:20]
     *  Unused local errors
     */
    (PcieLFir, bit(12|13|14|15|16|17|18|19|20)) ? defaultMaskedError;

    /** PCIE_LFIR[21:30]
     *  Unused local errors
     */
    (PcieLFir, bit(21|22|23|24|25|26|27|28|29|30)) ? defaultMaskedError;

    /** PCIE_LFIR[31:39]
     *  Unused local errors
     */
    (PcieLFir, bit(31|32|33|34|35|36|37|38|39)) ? defaultMaskedError;

    /** PCIE_LFIR[40]
     *  Malfunction alert (local xstop in another chiplet)
     */
    (PcieLFir, bit(40)) ? defaultMaskedError;
};

################################################################################
# PCIE Chiplet IOPCIFIRs
################################################################################

#        All these FIRs should have the same bit definition. Ideally, we want
#        to have only one copy of the bit definition. Currently rule code
#        parser does not have the support for something like this.
#        Maybe we can add this as a later feature.

################################################################################
# based on p8dd1_mss_FFDC_59.xls
################################################################################

rule IopPciFir_0
{
  CHECK_STOP:
    IOPCIFIR_0 & ~IOPCIFIR_0_MASK & ~IOPCIFIR_0_ACT0 & ~IOPCIFIR_0_ACT1;
  RECOVERABLE:
    IOPCIFIR_0 & ~IOPCIFIR_0_MASK & ~IOPCIFIR_0_ACT0 &  IOPCIFIR_0_ACT1;
};

rule IopPciFir_1
{
  CHECK_STOP:
    IOPCIFIR_1 & ~IOPCIFIR_1_MASK & ~IOPCIFIR_1_ACT0 & ~IOPCIFIR_1_ACT1;
  RECOVERABLE:
    IOPCIFIR_1 & ~IOPCIFIR_1_MASK & ~IOPCIFIR_1_ACT0 &  IOPCIFIR_1_ACT1;
};

group gIopPciFir filter singlebit
{
    /** IOPCIFIR_0[0]
     * FIR_STATUS_REG_G2_PLL_CCERR_STATUS
     */
    (IopPciFir_0, bit(0)) ? calloutPhbBothClks_0;

    /** IOPCIFIR_1[0]
     * FIR_STATUS_REG_G2_PLL_CCERR_STATUS
     */
    (IopPciFir_1, bit(0)) ? calloutPhbBothClks_1;

    /** IOPCIFIR_0[1]
     *  FIR_STATUS_REG_G3_PLL_CCERR_STATUS
     */
    (IopPciFir_0, bit(1)) ? calloutPhbBothClks_0;

    /** IOPCIFIR_1[1]
     *  FIR_STATUS_REG_G3_PLL_CCERR_STATUS
     */
    (IopPciFir_1, bit(1)) ? calloutPhbBothClks_1;

    /** IOPCIFIR_0[2]
     *  FIR_STATUS_REG_TX_A_ERR_STATUS
     */
    (IopPciFir_0, bit(2)) ? calloutPhbClkA_0_noGard;

    /** IOPCIFIR_1[2]
     *  FIR_STATUS_REG_TX_A_ERR_STATUS
     */
    (IopPciFir_1, bit(2)) ? calloutPhbClkA_1_noGard;

    /** IOPCIFIR_0[3]
     *  FIR_STATUS_REG_TX_B_ERR_STATUS
     */
    (IopPciFir_0, bit(3)) ? calloutPhbClkB_0_noGard;

    /** IOPCIFIR_1[3]
     *  FIR_STATUS_REG_TX_B_ERR_STATUS
     */
    (IopPciFir_1, bit(3)) ? calloutPhbClkB_1_noGard;

    /** IOPCIFIR_0[4]
     *  FIR_STATUS_REG_RX_A_ERR_STATUS
     */
    (IopPciFir_0, bit(4)) ? calloutPhbClkA_0_noGard;

    /** IOPCIFIR_1[4]
     *  FIR_STATUS_REG_RX_A_ERR_STATUS
     */
    (IopPciFir_1, bit(4)) ? calloutPhbClkA_1_noGard;

    /** IOPCIFIR_0[5]
     *  FIR_STATUS_REG_RX_B_ERR_STATUS
     */
    (IopPciFir_0, bit(5)) ? calloutPhbClkB_0_noGard;

    /** IOPCIFIR_1[5]
     *  FIR_STATUS_REG_RX_B_ERR_STATUS
     */
    (IopPciFir_1, bit(5)) ? calloutPhbClkB_1_noGard;

    /** IOPCIFIR_0[6]
     *  FIR_STATUS_REG_ZCAL_B_ERR_STATUS
     */
    (IopPciFir_0, bit(6)) ? calloutPhbBothClks_0;

    /** IOPCIFIR_1[6]
     *  FIR_STATUS_REG_ZCAL_B_ERR_STATUS
     */
    (IopPciFir_1, bit(6)) ? calloutPhbBothClks_1;

    /** IOPCIFIR_0[7]
     *  FIR_STATUS_REG_SCOM_FIR_PERR0_STATUS
     */
    (IopPciFir_0, bit(7)) ? defaultMaskedError;

    /** IOPCIFIR_1[7]
     *  FIR_STATUS_REG_SCOM_FIR_PERR0_STATUS
     */
    (IopPciFir_1, bit(7)) ? defaultMaskedError;

    /** IOPCIFIR_0[8]
     *  FIR_STATUS_REG_SCOM_FIR_PERR1_STATUS
     */
    (IopPciFir_0, bit(8)) ? defaultMaskedError;

    /** IOPCIFIR_1[8]
     *  FIR_STATUS_REG_SCOM_FIR_PERR1_STATUS
     */
    (IopPciFir_1, bit(8)) ? defaultMaskedError;
};

################################################################################
# Actions specific to PCIE chiplet
################################################################################

/**callout PHB associated with IOPCIFIR0 clkA, no garding */
actionclass calloutPhbClkA_0_noGard
{
    funccall("calloutPhbClkA_0");
    threshold1;
    gard(NoGard);
};

/**callout PHB associated with IOPCIFIR0 clkB, no garding */
actionclass calloutPhbClkB_0_noGard
{
    funccall("calloutPhbClkB_0");
    threshold1;
    gard(NoGard);
};

/**callout PHB associated with IOPCIFIR1 clkA, no garding */
actionclass calloutPhbClkA_1_noGard
{
    funccall("calloutPhbClkA_1");
    threshold1;
    gard(NoGard);
};

/**callout PHB associated with IOPCIFIR1 clkB, no garding */
actionclass calloutPhbClkB_1_noGard
{
    funccall("calloutPhbClkB_1");
    threshold1;
    gard(NoGard);
};

/** callout all PHB associated with IOPCIFIR0, no garding */
actionclass calloutPhbBothClks_0
{
    funccall("calloutPhbBothClks_0");
    threshold1;
    gard(NoGard);
};

/** callout all PHB associated with IOPCIFIR1, no garding */
actionclass calloutPhbBothClks_1
{
    funccall("calloutPhbBothClks_1");
    threshold1;
    gard(NoGard);
};