# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2012,2018
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

################################################################################
# NEST Chiplet Registers
################################################################################

rule NestChipletFir
{
  CHECK_STOP:
     (NEST_CHIPLET_CS_FIR       & `17fe000000000000`) & ~NEST_CHIPLET_FIR_MASK;
  UNIT_CS:
     (NEST_CHIPLET_CS_FIR       & `17fe000000000000`) & ~NEST_CHIPLET_FIR_MASK;
  RECOVERABLE:
    ((NEST_CHIPLET_RE_FIR >> 2) & `17fc000000000000`) & ~NEST_CHIPLET_FIR_MASK;
};

group gNestChipletFir filter priority( 3, 6, 5, 7 )
{
    # NOTE: The MBIFIR must be analyzed before the DMIFIR and both the MBIFIR
    # and DMIFIR must be analyzed before the MBSFIR. All other FIRs will be
    # analyzed in order.

    /** NEST_CHIPLET_FIR[3]
     *  Attention from LFIR
     */
    (NestChipletFir, bit(3)) ? analyze(gNestLFir);

    /** NEST_CHIPLET_FIR[5]
     *  Attention from DMIFIR
     */
    (NestChipletFir, bit(5)) ? analyze(gDmiFir);

    /** NEST_CHIPLET_FIR[6]
     *  Attention from MBIFIR
     */
    (NestChipletFir, bit(6)) ? analyze(gMbiFir);

    /** NEST_CHIPLET_FIR[7]
     *  Attention from MBSFIR
     */
    (NestChipletFir, bit(7)) ? analyze(gMbsFir);

    /** NEST_CHIPLET_FIR[8|9]
     *  Attention from MCBISTFIRs
     */
    (NestChipletFir, bit(8|9)) ? analyze(gMcbistFir);

    /** NEST_CHIPLET_FIR[10|11]
     *  Attention from MBSECCFIRs
     */
    (NestChipletFir, bit(10|11)) ? analyze(gMbsEccFir);

    /** NEST_CHIPLET_FIR[12]
     *  Attention from NESTFBISTFIR
     */
    (NestChipletFir, bit(12))? defaultMaskedError;

    /** NEST_CHIPLET_FIR[13]
     *  Attention from SCACFIR
     */
    (NestChipletFir, bit(13)) ? analyze(gScacFir);

    /** NEST_CHIPLET_FIR[14]
     *  Attention from MBS secure FIR
     */
    (NestChipletFir, bit(14))? analyze(gMbsSecureFir); # Checkstop only
};

################################################################################
# NEST Chiplet LFIR
################################################################################
# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls

rule NestLFir
{
  CHECK_STOP:  NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & ~NEST_LFIR_ACT1;
  UNIT_CS:     NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & ~NEST_LFIR_ACT1;
  RECOVERABLE: NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 &  NEST_LFIR_ACT1;
};

group gNestLFir filter singlebit,
                       secondarybits(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,
                                     17,18,19,20,21,22,23,24,25,26,27,28,29,30,
                                     31,32,33,34,35,36,37,38,39,40)
{
    /** NEST_LFIR[0]
     *  CFIR internal parity error
     */
    (NestLFir, bit(0)) ? thresholdAndMask_self;

    /** NEST_LFIR[1]
     *  Local errors from GPIO (PCB error)
     */
    (NestLFir, bit(1)) ? defaultMaskedError;

    /** NEST_LFIR[2]
     *  Local errors from CC (PCB error)
     */
    (NestLFir, bit(2)) ? defaultMaskedError;

    /** NEST_LFIR[3]
     *  Local errors from CC (OPCG, parity, scan collision, ...)
     */
    (NestLFir, bit(3)) ? defaultMaskedError;

    /** NEST_LFIR[4]
     *  Local errors from PSC (PCB error)
     */
    (NestLFir, bit(4)) ? defaultMaskedError;

    /** NEST_LFIR[5]
     *  Local errors from PSC (parity error)
     */
    (NestLFir, bit(5)) ? defaultMaskedError;

    /** NEST_LFIR[6]
     *  Local errors from Thermal (parity error)
     */
    (NestLFir, bit(6)) ? defaultMaskedError;

    /** NEST_LFIR[7]
     *  Local errors from Thermal (PCB error)
     */
    (NestLFir, bit(7)) ? defaultMaskedError;

    /** NEST_LFIR[8:10]
     *  Local errors from Thermal (Trip error)
     */
    (NestLFir, bit(8|9|10)) ? defaultMaskedError;

    /** NEST_LFIR[11:12]
     *  Local errors from Trace Array ( error)
     */
    (NestLFir, bit(11|12)) ? defaultMaskedError;

    /** NEST_LFIR[40]
     *  Malfunction alert
     */
    (NestLFir, bit(40)) ? defaultMaskedError;
};

################################################################################
#  NEST Chiplet DMIFIR
################################################################################
# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls

rule DmiFir
{
    CHECK_STOP:  DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & ~DMIFIR_ACT1;
    UNIT_CS:     DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & ~DMIFIR_ACT1;
    RECOVERABLE: DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 &  DMIFIR_ACT1;
};

group gDmiFir filter priority( 10,               # Channel failure
                                2, 11, 12, 9  ), # Recoverable
                     secondarybits(0,1,3,4,5,6,7,8,9,11,12,13,14,15,16,17,18,19,
                                   20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,
                                   35,36,37,38,39,40,41,42,43,44,45,46,47,48,49)
{
    /** DMIFIR[0]
     *  FIR_RX_INVALID_STATE_OR_PARITY_ERROR
     */
    (DmiFir, bit(0)) ? defaultMaskedError;

    /** DMIFIR[1]
     *  FIR_TX_INVALID_STATE_OR_PARITY_ERROR
     */
    (DmiFir, bit(1)) ? defaultMaskedError;

    /** DMIFIR[2]
     *  FIR_GCR_HANG_ERROR
     */
    (DmiFir, bit(2)) ? SelfHighThr1;

    /** DMIFIR[3:7]
     *  Reserved
     */
    (DmiFir, bit(3|4|5|6|7)) ? defaultMaskedError;

    /** DMIFIR[8]
     *  Training Error
     */
    (DmiFir, bit(8)) ? defaultMaskedError;

    /** DMIFIR[9]
     *  Spare Deployed
     */
    (DmiFir, bit(9)) ? spareDeployed;

    /** DMIFIR[10]
     *  Max Spares Exceeded
     */
    (DmiFir, bit(10)) ? maxSparesExceeded;

    /** DMIFIR[11]
     *  Recalibration or Dynamic Repair Error
     */
    (DmiFir, bit(11)) ? calloutDmiBusTh1;

    /** DMIFIR[12]
     *  Too Many Bus Errors
     */
    (DmiFir, bit(12)) ? calloutDmiBusTh1;

    /** DMIFIR[13:15]
     *  Reserved
     */
    (DmiFir, bit(13|14|15)) ? defaultMaskedError;

    /** DMIFIR[16:23]
     *  FIR_RX_BUS1 unused
     */
    (DmiFir, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError;

    /** DMIFIR[24:31]
     *  FIR_RX_BUS2 unused
     */
    (DmiFir, bit(24|25|26|27|28|29|30|31)) ? defaultMaskedError;

    /** DMIFIR[32:39]
     *  FIR_RX_BUS3 unused
     */
    (DmiFir, bit(32|33|34|35|36|37|38|39)) ? defaultMaskedError;

    /** DMIFIR[40:47]
     *  FIR_RX_BUS4 unused
     */
    (DmiFir, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError;

    /** DMIFIR[48]
     *  FIR_SCOMFIR_ERROR
     */
    (DmiFir, bit(48)) ? thresholdAndMask_self;

    /** DMIFIR[49]
     *  FIR_SCOMFIR_ERROR_CLONE
     */
    (DmiFir, bit(49)) ? thresholdAndMask_self;
};

################################################################################
#  NEST Chiplet ScacFir
################################################################################

rule ScacFir
{
    CHECK_STOP:  SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & ~SCACFIR_ACT1;
    UNIT_CS:     SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & ~SCACFIR_ACT1;
    RECOVERABLE: SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 &  SCACFIR_ACT1;
};

group gScacFir filter singlebit,
                      secondarybits(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,
                                    18,19,20,21,22,23,24,27,28,29,30,31,32,33,
                                    34,35,36)
{
    /** SCACFIR[0]
     *  SCAC_LFIR_I2CMINVADDR
     */
    (ScacFir, bit(0)) ? defaultMaskedError;

    /** SCACFIR[1]
     *  SCAC_LFIR_I2CMINVWRITE
     */
    (ScacFir, bit(1)) ? defaultMaskedError;

    /** SCACFIR[2]
     *  SCAC_LFIR_I2CMINVREAD
     */
    (ScacFir, bit(2)) ? defaultMaskedError;

    /** SCACFIR[3]
     *  SCAC_LFIR_I2CMAPAR
     */
    (ScacFir, bit(3)) ? defaultMaskedError;

    /** SCACFIR[4]
     *  SCAC_LFIR_I2CMPAR
     */
    (ScacFir, bit(4)) ? defaultMaskedError;

    /** SCACFIR[5]
     *  SCAC_LFIR_I2CMLBPAR
     */
    (ScacFir, bit(5)) ? defaultMaskedError;

    /** SCACFIR[6:9]
     *  Expansion (Reserved at 0 for exernal macro expansion reporting)
     */
    (ScacFir, bit(6|7|8|9)) ? defaultMaskedError;

    /** SCACFIR[10]
     *  SCAC_LFIR_I2CMINVCMD
     */
    (ScacFir, bit(10)) ? defaultMaskedError;

    /** SCACFIR[11]
     *  SCAC_LFIR_I2CMPERR
     */
    (ScacFir, bit(11)) ? defaultMaskedError;

    /** SCACFIR[12]
     *  SCAC_LFIR_I2CMOVERRUN
     */
    (ScacFir, bit(12)) ? defaultMaskedError;

    /** SCACFIR[13]
     *  SCAC_LFIR_I2CMACCESS
     */
    (ScacFir, bit(13)) ? defaultMaskedError;

    /** SCACFIR[14]
     *  SCAC_LFIR_I2CMARB
     */
    (ScacFir, bit(14)) ? defaultMaskedError;

    /** SCACFIR[15]
     *  SCAC_LFIR_I2CMNACK
     */
    (ScacFir, bit(15)) ? defaultMaskedError;

    /** SCACFIR[16]
     *  SCAC_LFIR_I2CMSTOP
     */
    (ScacFir, bit(16)) ? defaultMaskedError;

    /** SCACFIR[17]
     *  SCAC_LFIR_LOCALPIB1
     */
    (ScacFir, bit(17)) ? defaultMaskedError;

    /** SCACFIR[18]
     *  SCAC_LFIR_LOCALPIB2
     */
    (ScacFir, bit(18)) ? defaultMaskedError;

    /** SCACFIR[19]
     *  SCAC_LFIR_LOCALPIB3
     */
    (ScacFir, bit(19)) ? defaultMaskedError;

    /** SCACFIR[20]
     *  SCAC_LFIR_LOCALPIB4
     */
    (ScacFir, bit(20)) ? defaultMaskedError;

    /** SCACFIR[21]
     *  SCAC_LFIR_LOCALPIB5
     */
    (ScacFir, bit(21)) ? defaultMaskedError;

    /** SCACFIR[22]
     *  SCAC_LFIR_LOCALPIB6
     */
    (ScacFir, bit(22)) ? defaultMaskedError;

    /** SCACFIR[23]
     *  SCAC_LFIR_LOCALPIB7
     */
    (ScacFir, bit(23)) ? defaultMaskedError;

    /** SCACFIR[24]
     *  SCAC_LFIR_STALLERROR
     */
    (ScacFir, bit(24)) ? defaultMaskedError;

    /** SCACFIR[25]
     *  SCAC_LFIR_REGPARERR
     */
    (ScacFir, bit(25)) ? SelfMedThr1UE;

    /** SCACFIR[26]
     *  SCAC_LFIR_REGPARERRX
     */
    (ScacFir, bit(26)) ? SelfMedThr1UE;

    /** SCACFIR[32]
     *  SCAC_LFIR_SMERR
     */
    (ScacFir, bit(32)) ? SelfMedThr1;

    /** SCACFIR[33]
     *  SCAC_LFIR_REGACCERR
     */
    (ScacFir, bit(33)) ? callout2ndLvlMedThr1dumpSh;

    /** SCACFIR[34]
     *  SCAC_LFIR_RESETERR
     */
    (ScacFir, bit(34)) ? defaultMaskedError;

    /** SCACFIR[35]
     *  SCAC_LFIR_INTERNAL_SCOM_ERROR
     */
    (ScacFir, bit(35)) ? thresholdAndMask_self;

    /** SCACFIR[36]
     *  SCAC_LFIR_INTERNAL_SCOM_ERROR_CLONE
     */
    (ScacFir, bit(36)) ? thresholdAndMask_self;
};

################################################################################
#  NEST Chiplet MBIFIR
################################################################################
# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls

rule MbiFir
{
    CHECK_STOP:  MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & ~MBIFIR_ACT1;
    UNIT_CS:     MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & ~MBIFIR_ACT1;
    RECOVERABLE: MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 &  MBIFIR_ACT1;
};

group gMbiFir filter priority(  8, 9, 19, 20, 6, 0, # Channel failure
                               16, 5, 10 ),         # Recoverable
                     secondarybits(1,2,3,4,5,7,10,11,12,13,14,15,16,17,18,21,22,
                                   23,24,25,26)
{
    /** MBIFIR[0]
     *  MBIFIRQ_REPLAY_TIMEOUT
     */
    (MbiFir, bit(0)) ? replayTimeOutError;

    /** MBIFIR[1]
     *  MBIFIRQ_CHANNEL_FAIL
     */
    (MbiFir, bit(1)) ? defaultMaskedError;

    /** MBIFIR[2]
     *  MBIFIRQ_CRC_ERROR
     */
    (MbiFir, bit(2)) ? defaultMaskedError;

    /** MBIFIR[3]
     *  MBIFIRQ_FRAME_NOACK
     */
    (MbiFir, bit(3)) ? defaultMaskedError;

    /** MBIFIR[4]
     *  MBIFIRQ_SEQID_OUT_OF_ORDER
     */
    (MbiFir, bit(4)) ? defaultMaskedError;

    /** MBIFIR[5]
     *  MBIFIRQ_REPLAY_BUFFER_ECC_CE
     */
    (MbiFir, bit(5)) ? SelfMedThr5PerHour;

    /** MBIFIR[6]
     *  MBIFIRQ_REPLAY_BUFFER_ECC_UE
     */
    (MbiFir, bit(6)) ? SelfMedThr1UE;

    /** MBIFIR[7]
     *  MBIFIRQ_MBI_STATE_MACHINE_TIMEOUT
     */
    (MbiFir, bit(7)) ? defaultMaskedError;

    /** MBIFIR[8]
     *  MBIFIRQ_MBI_INTERNAL_CONTROL_PARITY_ERROR
     */
    (MbiFir, bit(8)) ? SelfMedThr1UE;

    /** MBIFIR[9]
     *  MBIFIRQ_MBI_DATA_FLOW_PARITY_ERROR
     */
    (MbiFir, bit(9)) ? SelfMedThr1UE;

    /** MBIFIR[10]
     *  MBIFIRQ_CRC_PERFORMANCE_DEGRADATION
     */
    (MbiFir, bit(10)) ? analyzeSpareBitAndThr;

    /** MBIFIR[11]
     *  MBIFIRQ_HOST_MC_GLOBAL_CHECKSTOP
     */
    (MbiFir, bit(11)) ? defaultMaskedError;

    /** MBIFIR[12]
     *  MBIFIRQ_HOST_MC_TRACESTOP
     */
    (MbiFir, bit(12)) ? defaultMaskedError;

    /** MBIFIR[13]
     *  MBIFIRQ_CHANNEL_INTERLOCK_FAIL
     */
    (MbiFir, bit(13)) ? defaultMaskedError;

    /** MBIFIR[14]
     *  MBIFIRQ_HOST_MC_LOCAL_CHECKSTOP
     */
    (MbiFir, bit(14)) ? defaultMaskedError;

    /** MBIFIR[15]
     *  MBIFIRQ_FRTL_CONTER_OVERFLOW
     */
    (MbiFir, bit(15)) ? defaultMaskedError;

    /** MBIFIR[16]
     *  MBIFIRQ_SCOM_REGISTER_PARITY_ERROR
     */
    (MbiFir, bit(16)) ? SelfMedThr1;

    /** MBIFIR[17]
     *  MBIFIRQ_IO_FAULT: IO to MBI
     */
    (MbiFir, bit(17)) ? defaultMaskedError;

    /** MBIFIR[18]
     *  MBIFIRQ_MULTIPLE_REPLAY
     */
    (MbiFir, bit(18)) ? defaultMaskedError;

    /** MBIFIR[19]
     *  MBIFIRQ_MBICFG_PARITY_SCOM_ERROR
     */
    (MbiFir, bit(19)) ? SelfMedThr1UE;

    /** MBIFIR[20]
     *  MBIFIRQ_BUFFER_OVERRUN_ERROR
     */
    (MbiFir, bit(20)) ? calloutDmiBusTh1UE;

    # This is for DD2 only
    /** MBIFIR[21]
     *  MBIFIRQ_WAT_ERROR
     */
    (MbiFir, bit(21)) ? defaultMaskedError;

    /** MBIFIR[22:24]
     *  Reserved
     */
    (MbiFir, bit(22|23|24)) ? defaultMaskedError;

    /** MBIFIR[25]
     *  MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE
     */
    (MbiFir, bit(25)) ? thresholdAndMask_self;

    /** MBIFIR[26]
     *  MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE_COPY
     */
    (MbiFir, bit(26)) ? thresholdAndMask_self;
};

################################################################################
#  NEST Chiplet MBSFIR
################################################################################
# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls
rule MbsFir
{
    CHECK_STOP:  MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & ~MBSFIR_ACT1;
    UNIT_CS:     MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & ~MBSFIR_ACT1;
    RECOVERABLE: MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 &  MBSFIR_ACT1;
};

group gMbsFir filter singlebit,
                     secondarybits(3,5,7,9,11,12,14,15,17,19,21,22,23,24,25,26,
                                   28,29,31,32,33,34)
{
    /** MBSFIR[0]
     *  MBS_FIR_REG_HOST_PROTOCOL_ERROR
     */
    (MbsFir, bit(0)) ? calloutDmiBusTh1UE;

    /** MBSFIR[1]
     *  MBS_FIR_REG_INT_PROTOCOL_ERROR
     */
    (MbsFir, bit(1)) ? SelfMedThr1UE;

    /** MBSFIR[2]
     *  MBS_FIR_REG_INVALID_ADDRESS_ERROR
     */
    (MbsFir, bit(2)) ? calloutDmiBusTh1;

    /** MBSFIR[3]
     *  MBS_FIR_REG_EXTERNAL_TIMEOUT
     */
    (MbsFir, bit(3)) ? callout2ndLvlMedThr1;

    /** MBSFIR[4]
     *  MBS_FIR_REG_INTERNAL_TIMEOUT
     */
    (MbsFir, bit(4)) ? internalTimeout;

    /** MBSFIR[3,4]
     *  MBS_FIR_REG_EXTERNAL_TIMEOUT
     */
    # NOTE: The signature will match the external timeout, but we will still
    #       call the internalTimeout plugin because there is extra processing
    #       done to handle parity errors and such.
    (MbsFir, bit(3,4)) ? internalTimeout;

    /** MBSFIR[5]
     *  MBS_FIR_REG_INT_BUFFER_CE
     */
    (MbsFir, bit(5)) ? SelfMedThr32PerDay;

    /** MBSFIR[6]
     *  MBS_FIR_REG_INT_BUFFER_UE
     */
    (MbsFir, bit(6)) ? SelfMedThr1UE;

    /** MBSFIR[7]
     *  MBS_FIR_REG_INT_BUFFER_SUE
     */
    (MbsFir, bit(7)) ? defaultMaskedError;

    /** MBSFIR[8]
     *  MBS_FIR_REG_INT_PARITY_ERROR
     */
    (MbsFir, bit(8)) ? SelfMedThr1UE;

    /** MBSFIR[9]
     *  MBS_FIR_REG_CACHE_SRW_CE
     */
    (MbsFir, bit(9)) ? clearSecMbsBitsAndLineDelete;

    /** MBSFIR[10]
     *  MBS_FIR_REG_CACHE_SRW_UE
     */
    (MbsFir, bit(10)) ? maskSecMbsBitsAndConnL4UE;

    /** MBSFIR[11]
     *  MBS_FIR_REG_CACHE_SRW_SUE
     */
    (MbsFir, bit(11)) ? defaultMaskedError;

    /** MBSFIR[12]
     *  MBS_FIR_REG_CACHE_CO_CE
     */
    (MbsFir, bit(12)) ? clearSecMbaCalBitsAndLineDelete;

    /** MBSFIR[13]
     *  MBS_FIR_REG_CACHE_CO_UE
     */
    (MbsFir, bit(13)) ? maskSecMbaCalBitsAndConnL4UE;

    /** MBSFIR[14]
     *  MBS_FIR_REG_CACHE_CO_SUE
     */
    (MbsFir, bit(14)) ? defaultMaskedError;

    /** MBSFIR[15]
     *  MBS_FIR_REG_DIR_CE
     */
    (MbsFir, bit(15)) ? L4CalloutMedThr32PerDay;

    /** MBSFIR[16]
     *  MBS_FIR_REG_DIR_UE
     */
    (MbsFir, bit(16)) ? L4CalloutMedThr1UE;

    /** MBSFIR[17]
     *  MBS_FIR_REG_DIR_MEMBER_DELETED
     */
    (MbsFir, bit(17)) ? defaultMaskedError;

    /** MBSFIR[18]
     *  MBS_FIR_REG_DIR_ALL_MEMBERS_DELETED
     */
    (MbsFir, bit(18)) ? L4CalloutMedThr1UE;

    /** MBSFIR[19]
     *  MBS_FIR_REG_LRU_ERROR
     */
    (MbsFir, bit(19)) ? L4CalloutMedThr32PerDay;

    /** MBSFIR[20]
     *  MBS_FIR_REG_EDRAM_ERROR
     */
    (MbsFir, bit(20)) ? L4CalloutMedThr1UE;

    /** MBSFIR[21]
     *  MBS_FIR_REG_EMERGENCY_THROTTLE_SET
     */
    (MbsFir, bit(21)) ? defaultMaskedError;

    /** MBSFIR[22]
     *  MBS_FIR_REG_HOST_INBAND_READ_ERROR
     */
    (MbsFir, bit(22)) ? defaultMaskedError;

    /** MBSFIR[23]
     *  MBS_FIR_REG_HOST_INBAND_WRITE_ERROR
     */
    (MbsFir, bit(23)) ? defaultMaskedError;

    /** MBSFIR[24]
     *  MBS_FIR_REG_OCC_INBAND_READ_ERROR
     */
    (MbsFir, bit(24)) ? defaultMaskedError;

    /** MBSFIR[25]
     *  MBS_FIR_REG_OCC_INBAND_WRITE_ERROR
     */
    (MbsFir, bit(25)) ? defaultMaskedError;

    /** MBSFIR[26]
     *  MBS_FIR_REG_SRB_BUFFER_CE
     */
    (MbsFir, bit(26)) ? thresholdAndMask_self;

    /** MBSFIR[27]
     *  MBS_FIR_REG_SRB_BUFFER_UE
     */
    (MbsFir, bit(27)) ? SelfMedThr1UE;

    /** MBSFIR[28]
     *  MBS_FIR_REG_SRB_BUFFER_SUE
     */
    (MbsFir, bit(28)) ? defaultMaskedError;

    /** MBSFIR[29]
     *  DD1: MBS_FIR_REG_INTERNAL_SCOM_ERROR
     */
    (MbsFir, bit(29)) ? thresholdAndMask_self; # DD1 action, masked for DD2+

    /** MBSFIR[30]
     *  MBS_FIR_REG_PROXIMAL_CE_UE
     */
    (MbsFir, bit(30)) ? mbsfirBit30;

    # This is for DD2 only
    /** MBSFIR[31]
     *  MBS_FIR_REG_SPARE_FIR31
     */
    (MbsFir, bit(31)) ? defaultMaskedError;

    # This is for DD2 only
    /** MBSFIR[32]
     *  MBS_FIR_REG_SPARE_FIR32
     */
    (MbsFir, bit(32)) ? defaultMaskedError;

    # This is for DD2 only
    /** MBSFIR[33]
     *  MBS_FIR_REG_INTERNAL_SCOM_ERROR
     */
    (MbsFir, bit(33)) ? thresholdAndMask_self;

    # This is for DD2 only
    /** MBSFIR[34]
     *  MBS_FIR_REG_INTERNAL_SCOM_ERROR_COPY
     */
    (MbsFir, bit(34)) ? thresholdAndMask_self;
};

################################################################################
#  NEST Chiplet MBSECCFIRs
################################################################################
# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls

rule Mba0_MbsEccFir
{
  CHECK_STOP:   MBSECCFIR_0      & ~MBSECCFIR_0_MASK &
               ~MBSECCFIR_0_ACT0 & ~MBSECCFIR_0_ACT1;
  UNIT_CS:      MBSECCFIR_0      & ~MBSECCFIR_0_MASK &
               ~MBSECCFIR_0_ACT0 & ~MBSECCFIR_0_ACT1;
  RECOVERABLE:  MBSECCFIR_0      & ~MBSECCFIR_0_MASK &
               ~MBSECCFIR_0_ACT0 &  MBSECCFIR_0_ACT1;
};

rule Mba1_MbsEccFir
{
  CHECK_STOP:   MBSECCFIR_1      & ~MBSECCFIR_1_MASK &
               ~MBSECCFIR_1_ACT0 & ~MBSECCFIR_1_ACT1;
  UNIT_CS:      MBSECCFIR_1      & ~MBSECCFIR_1_MASK &
               ~MBSECCFIR_1_ACT0 & ~MBSECCFIR_1_ACT1;
  RECOVERABLE:  MBSECCFIR_1      & ~MBSECCFIR_1_MASK &
               ~MBSECCFIR_1_ACT0 &  MBSECCFIR_1_ACT1;
};

group gMbsEccFir filter priority ( 19, 41 ),
                        secondarybits(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,
                                      17,18,20,21,22,23,24,25,26,27,28,29,30,31,
                                      32,33,34,35,36,37,38,39,40,41,42,43,44,45,
                                      48,50,51)
{
    /** MBSECCFIR_0[0]
     *  Memory chip mark on rank 0
     */
    (Mba0_MbsEccFir, bit(0)) ? analyzeFetchMpe0_0;

    /** MBSECCFIR_1[0]
     *  Memory chip mark on rank 0
     */
    (Mba1_MbsEccFir, bit(0)) ? analyzeFetchMpe1_0;

    /** MBSECCFIR_0[1]
     *  Memory chip mark on rank 1
     */
    (Mba0_MbsEccFir, bit(1)) ? analyzeFetchMpe0_1;

    /** MBSECCFIR_1[1]
     *  Memory chip mark on rank 1
     */
    (Mba1_MbsEccFir, bit(1)) ? analyzeFetchMpe1_1;

    /** MBSECCFIR_0[2]
     *  Memory chip mark on rank 2
     */
    (Mba0_MbsEccFir, bit(2)) ? analyzeFetchMpe0_2;

    /** MBSECCFIR_1[2]
     *  Memory chip mark on rank 2
     */
    (Mba1_MbsEccFir, bit(2)) ? analyzeFetchMpe1_2;

    /** MBSECCFIR_0[3]
     *  Memory chip mark on rank 3
     */
    (Mba0_MbsEccFir, bit(3)) ? analyzeFetchMpe0_3;

    /** MBSECCFIR_1[3]
     *  Memory chip mark on rank 3
     */
    (Mba1_MbsEccFir, bit(3)) ? analyzeFetchMpe1_3;

    /** MBSECCFIR_0[4]
     *  Memory chip mark on rank 4
     */
    (Mba0_MbsEccFir, bit(4)) ? analyzeFetchMpe0_4;

    /** MBSECCFIR_1[4]
     *  Memory chip mark on rank 4
     */
    (Mba1_MbsEccFir, bit(4)) ? analyzeFetchMpe1_4;

    /** MBSECCFIR_0[5]
     *  Memory chip mark on rank 5
     */
    (Mba0_MbsEccFir, bit(5)) ? analyzeFetchMpe0_5;

    /** MBSECCFIR_1[5]
     *  Memory chip mark on rank 5
     */
    (Mba1_MbsEccFir, bit(5)) ? analyzeFetchMpe1_5;

    /** MBSECCFIR_0[6]
     *  Memory chip mark on rank 6
     */
    (Mba0_MbsEccFir, bit(6)) ? analyzeFetchMpe0_6;

    /** MBSECCFIR_1[6]
     *  Memory chip mark on rank 6
     */
    (Mba1_MbsEccFir, bit(6)) ? analyzeFetchMpe1_6;

    /** MBSECCFIR_0[7]
     *  Memory chip mark on rank 7
     */
    (Mba0_MbsEccFir, bit(7)) ? analyzeFetchMpe0_7;

    /** MBSECCFIR_1[7]
     *  Memory chip mark on rank 7
     */
    (Mba1_MbsEccFir, bit(7)) ? analyzeFetchMpe1_7;

    /** MBSECCFIR_0[8:15]
     *  Reserved
     */
    (Mba0_MbsEccFir, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError;

    /** MBSECCFIR_1[8:15]
     *  Reserved
     */
    (Mba1_MbsEccFir, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError;

    /** MBSECCFIR_0[16]
     *  Memory NCE
     */
    (Mba0_MbsEccFir, bit(16)) ? analyzeFetchNce0;

    /** MBSECCFIR_1[16]
     *  Memory NCE
     */
    (Mba1_MbsEccFir, bit(16)) ? analyzeFetchNce1;

    /** MBSECCFIR_0[17]
     *  Memory RCE
     */
    (Mba0_MbsEccFir, bit(17)) ? analyzeFetchRce0;

    /** MBSECCFIR_1[17]
     *  Memory RCE
     */
    (Mba1_MbsEccFir, bit(17)) ? analyzeFetchRce1;

    /** MBSECCFIR_0[18]
     *  Memory SUE
     */
    (Mba0_MbsEccFir, bit(18)) ? defaultMaskedError;

    /** MBSECCFIR_1[18]
     *  Memory SUE
     */
    (Mba1_MbsEccFir, bit(18)) ? defaultMaskedError;

    /** MBSECCFIR_0[19]
     *  Memory UE
     */
    (Mba0_MbsEccFir, bit(19)) ? mba0MemoryUe;

    /** MBSECCFIR_1[19]
     *  Memory UE
     */
    (Mba1_MbsEccFir, bit(19)) ? mba1MemoryUe;

    /** MBSECCFIR_0[20:27]
     *  Maintenance chip mark
     */
    (Mba0_MbsEccFir, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError;

    /** MBSECCFIR_1[20:27]
     *  Maintenance chip mark
     */
    (Mba1_MbsEccFir, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError;

    /** MBSECCFIR_0[28:35]
     *  Reserved
     */
    (Mba0_MbsEccFir, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError;

    /** MBSECCFIR_1[28:35]
     *  Reserved
     */
    (Mba1_MbsEccFir, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError;

    /** MBSECCFIR_0[36]
     *  Maintenance NCE
     */
    (Mba0_MbsEccFir, bit(36)) ? defaultMaskedError;

    /** MBSECCFIR_1[36]
     *  Maintenance NCE
     */
    (Mba1_MbsEccFir, bit(36)) ? defaultMaskedError;

    /** MBSECCFIR_0[37]
     *  Maintenance SCE
     */
    (Mba0_MbsEccFir, bit(37)) ? defaultMaskedError;

    /** MBSECCFIR_1[37]
     *  Maintenance SCE
     */
    (Mba1_MbsEccFir, bit(37)) ? defaultMaskedError;

    /** MBSECCFIR_0[38]
     *  Maintenance MCE
     */
    (Mba0_MbsEccFir, bit(38)) ? defaultMaskedError;

    /** MBSECCFIR_1[38]
     *  Maintenance MCE
     */
    (Mba1_MbsEccFir, bit(38)) ? defaultMaskedError;

    /** MBSECCFIR_0[39]
     *  Maintenance RCE
     */
    (Mba0_MbsEccFir, bit(39)) ? defaultMaskedError;

    /** MBSECCFIR_1[39]
     *  Maintenance RCE
     */
    (Mba1_MbsEccFir, bit(39)) ? defaultMaskedError;

    /** MBSECCFIR_0[40]
     *  Maintenance SUE
     */
    (Mba0_MbsEccFir, bit(40)) ? defaultMaskedError;

    /** MBSECCFIR_1[40]
     *  Maintenance SUE
     */
    (Mba1_MbsEccFir, bit(40)) ? defaultMaskedError;

    /** MBSECCFIR_0[41]
     *  Maintenance UE
     */
    (Mba0_MbsEccFir, bit(41)) ? defaultMaskedError;

    /** MBSECCFIR_1[41]
     *  Maintenance UE
     */
    (Mba1_MbsEccFir, bit(41)) ? defaultMaskedError;

    /** MBSECCFIR_0[42]
     *  MBECCFIR_MPE_DURING_USE_MAINTENANCE_MARK_MODE
     */
    (Mba0_MbsEccFir, bit(42)) ? defaultMaskedError;

    /** MBSECCFIR_1[42]
     *  MBECCFIR_MPE_DURING_USE_MAINTENANCE_MARK_MODE
     */
    (Mba1_MbsEccFir, bit(42)) ? defaultMaskedError;

    /** MBSECCFIR_0[43]
     *  MBECCFIR_PREFETCH_MEMORY_UE
     */
    (Mba0_MbsEccFir, bit(43)) ? analyzeFetchPreUe0;

    /** MBSECCFIR_1[43]
     *  MBECCFIR_PREFETCH_MEMORY_UE
     */
    (Mba1_MbsEccFir, bit(43)) ? analyzeFetchPreUe1;

    /** MBSECCFIR_0[44]
     *  MBECCFIR_MEMORY_RCD_PARITY_ERROR
     */
    (Mba0_MbsEccFir, bit(44)) ? defaultMaskedError;

    /** MBSECCFIR_1[44]
     *  MBECCFIR_MEMORY_RCD_PARITY_ERROR
     */
    (Mba1_MbsEccFir, bit(44)) ? defaultMaskedError;

    /** MBSECCFIR_0[45]
     *  MBECCFIR_MAINTENANCE_RCD_PARITY_ERROR
     */
    (Mba0_MbsEccFir, bit(45)) ? defaultMaskedError;

    /** MBSECCFIR_1[45]
     *  MBECCFIR_MAINTENANCE_RCD_PARITY_ERROR
     */
    (Mba1_MbsEccFir, bit(45)) ? defaultMaskedError;

    /** MBSECCFIR_0[46]
     *  MBECCFIR_RECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR
     */
    (Mba0_MbsEccFir, bit(46)) ? MBA0CalloutMedThr1;

    /** MBSECCFIR_1[46]
     *  MBECCFIR_RECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR
     */
    (Mba1_MbsEccFir, bit(46)) ? MBA1CalloutMedThr1;

    /** MBSECCFIR_0[47]
     *  MBECCFIR_UNRECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR
     */
    (Mba0_MbsEccFir, bit(47)) ? MBA0CalloutMedThr1UE;

    /** MBSECCFIR_1[47]
     *  MBECCFIR_UNRECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR
     */
    (Mba1_MbsEccFir, bit(47)) ? MBA1CalloutMedThr1UE;

    /** MBSECCFIR_0[48]
     *  MBECCFIR_MASKABLE_CONFIGURATION_REGISTER_PARITY_ERROR
     */
    (Mba0_MbsEccFir, bit(48)) ? thresholdAndMask_mba0;

    /** MBSECCFIR_1[48]
     *  MBECCFIR_MASKABLE_CONFIGURATION_REGISTER_PARITY_ERROR
     */
    (Mba1_MbsEccFir, bit(48)) ? thresholdAndMask_mba1;

    /** MBSECCFIR_0[49]
     *  MBECCFIR_ECC_DATAPATH_PARITY_ERROR
     */
    (Mba0_MbsEccFir, bit(49)) ? MBA0CalloutMedThr1UE;

    /** MBSECCFIR_1[49]
     *  MBECCFIR_ECC_DATAPATH_PARITY_ERROR
     */
    (Mba1_MbsEccFir, bit(49)) ? MBA1CalloutMedThr1UE;

    /** MBSECCFIR_0[50]
     *  MBECCFIR_INTERNAL_SCOM_ERROR
     */
    (Mba0_MbsEccFir, bit(50)) ? thresholdAndMask_mba0;

    /** MBSECCFIR_1[50]
     *  MBECCFIR_INTERNAL_SCOM_ERROR
     */
    (Mba1_MbsEccFir, bit(50)) ? thresholdAndMask_mba1;

    /** MBSECCFIR_0[51]
     *  MBECCFIR_INTERNAL_SCOM_ERROR_COPY
     */
    (Mba0_MbsEccFir, bit(51)) ? thresholdAndMask_mba0;

    /** MBSECCFIR_1[51]
     *  MBECCFIR_INTERNAL_SCOM_ERROR_COPY
     */
    (Mba1_MbsEccFir, bit(51)) ? thresholdAndMask_mba1;
};

################################################################################
#  NEST Chiplet MCBISTFIRs
################################################################################
# RAS spreadsheet: p8dd1_mss_FFDC_37_ reviewd.xls

rule Mba0_McbistFir
{
  CHECK_STOP:   MCBISTFIR_0      & ~MCBISTFIR_0_MASK &
               ~MCBISTFIR_0_ACT0 & ~MCBISTFIR_0_ACT1;
  UNIT_CS:      MCBISTFIR_0      & ~MCBISTFIR_0_MASK &
               ~MCBISTFIR_0_ACT0 & ~MCBISTFIR_0_ACT1;
  RECOVERABLE:  MCBISTFIR_0      & ~MCBISTFIR_0_MASK &
               ~MCBISTFIR_0_ACT0 &  MCBISTFIR_0_ACT1;
};

rule Mba1_McbistFir
{
  CHECK_STOP:   MCBISTFIR_1      & ~MCBISTFIR_1_MASK &
               ~MCBISTFIR_1_ACT0 & ~MCBISTFIR_1_ACT1;
  UNIT_CS:      MCBISTFIR_1      & ~MCBISTFIR_1_MASK &
               ~MCBISTFIR_1_ACT0 & ~MCBISTFIR_1_ACT1;
  RECOVERABLE:  MCBISTFIR_1      & ~MCBISTFIR_1_MASK &
               ~MCBISTFIR_1_ACT0 &  MCBISTFIR_1_ACT1;
};

group gMcbistFir filter singlebit,
                        secondarybits(2,3,4,5,6,7,8,9,10,11,12,13,14,15,16)
{
    /** MCBISTFIR_0[0]
     *  MBSFIRQ_SCOM_PAR_ERRORS
     */
    (Mba0_McbistFir, bit(0)) ? MBA0CalloutMedThr1;

    /** MCBISTFIR_1[0]
     *  MBSFIRQ_SCOM_PAR_ERRORS
     */
    (Mba1_McbistFir, bit(0)) ? MBA1CalloutMedThr1;

    /** MCBISTFIR_0[1]
     *  MBSFIRQ_MBX_PAR_ERRORS
     */
    (Mba0_McbistFir, bit(1)) ? MBA0CalloutMedThr1;

    /** MCBISTFIR_1[1]
     *  MBSFIRQ_MBX_PAR_ERRORS
     */
    (Mba1_McbistFir, bit(1)) ? MBA1CalloutMedThr1;

    # This is for DD2 only
    /** MCBISTFIR_0[2]
     *  MBSFIRQ_DRAM_EVENT_BIT0
     */
    (Mba0_McbistFir, bit(2)) ? defaultMaskedError;

    # This is for DD2 only
    /** MCBISTFIR_1[2]
     *  MBSFIRQ_DRAM_EVENT_BIT0
     */
    (Mba1_McbistFir, bit(2)) ? defaultMaskedError;

    # This is for DD2 only
    /** MCBISTFIR_0[3]
     *  MBSFIRQ_DRAM_EVENT_BIT1
     */
    (Mba0_McbistFir, bit(3)) ? defaultMaskedError;

    # This is for DD2 only
    /** MCBISTFIR_1[3]
     *  MBSFIRQ_DRAM_EVENT_BIT1
     */
    (Mba1_McbistFir, bit(3)) ? defaultMaskedError;

    /** MCBISTFIR_0[4:14]
     *  Reserved
     */
    (Mba0_McbistFir, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError;

    /** MCBISTFIR_1[4:14]
     *  Reserved
     */
    (Mba1_McbistFir, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError;

    /** MCBISTFIR_0[15]
     *  MBSFIRQ_INTERNAL_SCOM_ERROR
     */
    (Mba0_McbistFir, bit(15)) ? thresholdAndMask_mba0;

    /** MCBISTFIR_1[15]
     *  MBSFIRQ_INTERNAL_SCOM_ERROR
     */
    (Mba1_McbistFir, bit(15)) ? thresholdAndMask_mba1;

    /** MCBISTFIR_0[16]
     *  MBSFIRQ_INTERNAL_SCOM_ERROR_CLONE
     */
    (Mba0_McbistFir, bit(16)) ? thresholdAndMask_mba0;

    /** MCBISTFIR_1[16]
     *  MBSFIRQ_INTERNAL_SCOM_ERROR_CLONE
     */
    (Mba1_McbistFir, bit(16)) ? thresholdAndMask_mba1;
};

################################################################################
#  NEST Chiplet MBSSECUREFIR
################################################################################

rule MbsSecureFir
{
  # NOTE: This secure FIR will only report checkstop attentions.
  CHECK_STOP: MBSSECUREFIR;
  UNIT_CS:    MBSSECUREFIR;
};

group gMbsSecureFir filter singlebit
{
    /** MBSSECUREFIR[0]
     *  MBSSIRQ_INVALID_MBSXCR_ACCESS
     */
    (MbsSecureFir, bit(0)) ? secureFirCallout;

    /** MBSSECUREFIR[1]
     *  MBSSIRQ_INVALID_MBAXCR01_ACCESS
     */
    (MbsSecureFir, bit(1)) ? secureFirCallout;

    /** MBSSECUREFIR[2]
     *  MBSSIRQ_INVALID_MBAXCR23_ACCESS
     */
    (MbsSecureFir, bit(2)) ? secureFirCallout;

    /** MBSSECUREFIR[3]
     *  MBSSIRQ_INVALID_MBAXCRMS_ACCRESS
     */
    (MbsSecureFir, bit(3)) ? secureFirCallout;

    /** MBSSECUREFIR[4]
     *  MBSSIRQ_SPARE (Spare)
     */
    (MbsSecureFir, bit(4)) ? secureFirCallout;

    /** MBSSECUREFIR[5]
     *  MBSSIRQ_INVALID_SIR_MASK_OR_ACTION_REGISTER_ACCESS
     */
    (MbsSecureFir, bit(5)) ? secureFirCallout;
};

################################################################################
# Actions specific to NEST chiplet
################################################################################

/** Callout the connected MBA 0 */
actionclass calloutMba0 { callout(connected(TYPE_MBA, 0), MRU_MED); };

/** Callout the connected MBA 1 */
actionclass calloutMba1 { callout(connected(TYPE_MBA, 1), MRU_MED); };

/** Callout the connected L4 */
actionclass calloutL4 { callout(connected(TYPE_L4), MRU_MED); };

/** Callout the DMI bus */
actionclass calloutDmiBus
{
    calloutSelfMedA;
    callout(connected(TYPE_MCS), MRU_MEDA);
    funccall("calloutInterface_dmi");
};

/** Handles MCS Chnl XSTOP if present otherwise handles MBIFIR Replay Timeout */
actionclass replayTimeOutError
{
    try( funccall("handleMcsChnlCs"), clearSecMbsBitsCalloutDmiBusTh1UE );
};

/** Handles MBACAL parity err if present, else handles MBS Internal Timeout */
actionclass internalTimeout
{
    threshold1;
    funccall("internalTimeout"); # must be called last so rc is passed on
};

/** Handles MBACAL parity err if present, else handles MBA0 MBSECC Memory UE */
actionclass mba0MemoryUe
{
    try ( funccall("handleSingleMbaCalParityErr0"), analyzeFetchUe0 );
};

/** Handles MBACAL parity err if present, else handles MBA1 MBSECC Memory UE */
actionclass mba1MemoryUe
{
    try ( funccall("handleSingleMbaCalParityErr1"), analyzeFetchUe1 );
};

/** Clear MBS SecondaryBits and calloutDmiBusTh1UE */
actionclass clearSecMbsBitsCalloutDmiBusTh1UE
{
    funccall("ClearMbsSecondaryBits");
    calloutDmiBusTh1UE;
};

/** Callout the DMI bus, threshold 1 */
actionclass calloutDmiBusTh1UE
{
    calloutDmiBusTh1;
    SUEGenerationPoint;
};

/** Callout the DMI bus, threshold 1 */
actionclass calloutDmiBusTh1 { calloutDmiBus; threshold1; };

/** Callout the DMI bus, threshold 2 per day */
actionclass calloutDmiBusTh2pday { calloutDmiBus; threshold2pday; };

/** If no sparebit is set, execute calloutDmiBusTh2pday*/
actionclass analyzeSpareBitAndThr
{
    try( funccall("checkSpareBit"), calloutDmiBusTh2pday );
};

/** Lane Repair: spare deployed */
actionclass spareDeployed
{ calloutDmiBus; funccall("spareDeployed"); };

/** Lane Repair: max spares exceeded */
actionclass maxSparesExceeded
{ calloutDmiBusTh1; funccall("maxSparesExceeded"); };

/** Analyze a fetch MPE on MBA0 rank 0 */
actionclass analyzeFetchMpe0_0 { funccall("AnalyzeFetchMpe0_0"); };

/** Analyze a fetch MPE on MBA1 rank 0 */
actionclass analyzeFetchMpe1_0 { funccall("AnalyzeFetchMpe1_0"); };

/** Analyze a fetch MPE on MBA0 rank 1 */
actionclass analyzeFetchMpe0_1 { funccall("AnalyzeFetchMpe0_1"); };

/** Analyze a fetch MPE on MBA1 rank 1 */
actionclass analyzeFetchMpe1_1 { funccall("AnalyzeFetchMpe1_1"); };

/** Analyze a fetch MPE on MBA0 rank 2 */
actionclass analyzeFetchMpe0_2 { funccall("AnalyzeFetchMpe0_2"); };

/** Analyze a fetch MPE on MBA1 rank 2 */
actionclass analyzeFetchMpe1_2 { funccall("AnalyzeFetchMpe1_2"); };

/** Analyze a fetch MPE on MBA0 rank 3 */
actionclass analyzeFetchMpe0_3 { funccall("AnalyzeFetchMpe0_3"); };

/** Analyze a fetch MPE on MBA1 rank 3 */
actionclass analyzeFetchMpe1_3 { funccall("AnalyzeFetchMpe1_3"); };

/** Analyze a fetch MPE on MBA0 rank 4 */
actionclass analyzeFetchMpe0_4 { funccall("AnalyzeFetchMpe0_4"); };

/** Analyze a fetch MPE on MBA1 rank 4 */
actionclass analyzeFetchMpe1_4 { funccall("AnalyzeFetchMpe1_4"); };

/** Analyze a fetch MPE on MBA0 rank 5 */
actionclass analyzeFetchMpe0_5 { funccall("AnalyzeFetchMpe0_5"); };

/** Analyze a fetch MPE on MBA1 rank 5 */
actionclass analyzeFetchMpe1_5 { funccall("AnalyzeFetchMpe1_5"); };

/** Analyze a fetch MPE on MBA0 rank 6 */
actionclass analyzeFetchMpe0_6 { funccall("AnalyzeFetchMpe0_6"); };

/** Analyze a fetch MPE on MBA1 rank 6 */
actionclass analyzeFetchMpe1_6 { funccall("AnalyzeFetchMpe1_6"); };

/** Analyze a fetch MPE on MBA0 rank 7 */
actionclass analyzeFetchMpe0_7 { funccall("AnalyzeFetchMpe0_7"); };

/** Analyze a fetch MPE on MBA1 rank 7 */
actionclass analyzeFetchMpe1_7 { funccall("AnalyzeFetchMpe1_7"); };

/** Analyze a fetch NCE on MBA0 */
actionclass analyzeFetchNce0 { funccall("AnalyzeFetchNce0"); };

/** Analyze a fetch NCE on MBA1 */
actionclass analyzeFetchNce1 { funccall("AnalyzeFetchNce1"); };

/** Analyze a fetch RCE on MBA0 */
actionclass analyzeFetchRce0 { funccall("AnalyzeFetchRce0"); };

/** Analyze a fetch RCE on MBA1 */
actionclass analyzeFetchRce1 { funccall("AnalyzeFetchRce1"); };

/** Analyze a PreFetch Ue on MBA0 */
actionclass analyzeFetchPreUe0 { funccall("AnalyzeFetchPreUe0"); };

/** Analyze a PreFetch Ue on MBA1 */
actionclass analyzeFetchPreUe1 { funccall("AnalyzeFetchPreUe1"); };

/** Analyze a fetch UE on MBA0 */
actionclass analyzeFetchUe0
{
    funccall("AnalyzeFetchUe0");
    threshold( field(33 / 30 min ) );
    SUEGenerationPoint;
};

/** Analyze a fetch UE on MBA1 */
actionclass analyzeFetchUe1
{
    funccall("AnalyzeFetchUe1");
    threshold( field(33 / 30 min ) );
    SUEGenerationPoint;
};

/** Clear MBS SecondaryBits and Line Delete*/
actionclass clearSecMbsBitsAndLineDelete
{
    calloutL4;
    threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_CEN_L4_CACHE_CES));
    funccall("CaptureL4CacheErr");
    funccall("ClearServiceCallFlag");
    funccall("ClearMbsSecondaryBits");
};

/** Clear MBACAL SecondaryBits and Line Delete*/
actionclass clearSecMbaCalBitsAndLineDelete
{
    calloutL4;
    threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_CEN_L4_CACHE_CES));
    funccall("CaptureL4CacheErr");
    funccall("ClearServiceCallFlag");
    funccall("ClearMbaCalSecondaryBits");
};

/** Mask MBACAL SecondaryBits and callout Connected L4*/
actionclass maskSecMbaCalBitsAndConnL4UE
{
    calloutL4;
    threshold1;
    funccall("CaptureL4CacheErr");
    funccall("MaskMbaCalSecondaryBits");
    SUEGenerationPoint;
};

/** Mask MBS SecondaryBits and callout Connected L4*/
actionclass maskSecMbsBitsAndConnL4UE
{
    calloutL4;
    threshold1;
    funccall("CaptureL4CacheErr");
    funccall("MaskMbsSecondaryBits");
    SUEGenerationPoint;
};

/** Callout MBA0 with "Threshold and Mask" policy. */
actionclass thresholdAndMask_mba0 { calloutMba0; thresholdAndMask; };

/** Callout MBA1 with "Threshold and Mask" policy. */
actionclass thresholdAndMask_mba1 { calloutMba1; thresholdAndMask; };

actionclass L4CalloutMedThr32PerDay
{
    calloutL4;
    threshold32pday;
};

actionclass L4CalloutMedThr1UE
{
    calloutL4;
    threshold1;
    SUEGenerationPoint;
};

actionclass MBA0CalloutMedThr1
{
    calloutMba0;
    threshold1;
};

actionclass MBA1CalloutMedThr1
{
    calloutMba1;
    threshold1;
};

actionclass MBA0CalloutMedThr1UE
{
    MBA0CalloutMedThr1;
    SUEGenerationPoint;
};

actionclass MBA1CalloutMedThr1UE
{
    MBA1CalloutMedThr1;
    SUEGenerationPoint;
};

/** The plugin checks if the membuf is at DD1.
    If DD1, then callout thresholdAndMask_self and change signature
    to DD1: MBS_FIR_REG_INTERNAL_SCOM_ERROR_COPY */
actionclass mbsfirBit30
{
    threshold32pday;
    try( funccall("mbsfirBit30_dd1"), L4CalloutMedThr1UE);
};

/** Callouts specific to MBSSECUREFIR attentions. */
actionclass secureFirCallout
{
    callout2ndLvlMed;
    calloutSelfLow;
    threshold1;
};