# IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # # $Source: src/usr/diag/prdf/common/plat/pegasus/Mcs.rule $ # # OpenPOWER HostBoot Project # # Contributors Listed Below - COPYRIGHT 2012,2016 # [+] International Business Machines Corp. # # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or # implied. See the License for the specific language governing # permissions and limitations under the License. # # IBM_PROLOG_END_TAG ################################################################################ # # Scope: # Registers and actions for the following chiplets: # Note that only addresses for MC0/MCS0 will be used. # # Chiplet Register Addresses Description # ======= ======================= ============================================ # MCS 0x02011800 - 0x0201187F MC0/MCS0 # MCS 0x02011880 - 0x020118FF MC0/MCS1 # MCS 0x02011900 - 0x0201197F MC1/MCS0 # MCS 0x02011980 - 0x020119FF MC1/MCS1 # MCS 0x02011A00 - 0x02011A3E DMI0 - DMI3 # MCS 0x02011C00 - 0x02011C7F MC2/MCS0 # MCS 0x02011C80 - 0x02011CFF MC2/MCS1 # MCS 0x02011D00 - 0x02011D7F MC3/MCS0 # MCS 0x02011D80 - 0x02011DFF MC3/MCS1 # MCS 0x02011E00 - 0x02011E3E DMI4 - DMI7 # ################################################################################ chip Mcs { name "Power8 MCS Chiplet"; targettype TYPE_MCS; sigoff 0x8000; dump DUMP_CONTENT_HW; scomlen 64; .include "prdfP8McsExtraSig.H"; ############################################################################# # # # ###### # # # # ###### #### ### #### ##### ###### ##### #### # # # # # # # # # # # # # # # # ###### ##### # # #### # ##### # # #### # # # # # # ### # # # # ##### # # # # # # # # # # # # # # # # # # # # # ###### #### ### #### # ###### # # #### # # # ############################################################################# ############################################################################ # PB Chiplet MCIFIR ############################################################################ register MCIFIR { name "MC0.MCS0.RIGHT.MCI.SCOMFIR.MCIFIRQ"; scomaddr 0x02011840; reset (&, 0x02011841); mask (|, 0x02011845); capture group default; capture group FirRegs; }; register MCIFIR_AND { name "MC0.MCS0.RIGHT.MCI.SCOMFIR.MCIFIRQ AND"; scomaddr 0x02011841; capture group never; access write_only; }; register MCIFIR_MASK { name "MC0.MCS0.RIGHT.MCI.SCOMFIR.MCIFIRMASK"; scomaddr 0x02011843; capture group default; capture group FirRegs; }; register MCIFIR_ACT0 { name "MC0.MCS0.RIGHT.MCI.SCOMFIR.MCIFIRACT0"; scomaddr 0x02011846; capture type secondary; capture group default; capture group FirRegs; capture req nonzero("MCIFIR"); }; register MCIFIR_ACT1 { name "MC0.MCS0.RIGHT.MCI.SCOMFIR.MCIFIRACT1"; scomaddr 0x02011847; capture type secondary; capture group default; capture group FirRegs; capture req nonzero("MCIFIR"); }; register MCIFIR_WOF { name "MC0.MCS0.RIGHT.MCI.SCOMFIR.MCIFIRWOF"; scomaddr 0x02011848; capture type secondary; capture group default; capture group FirRegs; capture req nonzero("MCIFIR"); }; ############################################################################ # Error Report Registers ############################################################################ register MCERPT0 { name "MC0.MCS0.LEFT.LEFT.MCERPT0"; scomaddr 0x0201181E; capture group default; capture group CerrRegs; }; register MCIERPT0 { name "MC0.MCS0.RIGHT.MCI.MCIERPT0"; scomaddr 0x0201184E; capture group default; capture group CerrRegs; }; ############################################################################ # Primary Memory Configuration Register ############################################################################ register MCFGP { name "MC0.MCS0.LEFT.LEFT.MCFGPQ"; scomaddr 0x02011800; capture group default; }; ############################################################################ # MCS Hardware Force Mirror Read SUE ############################################################################ register MCHWFM { name "MC0.MCS0.LEFT.LEFT.MCHWFMQ"; scomaddr 0x0201181C; capture group MirrorRegs; # Only valid on even MCSs of the mirror. # Will have to capture manually. }; }; ############################################################################## # # # #### # # # # # # # # ##### ### # # # ## ##### ### ### # # ### # # # # # # # # # # # # # # # # # # ## # # # # #### # # # #### ### # ####### # # # # # # # # ### # # # # # # # # # # # # # # # # # # # ## # # # # # ### #### ##### ### # # # ## # ### ### # # ### # # # ############################################################################## ################################################################################ # PB Chiplet MCIFIR # Reviewed p8dd1_mss_FFDC_72.xls on 01/16/14 ################################################################################ rule MciFir { CHECK_STOP: MCIFIR & ~MCIFIR_MASK & ~MCIFIR_ACT0 & ~MCIFIR_ACT1; RECOVERABLE: MCIFIR & ~MCIFIR_MASK & ~MCIFIR_ACT0 & MCIFIR_ACT1; SPECIAL: MCIFIR & ~MCIFIR_MASK & MCIFIR_ACT0 & ~MCIFIR_ACT1; # All of the Centaur CS (channel fail) bits set as recoverable. UNIT_CS: MCIFIR & ~MCIFIR_MASK & ~MCIFIR_ACT0 & MCIFIR_ACT1; }; group gMciFir attntype CHECK_STOP, RECOVERABLE, SPECIAL, UNIT_CS filter priority( 8, 9, 22, 23, 6, 0, 40, # Channel failure 20, 5, 10 ), # Recoverable secondarybits(1,2,3,4,5,7,10,11,12,13,14,15,16,17,18,19,20,21,24, 31,32,34,35,37,41,42,43,44,45,47,50,51,52,53) { /** MCIFIR[0] * MCIFIRQ_REPLAY_TIMEOUT */ (MciFir, bit(0)) ? clearSecMbsBitsCalloutDmiBusTh1; /** MCIFIR[1] * MCIFIRQ_CHANNEL_FAIL */ (MciFir, bit(1)) ? defaultMaskedError; /** MCIFIR[2] * MCIFIRQ_CRC_ERROR */ (MciFir, bit(2)) ? defaultMaskedError; /** MCIFIR[3] * MCIFIRQ_FRAME_NOACK */ (MciFir, bit(3)) ? defaultMaskedError; /** MCIFIR[4] * MCIFIRQ_SEQID_OUT_OF_ORDER */ (MciFir, bit(4)) ? defaultMaskedError; /** MCIFIR[5] * MCIFIRQ_REPLAY_BUFFER_ECC_CE */ (MciFir, bit(5)) ? SelfHighThr5PerHour; /** MCIFIR[6] * MCIFIRQ_REPLAY_BUFFER_ECC_UE */ (MciFir, bit(6)) ? SelfHighThr1; /** MCIFIR[7] * MCIFIRQ_MCI_CHINIT_STATE_MACHINE_TIMEOUT */ (MciFir, bit(7)) ? defaultMaskedError; /** MCIFIR[8] * MCIFIRQ_MCI_INTERNAL_CONTROL_PARITY_ERROR */ (MciFir, bit(8)) ? SelfHighThr1; /** MCIFIR[9] * MCIFIRQ_MCI_DATA_FLOW_PARITY_ERROR */ (MciFir, bit(9)) ? SelfHighThr1; /** MCIFIR[10] * MCIFIRQ_CRC_PERFORMANCE_DEGRADATION */ (MciFir, bit(10)) ? analyzeSpareBitAndThr; /** MCIFIR[11] * MCIFIRQ_CHANNEL_INTERLOCK_FAIL */ (MciFir, bit(11)) ? defaultMaskedError; /** MCIFIR[12] * MCIFIRQ_CENTAUR_CHECKSTOP */ # NOTE: This bit will be set to host_attn and only monitored by HostATTN # during Hostboot. (MciFir, bit(12)) ? defaultMaskedError; /** MCIFIR[13] * MCIFIRQ_CENTAUR_TRACESTOP */ (MciFir, bit(13)) ? defaultMaskedError; /** MCIFIR[14] * MCIFIRQ_FPGA_INTERRUPT */ (MciFir, bit(14)) ? defaultMaskedError; /** MCIFIR[15] * MCIFIRQ_CENTAUR_RECOVERABLE_ERROR */ # NOTE: This bit will be set to host_attn and only monitored by HostATTN # during Hostboot. (MciFir, bit(15)) ? defaultMaskedError; /** MCIFIR[16] * MCIFIRQ_CENTAUR_SPECIAL_ATTENTION */ # NOTE: This bit will be set to host_attn and only monitored by HostATTN # during Hostboot. (MciFir, bit(16)) ? defaultMaskedError; /** MCIFIR[17] * MCIFIRQ_CENTAUR_MAINTENANCE_COMPLETE */ # NOTE: This bit will be set to host_attn and only monitored by HostATTN # during Hostboot. (MciFir, bit(17)) ? defaultMaskedError; /** MCIFIR[18] * MCIFIRQ_CENTAUR_INBAND_PIB_ERROR */ (MciFir, bit(18)) ? defaultMaskedError; /** MCIFIR[19] * FRTL Conter Overflow */ (MciFir, bit(19)) ? defaultMaskedError; /** MCIFIR[20] * SCOM Register parity Error */ (MciFir, bit(20)) ? SelfHighThr1; /** MCIFIR[21] * MCIFIRQ_MULTIPLE_REPLAY */ (MciFir, bit(21)) ? defaultMaskedError; /** MCIFIR[22] * MCIFIRQ_MCICFG_PARITY_SCOM_ERROR */ (MciFir, bit(22)) ? SelfMedThr1; /** MCIFIR[23] * MCIFIRQ_REPLAY_BUFFER_OVERRUN */ (MciFir, bit(23)) ? calloutDmiBusTh1; /** MCIFIR[24] * MCIFIRQ_MCS_RECOVERABLE_ERROR */ (MciFir, bit(24)) ? SelfHighThr1; /** MCIFIR[25] * MCIFIRQ_MCS_INTERNAL_NONRECOVERABLE_ERROR */ (MciFir, bit(25)) ? SelfHighThr1; /** MCIFIR[26] * MCIFIRQ_POWERBUS_PROTOCOL_ERROR */ (MciFir, bit(26)) ? callout2ndLvlDumpSw; /** MCIFIR[27] * MCIFIRQ_MCS_COMMAND_LIST_TIMEOUT_DUE_TO_POWERBUS */ (MciFir, bit(27)) ? calloutDmiBusAndLvl2Th1; /** MCIFIR[28] * MCIFIRQ_MULTIPLE_RCMD_OR_CRESP_ACTIVE */ (MciFir, bit(28)) ? SelfLowLevel2MedThr1; /** MCIFIR[29] * MCIFIRQ_INBAND_BAR_HIT_WITH_INCORRECT_TTYPE */ (MciFir, bit(29)) ? SelfLowLevel2MedThr1; /** MCIFIR[30] * MCIFIRQ_MULTIPLE_BAR_HIT */ (MciFir, bit(30)) ? SelfLowLevel2MedThr1; /** MCIFIR[31] * MCIFIRQ_CHANNEL_FAIL_SIGNAL_ACTIVE */ # NOTE: PRD checks this bit anytime it is called to analyze the MCS. It is # intended to indicate that another bit in this FIR signaled a channel # failure/checkstop. It should always be masked. (MciFir, bit(31)) ? defaultMaskedError; /** MCIFIR[32] * Mirror action occurred */ (MciFir, bit(32)) ? handleMirrorAction; /** MCIFIR[33] * MCIFIRQ_NONFOREIGN_ACCESS_TO_FOREIGN_BAR */ (MciFir, bit(33)) ? callout2ndLvlDumpSw; /** MCIFIR[34] * MCIFIRQ_CENTAUR_SYNC_COMMAND_DETECTED */ (MciFir, bit(34)) ? defaultMaskedError; /** MCIFIR[35] * MCIFIRQ_POWERBUS_WRITE_DATA_BUFFER_CE */ (MciFir, bit(35)) ? calloutProcHighThr5PerHr; /** MCIFIR[36] * MCIFIRQ_POWERBUS_WRITE_DATA_BUFFER_UE */ (MciFir, bit(36)) ? calloutParentProcHighThr1; /** MCIFIR[37] * MCIFIRQ_POWERBUS_WRITE_DATA_BUFFER_SUE */ (MciFir, bit(37)) ? defaultMaskedError; /** MCIFIR[38] * MCIFIRQ_HA_ILLEGAL_CONSUMER_ACCESS_ERROR */ (MciFir, bit(38)) ? callout2ndLvlDumpSw; /** MCIFIR[39] * MCIFIRQ_HA_ILLEGAL_PRODUCER_ACCESS_ERROR */ (MciFir, bit(39)) ? callout2ndLvlDumpSw; /** MCIFIR[40] * CHANNEL TIMEOUT ERROR */ (MciFir, bit(40)) ? calloutDmiBusTh1; /** MCIFIR[41] * CENTAUR FAULT LINE */ (MciFir, bit(41)) ? defaultMaskedError; /** MCIFIR[42] * MCS WAT */ (MciFir, bit(42)) ? defaultMaskedError; /** MCIFIR[43] * INVALID ADDRESS */ (MciFir, bit(43)) ? defaultMaskedError; /** MCIFIR[44] * MCIFIRQ_COMMAND_AND_LIST_TIMEOUT */ (MciFir, bit(44)) ? defaultMaskedError; /** MCIFIR[45] * MCIFIRQ_MPIPL_OR_FLR_WRITE_SUE */ (MciFir, bit(45)) ? defaultMaskedError; /** MCIFIR[46] * MCIFIRQ_INVALID_CENTAUR_BYPASS */ (MciFir, bit(46)) ? calloutDmiBusSelfLowConnMed; /** MCIFIR[47] * MCS WRITE DATAFLOW SUE */ (MciFir, bit(47)) ? defaultMaskedError; /** MCIFIR[48] * MCIFIRQ_BAD_MDI0_UPDATE */ (MciFir, bit(48)) ? mcifirBit48; /** MCIFIR[49] * MCIFIRQ_INCONSISTENT_SF_STAT */ (MciFir, bit(49)) ? mcifirBit49; /** MCIFIR[50:51] * RESERVED */ (MciFir, bit(50|51)) ? defaultMaskedError; /** MCIFIR[52] * MCIFIRQ_INTERNAL_SCOM_ERROR */ (MciFir, bit(52)) ? defaultMaskedError; /** MCIFIR[53] * MCIFIRQ_INTERNAL_SCOM_ERROR_CLONE */ (MciFir, bit(53)) ? defaultMaskedError; /** MCIFIR[54:63] * RESERVED */ (MciFir, bit( 54|55|56|57|58|59| 60|61|62|63 )) ? defaultMaskedError; }; ############################################################################## # # # # ### # # # # ## ##### ### ### # # # # # # ### ### ### ### # # # # # # # # # # ## # # # # # # # # # # # ####### # # # # # # # # # # ##### ### ### ## ### # # # # # # # # # # # ## # # # # # # # # # # # # # ## # ### ### # # ### ### # # ### ### ### ### # # # ############################################################################## # Include the common action set. .include "CommonActions.rule" actionclass calloutProcHighThr5PerHr { callout(connected(TYPE_PROC),MRU_HIGH); threshold5phour; }; /** Callout the connected Centaur, threshold 1 */ actionclass calloutConnCenTh1 { callout(connected(TYPE_MEMBUF), MRU_MED); threshold1; }; /** Callout the DMI bus (MEDA) */ actionclass calloutDmiBus { calloutSelfMedA; callout(connected(TYPE_MEMBUF), MRU_MEDA); funccall("calloutInterface_dmi"); }; /** Clear MBS SecondaryBits and calloutDmiBusTh1 */ actionclass clearSecMbsBitsCalloutDmiBusTh1 { funccall("ClearMbsSecondaryBits"); calloutDmiBusTh1; }; /** Callout the DMI bus (MEDA), threshold 1*/ actionclass calloutDmiBusTh1 { calloutDmiBus; threshold1; }; /** Callout the DMI bus (MEDA) and 2nd Level Support (LOW), threshold 1 */ actionclass calloutDmiBusAndLvl2Th1 { calloutDmiBusTh1; callout2ndLvlLow; }; actionclass CalloutDmiBusAndThr2pd { calloutDmiBus; threshold2pday; }; /** If there is a lane repair attention, do nothing. Otherwise, callout DMI bus with threshold of 2/day. */ actionclass analyzeSpareBitAndThr { try( funccall("checkSpareBit"), CalloutDmiBusAndThr2pd ); }; /** The plugin checks if the Proc is either Murano DD2 or Venice DD1. If neither, then callout thresholdAndMask_self and change signature to DD1: MCIFIRQ_INTERNAL_SCOM_ERROR. */ actionclass mcifirBit48 { threshold32pday; try( funccall("dd1mcifirBit48"), calloutDmiBusSelfLowConnMed ); }; /** The plugin checks if the Proc is either Murano DD2 or Venice DD1. If neither, then callout thresholdAndMask_self and change signature to DD1: MCIFIRQ_INTERNAL_SCOM_ERROR_CLONE. */ actionclass mcifirBit49 { threshold32pday; try( funccall("dd1mcifirBit49"), calloutDmiBusSelfLowConnMed ); }; /** Callout MCS Low and Centaur High */ actionclass calloutDmiBusSelfLowConnMed { calloutSelfLow; callout(connected(TYPE_MEMBUF), MRU_MED); funccall("calloutInterface_dmi"); threshold1; }; /** Handles memory mirror action event */ actionclass handleMirrorAction { calloutSelfMed; threshold( field(33 / 30 min) ); funccall( "handleMirrorAction" ); };